\r
// extern m68ki_cpu_core m68ki_cpu;\r
\r
-extern int counter75hz;\r
-\r
\r
static u32 m68k_reg_read16(u32 a)\r
{\r
return;\r
case 1:\r
d &= 3;\r
- if (!(d&1)) PicoMCD |= 2; // reset pending, needed to be sure we fetch the right vectors on reset\r
+ if (!(d&1)) Pico_mcd->m.state_flags |= 1; // reset pending, needed to be sure we fetch the right vectors on reset\r
if ( (Pico_mcd->m.busreq&1) != (d&1)) dprintf("m68k: s68k reset %i", !(d&1));\r
if ( (Pico_mcd->m.busreq&2) != (d&2)) dprintf("m68k: s68k brq %i", (d&2)>>1);\r
- if ((PicoMCD&2) && (d&3)==1) {\r
+ if ((Pico_mcd->m.state_flags&1) && (d&3)==1) {\r
SekResetS68k(); // S68k comes out of RESET or BRQ state\r
- PicoMCD&=~2;\r
+ Pico_mcd->m.state_flags&=~1;\r
dprintf("m68k: resetting s68k, cycles=%i", SekCyclesLeft);\r
}\r
Pico_mcd->m.busreq = d;\r
dprintf("s68k irq mask: %02x", d);\r
if ((d&(1<<4)) && (Pico_mcd->s68k_regs[0x37]&4) && !(Pico_mcd->s68k_regs[0x33]&(1<<4))) {\r
CDD_Export_Status();\r
- // counter75hz = 0; // ???\r
}\r
break;\r
case 0x34: // fader\r
Pico_mcd->s68k_regs[0x37] = d&7;\r
if ((d&4) && !(d_old&4)) {\r
CDD_Export_Status();\r
- // counter75hz = 0; // ???\r
}\r
return;\r
}\r