}
#ifdef EMU_M68K
-static int SekIntAckS68k(int level)
+static int SekIntAckS68kM(int level)
{
int level_new = new_irq_level(level);
dprintf("s68kACK %i -> %i", level, level_new);
#endif
#ifdef EMU_C68K
-// interrupt acknowledgment
-static void SekIntAckS68k(int level)
+// interrupt acknowledgement
+static int SekIntAckS68k(int level)
{
int level_new = new_irq_level(level);
dprintf("s68kACK %i -> %i", level, level_new);
PicoCpuS68k.irq = level_new;
+ return CYCLONE_INT_ACK_AUTOVECTOR;
}
-static void SekResetAck()
+static void SekResetAckS68k(void)
{
dprintf("s68k: Reset encountered @ %06x", SekPcS68k);
}
-static int SekUnrecognizedOpcode()
+static int SekUnrecognizedOpcodeS68k(void)
{
unsigned int pc, op;
pc = SekPcS68k;
-int SekInitS68k()
+PICO_INTERNAL int SekInitS68k()
{
#ifdef EMU_C68K
// CycloneInit();
memset(&PicoCpuS68k,0,sizeof(PicoCpuS68k));
PicoCpuS68k.IrqCallback=SekIntAckS68k;
- PicoCpuS68k.ResetCallback=SekResetAck;
- PicoCpuS68k.UnrecognizedCallback=SekUnrecognizedOpcode;
+ PicoCpuS68k.ResetCallback=SekResetAckS68k;
+ PicoCpuS68k.UnrecognizedCallback=SekUnrecognizedOpcodeS68k;
#endif
#ifdef EMU_M68K
{
m68k_set_context(&PicoS68kCPU);
m68k_set_cpu_type(M68K_CPU_TYPE_68000);
m68k_init();
- m68k_set_int_ack_callback(SekIntAckS68k);
+ m68k_set_int_ack_callback(SekIntAckS68kM);
// m68k_pulse_reset(); // not yet, memmap is not set up
m68k_set_context(oldcontext);
}
}
// Reset the 68000:
-int SekResetS68k()
+PICO_INTERNAL int SekResetS68k()
{
if (Pico.rom==NULL) return 1;
#ifdef EMU_C68K
- PicoCpuS68k.stopped=0;
+ PicoCpuS68k.state_flags=0;
PicoCpuS68k.osp=0;
PicoCpuS68k.srh =0x27; // Supervisor mode
PicoCpuS68k.flags=4; // Z set
void *oldcontext = m68ki_cpu_p;
m68k_set_context(&PicoS68kCPU);
+ m68ki_cpu.sp[0]=0;
+ m68k_set_irq(0);
m68k_pulse_reset();
m68k_set_context(oldcontext);
}
return 0;
}
-int SekInterruptS68k(int irq)
+PICO_INTERNAL int SekInterruptS68k(int irq)
{
int irqs, real_irq = 1;
Pico_mcd->m.s68k_pend_ints |= 1 << irq;