\r
static FILE *AsmFile=NULL;\r
\r
-static int CycloneVer=0x0087; // Version number of library\r
+static int CycloneVer=0x0088; // Version number of library\r
int *CyJump=NULL; // Jump table\r
int ms=USE_MS_SYNTAX; // If non-zero, output in Microsoft ARMASM format\r
char *Narm[4]={ "b", "h","",""}; // Normal ARM Extensions for operand sizes 0,1,2\r
}\r
#endif\r
\r
-// trashes all temp regs\r
-static void PrintException(int ints)\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+static void AddressErrorWrapper(char rw, char *dataprg, int iw)\r
{\r
- if(!ints) {\r
- ot(" ;@ Cause an Exception - Vector address in r0\n");\r
- ot(" mov r11,r0\n");\r
- }\r
-\r
- ot(" ldr r0,[r7,#0x44] ;@ Get SR high\n");\r
- ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
- ot(" tst r0,#0x20\n");\r
- ot(";@ get our SP:\n");\r
- ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
- ot(" ldreq r1,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
- ot(" streq r0,[r7,#0x48]\n");\r
- ot(" moveq r0,r1\n");\r
-\r
- ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
- ot(";@ Push r1 onto stack\n");\r
- ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
- ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
- MemHandler(1,2);\r
- OpPushSr(1);\r
-\r
- ot(" mov r0,r11\n");\r
- ot(";@ Read IRQ Vector:\n");\r
- MemHandler(0,2);\r
- if(ints) {\r
- ot(" tst r0,r0 ;@ uninitialized int vector?\n");\r
- ot(" moveq r0,#0x3c\n");\r
- ot(" moveq lr,pc\n");\r
- ot(" ldreq pc,[r7,#0x70] ;@ Call read32(r0) handler\n");\r
- }\r
-#if USE_CHECKPC_CALLBACK\r
- ot(" add r0,r0,r10 ;@ r0 = Memory Base + New PC\n");\r
- ot(" mov lr,pc\n");\r
- ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
- ot(" mov r4,r0\n");\r
-#else\r
- ot(" add r4,r0,r10 ;@ r4 = Memory Base + New PC\n");\r
-#endif\r
+ ot("ExceptionAddressError_%c_%s%s\n", rw, dataprg, ms?"":":");\r
+ ot(" ldr r1,[r7,#0x44]\n");\r
+ ot(" mov r10,#0x%02x\n", iw);\r
+ ot(" mov r11,r0\n");\r
+ ot(" tst r1,#0x20\n");\r
+ ot(" orrne r10,r10,#4\n");\r
+ ot(" b ExceptionAddressError\n");\r
ot("\n");\r
-\r
- if(!ints) {\r
- ot(" ldr r0,[r7,#0x44] ;@ Get SR high\n");\r
- ot(" bic r0,r0,#0xd8 ;@ clear trace and unused flags\n");\r
- ot(" orr r0,r0,#0x20 ;@ set supervisor mode\n");\r
- ot(" strb r0,[r7,#0x44]\n");\r
- }\r
}\r
+#endif\r
\r
void FlushPC(void)\r
{\r
\r
static void PrintFramework()\r
{\r
+ int state_flags_to_check = 1; // stopped\r
+#if EMULATE_TRACE\r
+ state_flags_to_check |= 2; // tracing\r
+#endif\r
+#if EMULATE_HALT\r
+ state_flags_to_check |= 0x10; // halted\r
+#endif\r
+\r
ot(";@ --------------------------- Framework --------------------------\n");\r
if (ms) ot("CycloneRun\n");\r
else ot("CycloneRun:\n");\r
ot(" mov r9,r9,lsl #28 ;@ r9 = Flags 0xf0000000, cpsr format\n");\r
ot(" ;@ r10 = Source value / Memory Base\n");\r
ot("\n");\r
+#if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE\r
+ ot(" mov r2,#0\n");\r
+ ot(" str r2,[r7,#0x98] ;@ clear custom CycloneEnd\n");\r
+#endif\r
ot(";@ CheckInterrupt:\n");\r
ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r
ot(" beq NoInts0\n");\r
ot(" bgt CycloneDoInterrupt\n");\r
ot("NoInts0%s\n", ms?"":":");\r
ot("\n");\r
- ot(";@ Check if our processor is in stopped state and jump to opcode handler if not\n");\r
- ot(" ldr r0,[r7,#0x58]\n");\r
+ ot(";@ Check if our processor is in special state\n");\r
+ ot(";@ and jump to opcode handler if not\n");\r
+ ot(" ldr r0,[r7,#0x58] ;@ state_flags\n");\r
ot(" ldrh r8,[r4],#2 ;@ Fetch first opcode\n");\r
- ot(" tst r0,r0 ;@ stopped?\n");\r
- ot(" bne CycloneStopped\n");\r
- ot(" ldr pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot(" tst r0,#0x%02x ;@ special state?\n", state_flags_to_check);\r
+ ot(" ldreq pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot("\n");\r
+ ot("CycloneSpecial%s\n", ms?"":":");\r
+#if EMULATE_TRACE\r
+ ot(" tst r0,#2 ;@ tracing?\n");\r
+ ot(" bne CycloneDoTrace\n");\r
+#endif\r
+ ot(";@ stopped or halted\n");\r
+ ot(" mov r5,#0\n");\r
+ ot(" str r5,[r7,#0x5C] ;@ eat all cycles\n");\r
+ ot(" ldmia sp!,{r4-r11,pc} ;@ we are stopped, do nothing!\n");\r
ot("\n");\r
ot("\n");\r
\r
ot("CycloneEnd%s\n", ms?"":":");\r
ot(" sub r4,r4,#2\n");\r
ot("CycloneEndNoBack%s\n", ms?"":":");\r
-#if (CYCLONE_FOR_GENESIS == 2)\r
- ot(" ldr r1,[r7,#0x54]\n");\r
+#if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE\r
+ ot(" ldr r1,[r7,#0x98]\n");\r
ot(" mov r9,r9,lsr #28\n");\r
ot(" tst r1,r1\n");\r
ot(" bxne r1 ;@ jump to alternative CycloneEnd\n");\r
ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
ot(" strb r9,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
ot(" ldmia sp!,{r4-r11,pc}\n");\r
+ ltorg();\r
ot("\n");\r
- ot("CycloneStopped%s\n", ms?"":":");\r
- ot(" mov r5,#0\n");\r
- ot(" str r5,[r7,#0x5C] ;@ eat all cycles\n");\r
- ot(" ldmia sp!,{r4-r11,pc} ;@ we are stopped, do nothing!\n");\r
ot("\n");\r
\r
- ltorg();\r
-\r
+ ot("CycloneInit%s\n", ms?"":":");\r
#if COMPRESS_JUMPTABLE\r
- ot(";@ uncompress jump table\n");\r
- if (ms) ot("CycloneInit\n");\r
- else ot("CycloneInit:\n");\r
- ot(" ldr r12,=CycloneJumpTab\n");\r
- ot(" add r0,r12,#0xe000*4 ;@ ctrl code pointer\n");\r
- ot(" ldr r1,[r0,#-4]\n");\r
- ot(" tst r1,r1\n");\r
- ot(" movne pc,lr ;@ already uncompressed\n");\r
- ot(" add r3,r12,#0xa000*4 ;@ handler table pointer, r12=dest\n");\r
- ot("unc_loop%s\n", ms?"":":");\r
- ot(" ldrh r1,[r0],#2\n");\r
- ot(" and r2,r1,#0xf\n");\r
- ot(" bic r1,r1,#0xf\n");\r
- ot(" ldr r1,[r3,r1,lsr #2] ;@ r1=handler\n");\r
- ot(" cmp r2,#0xf\n");\r
- ot(" addeq r2,r2,#1 ;@ 0xf is really 0x10\n");\r
- ot(" tst r2,r2\n");\r
- ot(" ldreqh r2,[r0],#2 ;@ counter is in next word\n");\r
- ot(" tst r2,r2\n");\r
- ot(" beq unc_finish ;@ done decompressing\n");\r
- ot(" tst r1,r1\n");\r
- ot(" addeq r12,r12,r2,lsl #2 ;@ 0 handler means we should skip those bytes\n");\r
- ot(" beq unc_loop\n");\r
- ot("unc_loop_in%s\n", ms?"":":");\r
- ot(" subs r2,r2,#1\n");\r
- ot(" str r1,[r12],#4\n");\r
- ot(" bgt unc_loop_in\n");\r
- ot(" b unc_loop\n");\r
- ot("unc_finish%s\n", ms?"":":");\r
- ot(" ldr r12,=CycloneJumpTab\n");\r
- ot(" ;@ set a-line and f-line handlers\n");\r
- ot(" add r0,r12,#0xa000*4\n");\r
- ot(" ldr r1,[r0,#4] ;@ a-line handler\n");\r
- ot(" ldr r3,[r0,#8] ;@ f-line handler\n");\r
- ot(" mov r2,#0x1000\n");\r
- ot("unc_fill3%s\n", ms?"":":");\r
- ot(" subs r2,r2,#1\n");\r
- ot(" str r1,[r0],#4\n");\r
- ot(" bgt unc_fill3\n");\r
- ot(" add r0,r12,#0xf000*4\n");\r
- ot(" mov r2,#0x1000\n");\r
- ot("unc_fill4%s\n", ms?"":":");\r
- ot(" subs r2,r2,#1\n");\r
- ot(" str r3,[r0],#4\n");\r
- ot(" bgt unc_fill4\n");\r
- ot(" bx lr\n");\r
- ltorg();\r
- ot("\n");\r
+ ot(";@ decompress jump table\n");\r
+ ot(" ldr r12,=CycloneJumpTab\n");\r
+ ot(" add r0,r12,#0xe000*4 ;@ ctrl code pointer\n");\r
+ ot(" ldr r1,[r0,#-4]\n");\r
+ ot(" tst r1,r1\n");\r
+ ot(" movne pc,lr ;@ already uncompressed\n");\r
+ ot(" add r3,r12,#0xa000*4 ;@ handler table pointer, r12=dest\n");\r
+ ot("unc_loop%s\n", ms?"":":");\r
+ ot(" ldrh r1,[r0],#2\n");\r
+ ot(" and r2,r1,#0xf\n");\r
+ ot(" bic r1,r1,#0xf\n");\r
+ ot(" ldr r1,[r3,r1,lsr #2] ;@ r1=handler\n");\r
+ ot(" cmp r2,#0xf\n");\r
+ ot(" addeq r2,r2,#1 ;@ 0xf is really 0x10\n");\r
+ ot(" tst r2,r2\n");\r
+ ot(" ldreqh r2,[r0],#2 ;@ counter is in next word\n");\r
+ ot(" tst r2,r2\n");\r
+ ot(" beq unc_finish ;@ done decompressing\n");\r
+ ot(" tst r1,r1\n");\r
+ ot(" addeq r12,r12,r2,lsl #2 ;@ 0 handler means we should skip those bytes\n");\r
+ ot(" beq unc_loop\n");\r
+ ot("unc_loop_in%s\n", ms?"":":");\r
+ ot(" subs r2,r2,#1\n");\r
+ ot(" str r1,[r12],#4\n");\r
+ ot(" bgt unc_loop_in\n");\r
+ ot(" b unc_loop\n");\r
+ ot("unc_finish%s\n", ms?"":":");\r
+ ot(" ldr r12,=CycloneJumpTab\n");\r
+ ot(" ;@ set a-line and f-line handlers\n");\r
+ ot(" add r0,r12,#0xa000*4\n");\r
+ ot(" ldr r1,[r0,#4] ;@ a-line handler\n");\r
+ ot(" ldr r3,[r0,#8] ;@ f-line handler\n");\r
+ ot(" mov r2,#0x1000\n");\r
+ ot("unc_fill3%s\n", ms?"":":");\r
+ ot(" subs r2,r2,#1\n");\r
+ ot(" str r1,[r0],#4\n");\r
+ ot(" bgt unc_fill3\n");\r
+ ot(" add r0,r12,#0xf000*4\n");\r
+ ot(" mov r2,#0x1000\n");\r
+ ot("unc_fill4%s\n", ms?"":":");\r
+ ot(" subs r2,r2,#1\n");\r
+ ot(" str r3,[r0],#4\n");\r
+ ot(" bgt unc_fill4\n");\r
+ ot(" bx lr\n");\r
+ ltorg();\r
#else\r
- ot(";@ do nothing\n");\r
- if (ms) ot("CycloneInit\n");\r
- else ot("CycloneInit:\n");\r
- ot(" bx lr\n");\r
- ot("\n");\r
+ ot(";@ do nothing\n");\r
+ ot(" bx lr\n");\r
#endif\r
+ ot("\n");\r
+\r
+ // --------------\r
// 68k: XNZVC, ARM: NZCV\r
- if (ms) ot("CycloneSetSr\n");\r
- else ot("CycloneSetSr:\n");\r
+ ot("CycloneSetSr%s\n", ms?"":":");\r
ot(" mov r2,r1,lsr #8\n");\r
- ot(" ldrb r3,[r0,#0x44] ;@ get SR high\n");\r
- ot(" eor r3,r3,r2\n");\r
- ot(" tst r3,#0x20\n");\r
- ot(" and r2,r2,#0xa7 ;@ only nonzero bits\n");\r
+// ot(" ldrb r3,[r0,#0x44] ;@ get SR high\n");\r
+// ot(" eor r3,r3,r2\n");\r
+// ot(" tst r3,#0x20\n");\r
+#if EMULATE_TRACE\r
+ ot(" and r2,r2,#0xa7 ;@ only defined bits\n");\r
+#else\r
+ ot(" and r2,r2,#0x27 ;@ only defined bits\n");\r
+#endif\r
ot(" strb r2,[r0,#0x44] ;@ set SR high\n");\r
- ot(" bne setsr_noswap\n");\r
- ot(" ldr r2,[r0,#0x3C] ;@ Get A7\n");\r
- ot(" ldr r3,[r0,#0x48] ;@ Get OSP\n");\r
- ot(" str r3,[r0,#0x3C]\n");\r
- ot(" str r2,[r0,#0x48]\n");\r
- ot("setsr_noswap%s\n",ms?"":":");\r
ot(" mov r2,r1,lsl #25\n");\r
ot(" str r2,[r0,#0x4c] ;@ the X flag\n");\r
ot(" bic r2,r1,#0xf3\n");\r
ot(" bx lr\n");\r
ot("\n");\r
\r
- if (ms) ot("CycloneGetSr\n");\r
- else ot("CycloneGetSr:\n");\r
+ // --------------\r
+ ot("CycloneGetSr%s\n", ms?"":":");\r
ot(" ldrb r1,[r0,#0x46] ;@ flags\n");\r
ot(" bic r2,r1,#0xf3\n");\r
ot(" tst r1,#1\n");\r
ot(" bx lr\n");\r
ot("\n");\r
\r
- if (ms) ot("CycloneSetRealTAS\n");\r
- else ot("CycloneSetRealTAS:\n");\r
+ // --------------\r
+ ot("CyclonePack%s\n", ms?"":":");\r
+ ot(" stmfd sp!,{r4,r5,lr}\n");\r
+ ot(" mov r4,r0\n");\r
+ ot(" mov r5,r1\n");\r
+ ot(" mov r3,#16\n");\r
+ ot(";@ 0x00-0x3f: DA registers\n");\r
+ ot("c_pack_loop%s\n",ms?"":":");\r
+ ot(" ldr r1,[r0],#4\n");\r
+ ot(" subs r3,r3,#1\n");\r
+ ot(" str r1,[r5],#4\n");\r
+ ot(" bne c_pack_loop\n");\r
+ ot(";@ 0x40: PC\n");\r
+ ot(" ldr r0,[r4,#0x40] ;@ PC + Memory Base\n");\r
+ ot(" ldr r1,[r4,#0x60] ;@ Memory base\n");\r
+ ot(" sub r0,r0,r1\n");\r
+ ot(" str r0,[r5],#4\n");\r
+ ot(";@ 0x44: SR\n");\r
+ ot(" mov r0,r4\n");\r
+ ot(" bl CycloneGetSr\n");\r
+ ot(" strh r0,[r5],#2\n");\r
+ ot(";@ 0x46: IRQ level\n");\r
+ ot(" ldrb r0,[r4,#0x47]\n");\r
+ ot(" strb r0,[r5],#2\n");\r
+ ot(";@ 0x48: other SP\n");\r
+ ot(" ldr r0,[r4,#0x48]\n");\r
+ ot(" str r0,[r5],#4\n");\r
+ ot(";@ 0x4c: CPU state flags\n");\r
+ ot(" ldr r0,[r4,#0x58]\n");\r
+ ot(" str r0,[r5],#4\n");\r
+ ot(" ldmfd sp!,{r4,r5,pc}\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+ ot("CycloneUnpack%s\n", ms?"":":");\r
+ ot(" stmfd sp!,{r4,r5,lr}\n");\r
+ ot(" mov r4,r0\n");\r
+ ot(" mov r5,r1\n");\r
+ ot(" mov r3,#16\n");\r
+ ot(";@ 0x00-0x3f: DA registers\n");\r
+ ot("c_unpack_loop%s\n",ms?"":":");\r
+ ot(" ldr r1,[r5],#4\n");\r
+ ot(" subs r3,r3,#1\n");\r
+ ot(" str r1,[r0],#4\n");\r
+ ot(" bne c_unpack_loop\n");\r
+ ot(";@ 0x40: PC\n");\r
+ ot(" ldr r0,[r5],#4 ;@ PC\n");\r
+#if USE_CHECKPC_CALLBACK\r
+ ot(" mov r1,#0\n");\r
+ ot(" str r1,[r4,#0x60] ;@ Memory base\n");\r
+ ot(" mov lr,pc\n");\r
+ ot(" ldr pc,[r4,#0x64] ;@ Call checkpc()\n");\r
+#else\r
+ ot(" ldr r1,[r4,#0x60] ;@ Memory base\n");\r
+ ot(" add r0,r0,r1 ;@ r0 = Memory Base + New PC\n");\r
+#endif\r
+ ot(" str r0,[r4,#0x40] ;@ PC + Memory Base\n");\r
+ ot(";@ 0x44: SR\n");\r
+ ot(" ldrh r1,[r5],#2\n");\r
+ ot(" mov r0,r4\n");\r
+ ot(" bl CycloneSetSr\n");\r
+ ot(";@ 0x46: IRQ level\n");\r
+ ot(" ldrb r0,[r5],#2\n");\r
+ ot(" strb r0,[r4,#0x47]\n");\r
+ ot(";@ 0x48: other SP\n");\r
+ ot(" ldr r0,[r5],#4\n");\r
+ ot(" str r0,[r4,#0x48]\n");\r
+ ot(";@ 0x4c: CPU state flags\n");\r
+ ot(" ldr r0,[r5],#4\n");\r
+ ot(" str r0,[r4,#0x58]\n");\r
+ ot(" ldmfd sp!,{r4,r5,pc}\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+ ot("CycloneFlushIrq%s\n", ms?"":":");\r
+ ot(" ldr r1,[r0,#0x44] ;@ Get SR high T_S__III and irq level\n");\r
+ ot(" mov r2,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r
+ ot(" cmp r2,#6 ;@ irq>6 ?\n");\r
+ ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
+ ot(" cmple r2,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
+ ot(" movle r0,#0\n");\r
+ ot(" bxle lr ;@ no ints\n");\r
+ ot("\n");\r
+ ot(" stmdb sp!,{r4,r5,r7-r11,lr}\n");\r
+ ot(" mov r7,r0\n");\r
+ ot(" mov r0,r2\n");\r
+ ot(" ldrb r9,[r7,#0x46] ;@ r9 = Flags (NZCV)\n");\r
+ ot(" mov r5,#0\n");\r
+ ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");\r
+ ot(" mov r9,r9,lsl #28 ;@ r9 = Flags 0xf0000000, cpsr format\n");\r
+ ot(" adr r2,CycloneFlushIrqEnd\n");\r
+ ot(" str r2,[r7,#0x98] ;@ set custom CycloneEnd\n");\r
+ ot(" b CycloneDoInterrupt\n");\r
+ ot("\n");\r
+ ot("CycloneFlushIrqEnd%s\n", ms?"":":");\r
+ ot(" rsb r0,r5,#0\n");\r
+ ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");\r
+ ot(" strb r9,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
+ ot(" ldmia sp!,{r4,r5,r7-r11,lr}\n");\r
+ ot(" bx lr\n");\r
+ ot("\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+ ot("CycloneSetRealTAS%s\n", ms?"":":");\r
#if (CYCLONE_FOR_GENESIS == 2)\r
ot(" ldr r12,=CycloneJumpTab\n");\r
ot(" tst r0,r0\n");\r
ChangeTAS(0);\r
ot(" bx lr\n");\r
ltorg();\r
- ot("\n");\r
#else\r
ot(" bx lr\n");\r
- ot("\n");\r
#endif\r
+ ot("\n");\r
\r
- ot(";@ DoInterrupt - r0=IRQ number\n");\r
+ // --------------\r
+ ot(";@ DoInterrupt - r0=IRQ level\n");\r
ot("CycloneDoInterruptGoBack%s\n", ms?"":":");\r
ot(" sub r4,r4,#2\n");\r
ot("CycloneDoInterrupt%s\n", ms?"":":");\r
- ot(";@ Get IRQ Vector address:\n");\r
- ot(" mov r0,r0,asl #2\n");\r
- ot(" add r11,r0,#0x60\n");\r
- PrintException(1);\r
- \r
- ot(" ldrb r0,[r7,#0x47] ;@ IRQ\n");\r
- ot(" mov r2,#0\n");\r
- ot(" orr r1,r0,#0x20 ;@ Supervisor mode + IRQ number\n");\r
- ot(" strb r1,[r7,#0x44] ;@ Put SR high\n");\r
-\r
- ot(";@ Clear stopped states:\n");\r
+ ot(" bic r8,r8,#0xff000000\n");\r
+ ot(" orr r8,r8,r0,lsl #29 ;@ abuse r8\n");\r
+\r
+ // Steps are from "M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL", p. 6-4\r
+ // but their order is based on http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r
+ // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
+ ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
+ ot(" and r0,r0,#7\n");\r
+ ot(" orr r3,r0,#0x20 ;@ Supervisor mode + IRQ level\n");\r
+ ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+ ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");\r
+#endif\r
ot(" str r2,[r7,#0x58]\n");\r
+ ot(" ldrb r10,[r7,#0x44] ;@ Get old SR high\n");\r
+ ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
+ ot("\n");\r
+\r
+ // 3. Save the current processor context.\r
+ ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" ldr r11,[r7,#0x3c] ;@ Get A7\n");\r
+ ot(" tst r10,#0x20\n");\r
+ ot(";@ get our SP:\n");\r
+ ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
+ ot(" streq r11,[r7,#0x48]\n");\r
+ ot(" moveq r11,r2\n");\r
+ ot(";@ Push old PC onto stack\n");\r
+ ot(" sub r0,r11,#4 ;@ Predecremented A7\n");\r
+ ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
+ MemHandler(1,2);\r
+ ot(";@ Push old SR:\n");\r
+ ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
+ ot(" mov r1,r9,lsr #28 ;@ ____NZCV\n");\r
+ ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
+ ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
+ ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
+ ot(" and r0,r0,#0x20000000\n");\r
+ ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
+ ot(" orr r1,r1,r10,lsl #8 ;@ Include old SR high\n");\r
+ ot(" sub r0,r11,#6 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0); // already checked for address error by prev MemHandler\r
ot("\n");\r
+\r
+ // 2. Obtain the exception vector.\r
+ ot(" mov r11,r8,lsr #29\n");\r
+ ot(" mov r0,r11\n");\r
#if USE_INT_ACK_CALLBACK\r
+ ot(";@ call IrqCallback if it is defined\n");\r
#if INT_ACK_NEEDS_STUFF\r
ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
ot(" mov r1,r9,lsr #28\n");\r
ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
#endif\r
- ot(" ldr r11,[r7,#0x8c] ;@ IrqCallback\n");\r
- ot(" tst r11,r11\n");\r
- ot(" movne lr,pc\n");\r
- ot(" movne pc,r11 ;@ call IrqCallback if it is defined\n");\r
-#if INT_ACK_CHANGES_STUFF\r
+ ot(" ldr r3,[r7,#0x8c] ;@ IrqCallback\n");\r
+ ot(" add lr,pc,#4*3\n");\r
+ ot(" tst r3,r3\n");\r
+ ot(" streqb r3,[r7,#0x47] ;@ just clear IRQ if there is no callback\n");\r
+ ot(" mvneq r0,#0 ;@ and simulate -1 return\n");\r
+ ot(" bxne r3\n");\r
+#if INT_ACK_CHANGES_CYCLES\r
ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
- ot(" ldrb r9,[r7,#0x46] ;@ r9 = Load Flags (NZCV)\n");\r
- ot(" mov r9,r9,lsl #28\n");\r
- ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
#endif\r
+ ot(";@ get IRQ vector address:\n");\r
+ ot(" cmn r0,#1 ;@ returned -1?\n");\r
+ ot(" addeq r0,r11,#0x18 ;@ use autovector then\n");\r
+ ot(" cmn r0,#2 ;@ returned -2?\n"); // should be safe as above add should never result in -2\r
+ ot(" moveq r0,#0x18 ;@ use spurious interrupt then\n");\r
#else // !USE_INT_ACK_CALLBACK\r
ot(";@ Clear irq:\n");\r
+ ot(" mov r2,#0\n");\r
ot(" strb r2,[r7,#0x47]\n");\r
+ ot(" add r0,r0,#0x18 ;@ use autovector\n");\r
+#endif\r
+ ot(" mov r0,r0,lsl #2 ;@ get vector address\n");\r
+ ot("\n");\r
+ ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(";@ Read IRQ Vector:\n");\r
+ MemHandler(0,2,0,0);\r
+ ot(" tst r0,r0 ;@ uninitialized int vector?\n");\r
+ ot(" moveq r0,#0x3c\n");\r
+ ot(" moveq lr,pc\n");\r
+ ot(" ldreq pc,[r7,#0x70] ;@ Call read32(r0) handler\n");\r
+#if USE_CHECKPC_CALLBACK\r
+ ot(" add lr,pc,#4\n");\r
+ ot(" add r0,r0,r10 ;@ r0 = Memory Base + New PC\n");\r
+ ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
+ #if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" mov r4,r0\n");\r
+ #else\r
+ ot(" bic r4,r0,#1\n");\r
+ #endif\r
+#else\r
+ ot(" add r4,r0,r10 ;@ r4 = Memory Base + New PC\n");\r
+ #if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" bic r4,r4,#1\n");\r
+ #endif\r
+#endif\r
+ ot("\n");\r
+\r
+ // 4. Obtain a new context and resume instruction processing.\r
+ // note: the obtain part was already done in previous steps\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
#endif\r
ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
ot(" subs r5,r5,#44 ;@ Subtract cycles\n");\r
ot(" b CycloneEnd\n");\r
ot("\n");\r
\r
+ // --------------\r
+ // trashes all temp regs\r
ot("Exception%s\n", ms?"":":");\r
- ot(" stmdb sp!,{lr} ;@ Preserve ARM return address\n");\r
- PrintException(0);\r
- ot(" ldmia sp!,{pc} ;@ Return\n");\r
+ ot(" ;@ Cause an Exception - Vector number in r0\n");\r
+ ot(" mov r11,lr ;@ Preserve ARM return address\n");\r
+ ot(" bic r8,r8,#0xff000000\n");\r
+ ot(" orr r8,r8,r0,lsl #24 ;@ abuse r8\n");\r
+\r
+ // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
+ ot(" ldr r10,[r7,#0x44] ;@ Get old SR high\n");\r
+ ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
+ ot(" and r3,r10,#0x27 ;@ clear trace and unused flags\n");\r
+ ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");\r
+ ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
+ ot(" str r2,[r7,#0x58]\n");\r
+ ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
+ ot("\n");\r
+\r
+ // 3. Save the current processor context.\r
+ ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
+ ot(" tst r10,#0x20\n");\r
+ ot(";@ get our SP:\n");\r
+ ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
+ ot(" streq r0,[r7,#0x48]\n");\r
+ ot(" moveq r0,r2\n");\r
+ ot(";@ Push old PC onto stack\n");\r
+ ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" sub r0,r0,#4 ;@ Predecremented A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
+ MemHandler(1,2);\r
+ ot(";@ Push old SR:\n");\r
+ ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
+ ot(" mov r1,r9,lsr #28 ;@ ____NZCV\n");\r
+ ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
+ ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
+ ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
+ ot(" and r0,r0,#0x20000000\n");\r
+ ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" orr r1,r1,r10,lsl #8 ;@ Include SR high\n");\r
+ ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0);\r
+ ot("\n");\r
+\r
+ // 2. Obtain the exception vector\r
+ ot(";@ Read Exception Vector:\n");\r
+ ot(" mov r0,r8,lsr #24\n");\r
+ ot(" mov r0,r0,lsl #2\n");\r
+ MemHandler(0,2,0,0);\r
+ ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
+#if USE_CHECKPC_CALLBACK\r
+ ot(" add lr,pc,#4\n");\r
+ ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");\r
+ ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
+ #if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" mov r4,r0\n");\r
+ #else\r
+ ot(" bic r4,r0,#1\n");\r
+ #endif\r
+#else\r
+ ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");\r
+ #if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" bic r4,r4,#1\n");\r
+ #endif\r
+#endif\r
+ ot("\n");\r
+\r
+ // 4. Resume execution.\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#endif\r
+ ot(" bx r11 ;@ Return\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+ // first some wrappers: I see no point inlining this code,\r
+ // as it will be executed in really rare cases.\r
+ AddressErrorWrapper('r', "data", 0x11);\r
+ AddressErrorWrapper('r', "prg", 0x12);\r
+ AddressErrorWrapper('w', "data", 0x01);\r
+ // there are no program writes\r
+ // cpu space is only for bus errors?\r
+ ot("ExceptionAddressError_r_prg_r4%s\n", ms?"":":");\r
+ ot(" ldr r1,[r7,#0x44]\n");\r
+ ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" mov r10,#0x12\n");\r
+ ot(" sub r11,r4,r3\n");\r
+ ot(" tst r1,#0x20\n");\r
+ ot(" orrne r10,r10,#4\n");\r
+ ot("\n");\r
+\r
+ ot("ExceptionAddressError%s\n", ms?"":":");\r
+ ot(";@ r10 - info word (without instruction/not bit), r11 - faulting address\n");\r
+\r
+ // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
+ ot(" ldrb r0,[r7,#0x44] ;@ Get old SR high\n");\r
+ ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
+ ot(" and r3,r0,#0x27 ;@ clear trace and unused flags\n");\r
+ ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");\r
+ ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
+ ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
+ ot(" tst r2,#4\n");\r
+ ot(" orrne r10,r10,#8 ;@ complete info word\n");\r
+ ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");\r
+#if EMULATE_HALT\r
+ ot(" tst r2,#8\n");\r
+ ot(" orrne r2,r2,#0x10 ;@ HALT\n");\r
+ ot(" orr r2,r2,#8 ;@ processing address error\n");\r
+ ot(" str r2,[r7,#0x58]\n");\r
+ ot(" movne r5,#0\n");\r
+ ot(" bne CycloneEndNoBack ;@ bye bye\n");\r
+#else\r
+ ot(" str r2,[r7,#0x58]\n");\r
+#endif\r
+ ot(" and r9,r9,#0xf0000000\n");\r
+ ot(" orr r9,r9,r0,lsl #4 ;@ some preparations for SR push\n");\r
+ ot("\n");\r
+\r
+ // 3. Save the current processor context + additional information.\r
+ ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
+ ot(" tst r9,#0x200\n");\r
+ ot(";@ get our SP:\n");\r
+ ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
+ ot(" streq r0,[r7,#0x48]\n");\r
+ ot(" moveq r0,r2\n");\r
+ // PC\r
+ ot(";@ Push old PC onto stack\n");\r
+ ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" sub r0,r0,#4 ;@ Predecremented A7\n");\r
+ ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,2,0,EMULATE_HALT);\r
+ // SR\r
+ ot(";@ Push old SR:\n");\r
+ ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
+ ot(" mov r1,r9,ror #28 ;@ ____NZCV\n");\r
+ ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
+ ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
+ ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
+ ot(" and r0,r0,#0x20000000\n");\r
+ ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" and r9,r9,#0xf0000000\n");\r
+ ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0);\r
+ // IR (instruction register)\r
+ ot(";@ Push IR:\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" mov r1,r8\n");\r
+ ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0);\r
+ // access address\r
+ ot(";@ Push address:\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" mov r1,r11\n");\r
+ ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,2,0,0);\r
+ // information word\r
+ ot(";@ Push info word:\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" mov r1,r10\n");\r
+ ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0);\r
+ ot("\n");\r
+\r
+ // 2. Obtain the exception vector\r
+ ot(";@ Read Exception Vector:\n");\r
+ ot(" mov r0,#0x0c\n");\r
+ MemHandler(0,2,0,0);\r
+ ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
+#if USE_CHECKPC_CALLBACK\r
+ ot(" add lr,pc,#4\n");\r
+ ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");\r
+ ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
+ ot(" mov r4,r0\n");\r
+#else\r
+ ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");\r
+#endif\r
+ ot("\n");\r
+\r
+#if EMULATE_ADDRESS_ERRORS_JUMP && EMULATE_HALT\r
+ ot(" tst r4,#1\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#else\r
+ ot(" bic r4,r4,#1\n");\r
+#endif\r
+\r
+ // 4. Resume execution.\r
+ ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+ ot(" subs r5,r5,#50 ;@ Subtract cycles\n");\r
+ ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot(" b CycloneEnd\n");\r
+ ot("\n");\r
+#endif\r
+\r
+ // --------------\r
+#if EMULATE_TRACE\r
+ // expects srh and irq level in r1, next opcode already fetched to r8\r
+ ot("CycloneDoTraceWithChecks%s\n", ms?"":":");\r
+ ot(" ldr r0,[r7,#0x58]\n");\r
+ ot(" cmp r5,#0\n");\r
+ ot(" orr r0,r0,#2 ;@ go to trace mode\n");\r
+ ot(" str r0,[r7,#0x58]\n");\r
+ ot(" blt CycloneEnd\n"); // should take care of situation where we come here when already tracing\r
+ ot(";@ CheckInterrupt:\n");\r
+ ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n");\r
+ ot(" beq CycloneDoTrace\n");\r
+ ot(" cmp r0,#6 ;@ irq>6 ?\n");\r
+ ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
+ ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
+ ot(" bgt CycloneDoInterruptGoBack\n");\r
+ ot("\n");\r
+\r
+ // expects next opcode to be already fetched to r8\r
+ ot("CycloneDoTrace%s\n", ms?"":":");\r
+ ot(" str r5,[r7,#0x9c] ;@ save cycles\n");\r
+ ot(" ldr r1,[r7,#0x98]\n");\r
+ ot(" mov r5,#0\n");\r
+ ot(" str r1,[r7,#0xa0]\n");\r
+ ot(" adr r0,TraceEnd\n");\r
+ ot(" str r0,[r7,#0x98] ;@ store TraceEnd as CycloneEnd hadler\n");\r
+ ot(" ldr pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot("\n");\r
+\r
+ ot("TraceEnd%s\n", ms?"":":");\r
+ ot(" ldr r2,[r7,#0x58]\n");\r
+ ot(" ldr r0,[r7,#0x9c] ;@ restore cycles\n");\r
+ ot(" ldr r1,[r7,#0xa0] ;@ old CycloneEnd handler\n");\r
+ ot(" mov r9,r9,lsl #28\n");\r
+ ot(" add r5,r0,r5\n");\r
+ ot(" str r1,[r7,#0x98]\n");\r
+ ot(";@ still tracing?\n"); // exception might have happend\r
+ ot(" tst r2,#2\n");\r
+ ot(" beq TraceDisabled\n");\r
+ ot(";@ trace exception\n");\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+ ot(" ldr r1,[r7,#0x58]\n");\r
+ ot(" mov r0,#9\n");\r
+ ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
+ ot(" str r1,[r7,#0x58]\n");\r
+#else\r
+ ot(" mov r0,#9\n");\r
+#endif\r
+ ot(" bl Exception\n");\r
+ ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+ ot(" subs r5,r5,#34 ;@ Subtract cycles\n");\r
+ ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot(" b CycloneEnd\n");\r
ot("\n");\r
+ ot("TraceDisabled%s\n", ms?"":":");\r
+ ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+ ot(" cmp r5,#0\n");\r
+ ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot(" b CycloneEnd\n");\r
+ ot("\n");\r
+#endif\r
}\r
\r
// ---------------------------------------------------------------------------\r
// Call Read(r0), Write(r0,r1) or Fetch(r0)\r
// Trashes r0-r3,r12,lr\r
-int MemHandler(int type,int size,int addrreg)\r
+int MemHandler(int type,int size,int addrreg,int need_addrerr_check)\r
{\r
int func=0;\r
func=0x68+type*0xc+(size<<2); // Find correct offset\r
ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x000000ff);\r
addrreg=0;\r
#endif\r
+\r
+#if EMULATE_ADDRESS_ERRORS_IO\r
+ if (size > 0 && need_addrerr_check)\r
+ {\r
+ ot(" add lr,pc,#4*%i\n", addrreg==0?2:3); // helps to prevent interlocks\r
+ if (addrreg != 0) ot(" mov r0,r%i\n", addrreg);\r
+ ot(" tst r0,#1 ;@ address error?\n");\r
+ switch (type) {\r
+ case 0: ot(" bne ExceptionAddressError_r_data\n"); break;\r
+ case 1: ot(" bne ExceptionAddressError_w_data\n"); break;\r
+ case 2: ot(" bne ExceptionAddressError_r_prg\n"); break;\r
+ }\r
+ }\r
+ else\r
+#endif\r
if (addrreg != 0)\r
{\r
- ot(" add lr,pc,#4\n"); // helps to prevent interlocks\r
+ ot(" add lr,pc,#4\n");\r
ot(" mov r0,r%i\n", addrreg);\r
}\r
else\r
\r
// Emit null opcode:\r
ot("Op____%s ;@ Called if an opcode is not recognised\n", ms?"":":");\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+ ot(" ldr r1,[r7,#0x58]\n");\r
ot(" sub r4,r4,#2\n");\r
+ ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
+ ot(" str r1,[r7,#0x58]\n");\r
+#else\r
+ ot(" sub r4,r4,#2\n");\r
+#endif\r
#if USE_UNRECOGNIZED_CALLBACK\r
ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
ot(" mov r1,r9,lsr #28\n");\r
ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
ot(" mov r9,r9,lsl #28\n");\r
ot(" tst r0,r0\n");\r
- ot(" moveq r0,#0x10\n");\r
+ ot(" moveq r0,#4\n");\r
ot(" bleq Exception\n");\r
#else\r
- ot(" mov r0,#0x10\n");\r
+ ot(" mov r0,#4\n");\r
ot(" bl Exception\n");\r
#endif\r
ot("\n");\r
ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
ot(" mov r9,r9,lsl #28\n");\r
ot(" tst r0,r0\n");\r
- ot(" moveq r0,#0x28\n");\r
+ ot(" moveq r0,#0x0a\n");\r
ot(" bleq Exception\n");\r
#else\r
- ot(" mov r0,#0x28\n");\r
+ ot(" mov r0,#0x0a\n");\r
ot(" bl Exception\n");\r
#endif\r
ot("\n");\r
ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
ot(" mov r9,r9,lsl #28\n");\r
ot(" tst r0,r0\n");\r
- ot(" moveq r0,#0x2c\n");\r
+ ot(" moveq r0,#0x0b\n");\r
ot(" bleq Exception\n");\r
#else\r
- ot(" mov r0,#0x2c\n");\r
+ ot(" mov r0,#0x0b\n");\r
ot(" bl Exception\n");\r
#endif\r
ot("\n");\r
{\r
int i;\r
char *name="Cyclone.s";\r
+ const char *globl=ms?"export":".global";\r
\r
// Open the assembly file\r
if (ms) name="Cyclone.asm";\r
for(i=0xa000; i<0xb000; i++) CyJump[i] = -2; // a-line emulation\r
for(i=0xf000; i<0x10000; i++) CyJump[i] = -3; // f-line emulation\r
\r
- if (ms)\r
- {\r
- ot(" area |.text|, code\n");\r
- ot(" export CycloneInit\n");\r
- ot(" export CycloneRun\n");\r
- ot(" export CycloneSetSr\n");\r
- ot(" export CycloneGetSr\n");\r
- ot(" export CycloneSetRealTAS\n");\r
- ot(" export CycloneVer\n");\r
- ot("\n");\r
- ot("CycloneVer dcd 0x%.4x\n",CycloneVer);\r
- }\r
- else\r
- {\r
- ot(" .global CycloneInit\n");\r
- ot(" .global CycloneRun\n");\r
- ot(" .global CycloneSetSr\n");\r
- ot(" .global CycloneGetSr\n");\r
- ot(" .global CycloneVer\n");\r
+ ot(ms?" area |.text|, code\n":" .text\n .align 4\n\n");\r
+ ot(" %s CycloneInit\n",globl);\r
+ ot(" %s CycloneRun\n",globl);\r
+ ot(" %s CycloneSetSr\n",globl);\r
+ ot(" %s CycloneGetSr\n",globl);\r
+ ot(" %s CycloneFlushIrq\n",globl);\r
+ ot(" %s CyclonePack\n",globl);\r
+ ot(" %s CycloneUnpack\n",globl);\r
+ ot(" %s CycloneVer\n",globl);\r
#if (CYCLONE_FOR_GENESIS == 2)\r
- ot(" .global CycloneSetRealTAS\n");\r
- ot(" .global CycloneDoInterrupt\n");\r
- ot(" .global CycloneJumpTab\n");\r
+ ot(" %s CycloneSetRealTAS\n",globl);\r
+ ot(" %s CycloneDoInterrupt\n",globl);\r
+ ot(" %s CycloneDoTrace\n",globl);\r
+ ot(" %s CycloneJumpTab\n",globl);\r
#endif\r
- ot("CycloneVer: .long 0x%.4x\n",CycloneVer);\r
- }\r
+ ot("\n");\r
+ ot(ms?"CycloneVer dcd 0x":"CycloneVer: .long 0x");\r
+ ot("%.4x\n",CycloneVer);\r
ot("\n");\r
\r
PrintFramework();\r
notaz.gp2x.de / picodrive.git / blobdiff