adjustments for CPU core changes

[picodrive.git] / cpu / Cyclone / OpBranch.cpp

diff --git a/cpu/Cyclone/OpBranch.cpp b/cpu/Cyclone/OpBranch.cpp
index c24c769..d1c2391 100644 (file)
--- a/cpu/Cyclone/OpBranch.cpp
+++ b/cpu/Cyclone/OpBranch.cpp
@@ -11,8 +11,7 @@ static void CheckPc(int reg)
   ot("  ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
   ot("  mov r4,r0\n");\r
 #else\r
-  if (reg != 4)\r
-    ot("  mov r4,r%i\n", reg);\r
+  ot("  bic r4,r%d,#1\n",reg); // we do not emulate address errors\r
 #endif\r
   ot("\n");\r
 }\r
@@ -158,11 +157,12 @@ int OpUnlk(int op)
 }\r
 \r
 // --------------------- Opcodes 0x4e70+ ---------------------\r
+// 01001110 01110ttt\r
 int Op4E70(int op)\r
 {\r
   int type=0;\r
 \r
-  type=op&7; // 01001110 01110ttt, reset/nop/stop/rte/rtd/rts/trapv/rtr\r
+  type=op&7; // reset/nop/stop/rte/rtd/rts/trapv/rtr\r
 \r
   switch (type)\r
   {\r
@@ -193,7 +193,7 @@ int Op4E70(int op)
     case 6: // trapv\r
     OpStart(op,0x10); Cycles=4;\r
     ot("  tst r9,#0x10000000\n");\r
-    ot("  subne r5,r5,#%i\n",30);\r
+    ot("  subne r5,r5,#%i\n",34);\r
     ot("  movne r0,#0x1c ;@ TRAPV exception\n");\r
     ot("  blne Exception\n");\r
     OpEnd(0x10);\r
@@ -236,17 +236,17 @@ int OpJsr(int op)
   ot(";@ Jump - Get new PC from r0\n");\r
   if (op&0x40)\r
   {\r
-    // Jmp - Get new PC from r0\r
+    // Jmp - Get new PC from r11\r
     ot("  add r0,r11,r10 ;@ Memory Base + New PC\n");\r
     ot("\n");\r
   }\r
   else\r
   {\r
     ot(";@ Jsr - Push old PC first\n");\r
-    ot("  sub r1,r4,r10 ;@ r1 = Old PC\n");\r
-    ot("  mov r1,r1,lsl #8\n");\r
     ot("  ldr r0,[r7,#0x3c]\n");\r
-    ot("  mov r1,r1,asr #8\n");\r
+    ot("  sub r1,r4,r10 ;@ r1 = Old PC\n");\r
+//    ot("  mov r1,r1,lsl #8\n");\r
+//    ot("  mov r1,r1,asr #8\n");\r
     ot(";@ Push r1 onto stack\n");\r
     ot("  sub r0,r0,#4 ;@ Predecrement A7\n");\r
     ot("  str r0,[r7,#0x3c] ;@ Save A7\n");\r
@@ -319,14 +319,25 @@ int OpDbra(int op)
 \r
     ot(";@ Check if Dn.w is -1\n");\r
     ot("  cmn r0,#1\n");\r
+\r
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA\r
+    ot("  beq DbraMin1\n");\r
     ot("\n");\r
 \r
+    ot(";@ Get Branch offset:\n");\r
+    ot("  ldrsh r0,[r4]\n");\r
+    ot("  add r0,r4,r0 ;@ r4 = New PC\n");\r
+    CheckPc(0);\r
+#else\r
+    ot("\n");\r
     ot(";@ Get Branch offset:\n");\r
     ot("  ldrnesh r0,[r4]\n");\r
     ot("  addeq r4,r4,#2 ;@ Skip branch offset\n");\r
     ot("  subeq r5,r5,#4 ;@ additional cycles\n");\r
     ot("  addne r4,r4,r0 ;@ r4 = New PC\n");\r
+    ot("  bic r4,r4,#1\n"); // we do not emulate address errors\r
     ot("\n");\r
+#endif\r
     Cycles=12-2;\r
     OpEnd();\r
   }\r
@@ -342,6 +353,18 @@ int OpDbra(int op)
     OpEnd();\r
   }\r
 \r
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA\r
+  if (op==0x51c8)\r
+  {\r
+    ot(";@ Dn.w is -1:\n");\r
+    ot("DbraMin1%s\n", ms?"":":");\r
+    ot("  add r4,r4,#2 ;@ Skip branch offset\n");\r
+    ot("\n");\r
+    Cycles=12+2;\r
+    OpEnd();\r
+  }\r
+#endif\r
+\r
   return 0;\r
 }\r
 \r
@@ -349,7 +372,7 @@ int OpDbra(int op)
 // Emit a Branch opcode 0110cccc nn  (cccc=condition)\r
 int OpBranch(int op)\r
 {\r
-  int size=0,use=0;\r
+  int size=0,use=0,checkpc=0;\r
   int offset=0;\r
   int cc=0;\r
   char *asr_r11="";\r
@@ -361,6 +384,7 @@ int OpBranch(int op)
   if (offset==0)  size=1;\r
   if (offset==-1) size=2;\r
 \r
+  if (size==2) size=0; // 000 model does not support long displacement\r
   if (size) use=op; // 16-bit or 32-bit\r
   else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches\r
 \r
@@ -414,11 +438,11 @@ int OpBranch(int op)
   if (cc==1)\r
   {\r
     ot(";@ Bsr - remember old PC\n");\r
+    ot("  ldr r2,[r7,#0x3c]\n");\r
     ot("  sub r1,r4,r10 ;@ r1 = Old PC\n");\r
     if (size) ot("  add r1,r1,#%d\n",1<<size);\r
-    ot("  mov r1,r1, lsl #8\n");\r
-    ot("  ldr r2,[r7,#0x3c]\n");\r
-    ot("  mov r1,r1, asr #8\n");\r
+//    ot("  mov r1,r1, lsl #8\n");\r
+//    ot("  mov r1,r1, asr #8\n");\r
     ot("\n");\r
     ot(";@ Push r1 onto stack\n");\r
     ot("  sub r0,r2,#4 ;@ Predecrement A7\n");\r
@@ -426,28 +450,27 @@ int OpBranch(int op)
     MemHandler(1,2);\r
     ot("\n");\r
     Cycles=18; // always 18\r
-    if (offset==0 || offset==-1)\r
-    {\r
-      ot(";@ Branch is quite far, so may be a good idea to check Memory Base+pc\n");\r
-      ot("  add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
-      CheckPc(0);\r
-    }\r
-    else\r
-      ot("  add r4,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
+  }\r
+\r
+  ot("  add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
+\r
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8\r
+  if (offset!=0 && offset!=-1) checkpc=1;\r
+#endif\r
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_16\r
+  if (offset==0)  checkpc=1;\r
+#endif\r
+#if USE_CHECKPC_CALLBACK\r
+  if (offset==-1) checkpc=1;\r
+#endif\r
+  if (checkpc)\r
+  {\r
+    CheckPc(0);\r
   }\r
   else\r
   {\r
-    if (offset==0 || offset==-1)\r
-    {\r
-      ot("  add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
-      ot(";@ Branch is quite far, so may be a good idea to check Memory Base+pc\n");\r
-      CheckPc(0);\r
-    }\r
-    else\r
-    {\r
-      ot("  add r4,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
-      ot("\n");\r
-    }\r
+    ot("  bic r4,r0,#1\n"); // we do not emulate address errors\r
+    ot("\n");\r
   }\r
 \r
   OpEnd(size?0x10:0);\r
@@ -456,7 +479,7 @@ int OpBranch(int op)
   if (cc>=2&&(op&0xff00)==0x6200)\r
   {\r
     ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");\r
-    if (size) ot("  add r4,r4,#%d\n",8<<size);\r
+    if (size) ot("  add r4,r4,#%d\n",1<<size);\r
     Cycles+=(size==1) ? 2 : -2; // Branch not taken\r
     OpEnd(0);\r
   }\r