ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
ot(" mov r4,r0\n");\r
#else\r
- if (reg != 4)\r
- ot(" mov r4,r%i\n", reg);\r
+ ot(" bic r4,r%d,#1\n",reg); // we do not emulate address errors\r
#endif\r
ot("\n");\r
}\r
OpStart(op,0x10);\r
\r
ot(";@ Get An\n");\r
- EaCalc(10, 7, 8, 2, 1);\r
- EaRead(10, 0, 8, 2, 7, 1);\r
+ EaCalc(10, 0xf, 8, 2, 1);\r
+ EaRead(10, 0, 8, 2, 0xf, 1);\r
\r
ot(" add r11,r0,#4 ;@ A7+=4\n");\r
ot("\n");\r
ot("\n");\r
ot(";@ An = value from stack:\n");\r
EaWrite(10, 0, 8, 2, 7, 1);\r
- \r
+\r
Cycles=12;\r
OpEnd(0x10);\r
return 0;\r
}\r
\r
// --------------------- Opcodes 0x4e70+ ---------------------\r
+// 01001110 01110ttt\r
int Op4E70(int op)\r
{\r
int type=0;\r
\r
- type=op&7; // 01001110 01110ttt, reset/nop/stop/rte/rtd/rts/trapv/rtr\r
+ type=op&7; // reset/nop/stop/rte/rtd/rts/trapv/rtr\r
\r
switch (type)\r
{\r
SuperChange(op);\r
CheckInterrupt(op);\r
OpEnd(0x10);\r
- SuperEnd(op);\r
return 0;\r
\r
case 5: // rts\r
case 6: // trapv\r
OpStart(op,0x10); Cycles=4;\r
ot(" tst r9,#0x10000000\n");\r
- ot(" subne r5,r5,#%i\n",30);\r
+ ot(" subne r5,r5,#%i\n",34);\r
ot(" movne r0,#0x1c ;@ TRAPV exception\n");\r
ot(" blne Exception\n");\r
OpEnd(0x10);\r
// See if we can do this opcode:\r
if (EaCanRead(sea,-1)==0) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,0);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,(op&0x40)?0:0x10);\r
ot(";@ Jump - Get new PC from r0\n");\r
if (op&0x40)\r
{\r
- // Jmp - Get new PC from r0\r
+ // Jmp - Get new PC from r11\r
ot(" add r0,r11,r10 ;@ Memory Base + New PC\n");\r
ot("\n");\r
}\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
OpStart(op);\r
\r
- if (cc>=2)\r
+ switch (cc)\r
{\r
- ot(";@ Is the condition true?\n");\r
- if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");\r
- ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
- if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000\n");\r
- ot(";@ If so, don't dbra\n");\r
- ot(" b%s DbraTrue%.4x\n",Cond[cc],op);\r
- ot("\n");\r
+ case 0: // T\r
+ case 1: // F\r
+ break;\r
+ case 2: // hi\r
+ ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");\r
+ ot(" beq DbraTrue\n\n");\r
+ break;\r
+ case 3: // ls\r
+ ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");\r
+ ot(" bne DbraTrue\n\n");\r
+ break;\r
+ default:\r
+ ot(";@ Is the condition true?\n");\r
+ ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
+ ot(";@ If so, don't dbra\n");\r
+ ot(" b%s DbraTrue\n\n",Cond[cc]);\r
+ break;\r
}\r
\r
- ot(";@ Decrement Dn.w\n");\r
- ot(" and r1,r8,#0x0007\n");\r
- ot(" mov r1,r1,lsl #2\n");\r
- ot(" ldrsh r0,[r7,r1]\n");\r
- ot(" sub r0,r0,#1\n");\r
- ot(" strh r0,[r7,r1]\n");\r
- ot("\n");\r
+ if (cc!=0)\r
+ {\r
+ ot(";@ Decrement Dn.w\n");\r
+ ot(" and r1,r8,#0x0007\n");\r
+ ot(" mov r1,r1,lsl #2\n");\r
+ ot(" ldrsh r0,[r7,r1]\n");\r
+ ot(" sub r0,r0,#1\n");\r
+ ot(" strh r0,[r7,r1]\n");\r
+ ot("\n");\r
\r
- ot(";@ Check if Dn.w is -1\n");\r
- ot(" cmps r0,#-1\n");\r
- ot(" beq DbraMin1%.4x\n",op);\r
- ot("\n");\r
+ ot(";@ Check if Dn.w is -1\n");\r
+ ot(" cmn r0,#1\n");\r
\r
- ot(";@ Get Branch offset:\n");\r
- ot(" ldrsh r0,[r4]\n");\r
- ot(" add r4,r4,r0 ;@ r4 = New PC\n");\r
- ot("\n");\r
- Cycles=12-2;\r
- OpEnd();\r
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA\r
+ ot(" beq DbraMin1\n");\r
+ ot("\n");\r
+\r
+ ot(";@ Get Branch offset:\n");\r
+ ot(" ldrsh r0,[r4]\n");\r
+ ot(" add r0,r4,r0 ;@ r4 = New PC\n");\r
+ CheckPc(0);\r
+#else\r
+ ot("\n");\r
+ ot(";@ Get Branch offset:\n");\r
+ ot(" ldrnesh r0,[r4]\n");\r
+ ot(" addeq r4,r4,#2 ;@ Skip branch offset\n");\r
+ ot(" subeq r5,r5,#4 ;@ additional cycles\n");\r
+ ot(" addne r4,r4,r0 ;@ r4 = New PC\n");\r
+ ot(" bic r4,r4,#1\n"); // we do not emulate address errors\r
+ ot("\n");\r
+#endif\r
+ Cycles=12-2;\r
+ OpEnd();\r
+ }\r
\r
- ot(";@ Dn.w is -1:\n");\r
- ot("DbraMin1%.4x%s\n", op, ms?"":":");\r
- ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
- ot("\n");\r
- Cycles=12+2;\r
- OpEnd();\r
+ //if (cc==0||cc>=2)\r
+ if (op==0x50c8)\r
+ {\r
+ ot(";@ condition true:\n");\r
+ ot("DbraTrue%s\n", ms?"":":");\r
+ ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
+ ot("\n");\r
+ Cycles=12;\r
+ OpEnd();\r
+ }\r
\r
- ot(";@ condition true:\n");\r
- ot("DbraTrue%.4x%s\n", op, ms?"":":");\r
- ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
- ot("\n");\r
- Cycles=12;\r
- OpEnd();\r
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA\r
+ if (op==0x51c8)\r
+ {\r
+ ot(";@ Dn.w is -1:\n");\r
+ ot("DbraMin1%s\n", ms?"":":");\r
+ ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
+ ot("\n");\r
+ Cycles=12+2;\r
+ OpEnd();\r
+ }\r
+#endif\r
\r
return 0;\r
}\r
// Emit a Branch opcode 0110cccc nn (cccc=condition)\r
int OpBranch(int op)\r
{\r
- int size=0,use=0;\r
+ int size=0,use=0,checkpc=0;\r
int offset=0;\r
int cc=0;\r
+ char *asr_r11="";\r
\r
offset=(char)(op&0xff);\r
cc=(op>>8)&15;\r
if (offset==0) size=1;\r
if (offset==-1) size=2;\r
\r
+ if (size==2) size=0; // 000 model does not support long displacement\r
if (size) use=op; // 16-bit or 32-bit\r
else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches\r
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
OpStart(op,size?0x10:0);\r
-\r
- ot(";@ Get Branch offset:\n");\r
- if (size) \r
- {\r
- EaCalc(0,0,0x3c,size);\r
- EaRead(0,0,0x3c,size,0);\r
- }\r
- else\r
- ot(" mov r0,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");\r
-\r
- // above code messes cycles\r
Cycles=10; // Assume branch taken\r
\r
if (cc==1) ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
\r
- if (cc>=2)\r
+ switch (cc)\r
{\r
- ot(";@ Is the condition true?\n");\r
- if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");\r
- ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
- if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000\n");\r
-\r
- ot(" b%s DontBranch%.4x\n",Cond[cc^1],op);\r
- ot("\n");\r
+ case 0: // T\r
+ case 1: // F\r
+ break;\r
+ case 2: // hi\r
+ ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");\r
+ ot(" bne BccDontBranch%i\n\n",8<<size);\r
+ break;\r
+ case 3: // ls\r
+ ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");\r
+ ot(" beq BccDontBranch%i\n\n",8<<size);\r
+ break;\r
+ default:\r
+ ot(";@ Is the condition true?\n");\r
+ ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
+ ot(" b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);\r
+ break;\r
}\r
\r
- if (size==0) ot(" mov r0,r0,asr #24 ;@ ...shift down\n\n");\r
+ if (size) \r
+ {\r
+ if (size<2)\r
+ {\r
+ ot(" ldrsh r11,[r4] ;@ Fetch Branch offset\n");\r
+ }\r
+ else\r
+ {\r
+ ot(" ldrh r2,[r4] ;@ Fetch Branch offset\n");\r
+ ot(" ldrh r11,[r4,#2]\n");\r
+ ot(" orr r11,r11,r2,lsl #16\n");\r
+ }\r
+ }\r
+ else\r
+ {\r
+ ot(" mov r11,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");\r
+ asr_r11=",asr #24";\r
+ }\r
\r
ot(";@ Branch taken - Add on r0 to PC\n");\r
\r
{\r
ot(";@ Bsr - remember old PC\n");\r
ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
+ if (size) ot(" add r1,r1,#%d\n",1<<size);\r
ot(" mov r1,r1, lsl #8\n");\r
+ ot(" ldr r2,[r7,#0x3c]\n");\r
ot(" mov r1,r1, asr #8\n");\r
ot("\n");\r
- if (size) ot(" sub r4,r4,#%d ;@ (Branch is relative to Opcode+2)\n",1<<size);\r
- ot(" ldr r2,[r7,#0x3c]\n");\r
- ot(" add r4,r4,r0 ;@ r4 = New PC\n");\r
ot(";@ Push r1 onto stack\n");\r
ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r
ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
MemHandler(1,2);\r
ot("\n");\r
Cycles=18; // always 18\r
- if (offset==0 || offset==-1)\r
- {\r
- ot(";@ Branch is quite far, so may be a good idea to check Memory Base+pc\n");\r
- CheckPc(4);\r
- }\r
+ }\r
+\r
+ ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
+\r
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8\r
+ if (offset!=0 && offset!=-1) checkpc=1;\r
+#endif\r
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_16\r
+ if (offset==0) checkpc=1;\r
+#endif\r
+#if USE_CHECKPC_CALLBACK\r
+ if (offset==-1) checkpc=1;\r
+#endif\r
+ if (checkpc)\r
+ {\r
+ CheckPc(0);\r
}\r
else\r
{\r
- if (size) ot(" sub r4,r4,#%d ;@ (Branch is relative to Opcode+2)\n",1<<size);\r
- if (offset==0 || offset==-1)\r
- {\r
- ot(" add r0,r4,r0 ;@ r4 = New PC\n");\r
- ot(";@ Branch is quite far, so may be a good idea to check Memory Base+pc\n");\r
- CheckPc(0);\r
- }\r
- else\r
- {\r
- ot(" add r4,r4,r0 ;@ r4 = New PC\n");\r
- ot("\n");\r
- }\r
+ ot(" bic r4,r0,#1\n"); // we do not emulate address errors\r
+ ot("\n");\r
}\r
\r
-\r
OpEnd(size?0x10:0);\r
\r
- if (cc>=2)\r
+ // since all "DontBranch" code is same for every size, output only once\r
+ if (cc>=2&&(op&0xff00)==0x6200)\r
{\r
- ot("DontBranch%.4x%s\n", op, ms?"":":");\r
- Cycles+=(size==1)? 2 : -2; // Branch not taken\r
- OpEnd(size?0x10:0);\r
+ ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");\r
+ if (size) ot(" add r4,r4,#%d\n",1<<size);\r
+ Cycles+=(size==1) ? 2 : -2; // Branch not taken\r
+ OpEnd(0);\r
}\r
\r
return 0;\r
notaz.gp2x.de / picodrive.git / blobdiff