bugfixes, test_misc2, checkpc options

[picodrive.git] / cpu / Cyclone / OpLogic.cpp

diff --git a/cpu/Cyclone/OpLogic.cpp b/cpu/Cyclone/OpLogic.cpp
index 3389a8e..7623704 100644 (file)
--- a/cpu/Cyclone/OpLogic.cpp
+++ b/cpu/Cyclone/OpLogic.cpp
@@ -409,13 +409,6 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
     if (type==0) ot("  movs r0,r0,%s %s\n",dir?"asl":"asr",pct);\r
     if (type==1) ot("  movs r0,r0,%s %s\n",dir?"lsl":"lsr",pct);\r
 \r
-    if (dir==0 && size<2)\r
-    {\r
-      ot(";@ restore after right shift:\n");\r
-      ot("  mov r0,r0,lsl #%d\n",32-(8<<size));\r
-      ot("\n");\r
-    }\r
-\r
     OpGetFlags(0,0);\r
     if (usereg) { // store X only if count is not 0\r
       ot("  cmp %s,#0 ;@ shifting by 0?\n",pct);\r
@@ -425,6 +418,16 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
       // count will never be 0 if we use immediate\r
       ot("  str r9,[r7,#0x4c] ;@ Save X bit\n");\r
     }\r
+    ot("\n");\r
+\r
+    if (dir==0 && size<2)\r
+    {\r
+      ot(";@ restore after right shift:\n");\r
+      ot("  movs r0,r0,lsl #%d\n",32-(8<<size));\r
+      if (type)\r
+        ot("  orrmi r9,r9,#0x80000000 ;@ Potentially missed N flag\n");\r
+      ot("\n");\r
+    }\r
 \r
     if (type==0 && dir) {\r
       ot(";@ calculate V flag (set if sign bit changes at anytime):\n");\r
@@ -433,9 +436,8 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
       ot("  cmpne r3,r1,asr %s\n", pct);\r
       ot("  biceq r9,r9,#0x10000000\n");\r
       ot("  orrne r9,r9,#0x10000000\n");\r
+      ot("\n");\r
     }\r
-\r
-    ot("\n");\r
   }\r
 \r
   // --------------------------------------\r
@@ -467,12 +469,20 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
 \r
     if (usereg)\r
     {\r
-      ot(";@ Reduce r2 until <0:\n");\r
-      ot("Reduce_%.4x%s\n",op,ms?"":":");\r
-      ot("  subs r2,r2,#%d\n",wide+1);\r
-      ot("  bpl Reduce_%.4x\n",op);\r
-      ot("  adds r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);\r
-      ot("  beq norotx%.4x\n",op);\r
+      if (size==2)\r
+      {\r
+        ot("  subs r2,r2,#33\n");\r
+        ot("  addmis r2,r2,#33 ;@ Now r2=0-%d\n",wide);\r
+      }\r
+      else\r
+      {\r
+        ot(";@ Reduce r2 until <0:\n");\r
+        ot("Reduce_%.4x%s\n",op,ms?"":":");\r
+        ot("  subs r2,r2,#%d\n",wide+1);\r
+        ot("  bpl Reduce_%.4x\n",op);\r
+        ot("  adds r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);\r
+      }\r
+      ot("  beq norotx_%.4x\n",op);\r
       ot("\n");\r
     }\r
 \r
@@ -488,30 +498,26 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
 \r
     if (shift) ot("  mov r0,r0,lsr #%d ;@ Shift down\n",shift);\r
 \r
-    ot(";@ Rotate bits:\n");\r
-    ot("  mov r3,r0,lsr r2 ;@ Get right part\n");\r
-    ot("  rsbs r2,r2,#%d ;@ should also clear ARM V\n",wide+1);\r
-    ot("  movs r0,r0,lsl r2 ;@ Get left part\n");\r
-    ot("  orr r0,r3,r0 ;@ r0=Rotated value\n");\r
-\r
-    ot(";@ Insert X bit into r2-1:\n");\r
+    ot("\n");\r
+    ot(";@ First get X bit (middle):\n");\r
     ot("  ldr r3,[r7,#0x4c]\n");\r
-    ot("  sub r2,r2,#1\n");\r
+    ot("  rsb r1,r2,#%d\n",wide);\r
     ot("  and r3,r3,#0x20000000\n");\r
     ot("  mov r3,r3,lsr #29\n");\r
-    ot("  orr r0,r0,r3,lsl r2\n");\r
+    ot("  mov r3,r3,lsl r1\n");\r
+\r
+    ot(";@ Rotate bits:\n");\r
+    ot("  orr r3,r3,r0,lsr r2 ;@ Orr right part\n");\r
+    ot("  rsbs r2,r2,#%d ;@ should also clear ARM V\n",wide+1);\r
+    ot("  orrs r0,r3,r0,lsl r2 ;@ Orr left part, set flags\n");\r
     ot("\n");\r
 \r
     if (shift) ot("  movs r0,r0,lsl #%d ;@ Shift up and get correct NC flags\n",shift);\r
     OpGetFlags(0,!usereg);\r
-    if (!shift) {\r
-      ot("  tst r0,r0\n");\r
-      ot("  bicne r9,r9,#0x40000000 ;@ make sure we didn't mess Z\n");\r
-    }\r
     if (usereg) { // store X only if count is not 0\r
       ot("  str r9,[r7,#0x4c] ;@ if not 0, Save X bit\n");\r
       ot("  b nozerox%.4x\n",op);\r
-      ot("norotx%.4x%s\n",op,ms?"":":");\r
+      ot("norotx_%.4x%s\n",op,ms?"":":");\r
       ot("  ldr r2,[r7,#0x4c]\n");\r
       ot("  adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
       OpGetFlags(0,0);\r
@@ -536,9 +542,10 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
     }\r
 \r
     ot(";@ Rotate register:\n");\r
+    if (!dir) ot("  adds r0,r0,#0 ;@ first clear V and C\n"); // ARM does not clear C if rot count is 0\r
     if (count<0)\r
     {\r
-      if (dir) ot("  rsbs %s,%s,#32\n",pct,pct);\r
+      if (dir) ot("  rsb %s,%s,#32\n",pct,pct);\r
       ot("  movs r0,r0,ror %s\n",pct);\r
     }\r
     else\r
@@ -549,9 +556,9 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
     }\r
 \r
     OpGetFlags(0,0);\r
-    if (!dir) ot("  bic r9,r9,#0x10000000 ;@ make suve V is clear\n");\r
     if (dir)\r
     {\r
+      ot("  bic r9,r9,#0x30000000 ;@ clear CV\n");\r
       ot(";@ Get carry bit from bit 0:\n");\r
       if (usereg)\r
       {\r
@@ -561,14 +568,6 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
       else\r
         ot("  tst r0,#1\n");\r
       ot("  orrne r9,r9,#0x20000000\n");\r
-      ot("  biceq r9,r9,#0x20000000\n");\r
-    }\r
-    else if (usereg)\r
-    {\r
-      // if we rotate something by 0, ARM doesn't clear C\r
-      // so we need to detect that\r
-      ot("  cmp %s,#0\n",pct);\r
-      ot("  biceq r9,r9,#0x20000000\n");\r
     }\r
     ot("\n");\r
 \r
@@ -599,7 +598,7 @@ int OpAsr(int op)
   // Use the same opcode for target registers:\r
   use=op&~0x0007;\r
 \r
-  // As long as count is not 8, use the same opcode for all shift counts::\r
+  // As long as count is not 8, use the same opcode for all shift counts:\r
   if (usereg==0 && count!=8 && !(count==1&&type==2)) { use|=0x0e00; count=-1; }\r
   if (usereg) { use&=~0x0e00; count=-1; } // Use same opcode for all Dn\r
 \r