// trashes r0,r2\r
void OpFlagsToReg(int high)\r
{\r
- ot(" ldrb r0,[r7,#0x45] ;@ X bit\n");\r
+ ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
ot(" mov r1,r9,lsr #28 ;@ ____NZCV\n");\r
ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
ot("\n");\r
if (high) ot(" ldrb r2,[r7,#0x44] ;@ Include SR high\n");\r
- ot(" and r0,r0,#0x02\n");\r
- ot(" orr r1,r1,r0,lsl #3 ;@ ___XNZVC\n");\r
+ ot(" and r0,r0,#0x20000000\n");\r
+ ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
if (high) ot(" orr r1,r1,r2,lsl #8\n");\r
ot("\n");\r
}\r
void OpRegToFlags(int high)\r
{\r
ot(" eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");\r
- ot(" mov r2,r0,lsr #3 ;@ r2=___XN\n");\r
+ ot(" mov r2,r0,lsl #25\n");\r
ot(" tst r1,#1 ;@ 1 if C!=V\n");\r
ot(" eorne r0,r0,#3 ;@ ___XNZCV\n");\r
- ot(" strb r2,[r7,#0x45] ;@ Store X bit\n");\r
+ ot(" str r2,[r7,#0x4c] ;@ Store X bit\n");\r
ot(" mov r9,r0,lsl #28 ;@ r9=NZCV...\n");\r
\r
if (high)\r
{\r
ot(" ldr r11,[r7,#0x44] ;@ Get SR high\n");\r
ot(" tst r11,#0x20 ;@ Check we are in supervisor mode\n");\r
- ot(" beq WrongMode%.4x ;@ No\n",op);\r
+ ot(" beq WrongPrivilegeMode ;@ No\n");\r
ot("\n");\r
}\r
\r
-void SuperEnd(int op)\r
+void SuperEnd(void)\r
{\r
- ot("WrongMode%.4x%s\n",op,ms?"":":");\r
- ot(" sub r4,r4,#2 ;@ this opcode wasn't executed - go back\n");\r
+ ot(";@ ----------\n");\r
+ ot(";@ tried execute privileged instruction in user mode\n");\r
+ ot("WrongPrivilegeMode%s\n",ms?"":":");\r
+ ot(" sub r4,r4,#2 ;@ last opcode wasn't executed - go back\n");\r
ot(" mov r0,#0x20 ;@ privilege violation\n");\r
ot(" bl Exception\n");\r
Cycles=34;\r
- OpEnd();\r
+ OpEnd(0x10);\r
}\r
\r
// does OSP and A7 swapping if needed\r
// new or old SR (not the one already in [r7,#0x44]) should be passed in r11\r
-// trashes r1,r11\r
-void SuperChange(int op)\r
+// trashes r0,r11\r
+void SuperChange(int op,int load_srh)\r
{\r
ot(";@ A7 <-> OSP?\n");\r
- ot(" ldr r1,[r7,#0x44] ;@ Get other SR high\n");\r
- ot(" and r11,r11,#0x20\n");\r
- ot(" and r1,r1,#0x20\n");\r
- ot(" teq r11,r1 ;@ r11 xor r1\n");\r
+ if (load_srh)\r
+ ot(" ldr r0,[r7,#0x44] ;@ Get other SR high\n");\r
+ ot(" eor r0,r0,r11\n");\r
+ ot(" tst r0,#0x20\n");\r
ot(" beq no_sp_swap%.4x\n",op);\r
ot(" ;@ swap OSP and A7:\n");\r
ot(" ldr r11,[r7,#0x3C] ;@ Get A7\n");\r
- ot(" ldr r1, [r7,#0x48] ;@ Get OSP\n");\r
+ ot(" ldr r0, [r7,#0x48] ;@ Get OSP\n");\r
ot(" str r11,[r7,#0x48]\n");\r
- ot(" str r1, [r7,#0x3C]\n");\r
+ ot(" str r0, [r7,#0x3C]\n");\r
ot("no_sp_swap%.4x%s\n", op, ms?"":":");\r
}\r
\r
if (EaCanRead (sea,size)==0) return 1;\r
if (EaCanWrite(tea )==0) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (tea<0x38) use&=~0x0e00; // Use same handler for register ?0-7\r
\r
- if (tea>=0x18 && tea<0x28 && (tea&7)==7) use|=0x0e00; // Specific handler for (a7)+ and -(a7)\r
+ if (tea==0x1f || tea==0x27) use|=0x0e00; // Specific handler for (a7)+ and -(a7)\r
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=4;\r
+ OpStart(op,sea,tea); Cycles=4;\r
\r
- EaCalc(0,0x003f,sea,size);\r
- EaRead(0, 1,sea,size,0x003f);\r
+ EaCalcRead(-1,1,sea,size,0x003f);\r
\r
- if (movea==0) {\r
+ if (movea==0)\r
+ {\r
ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
ot(" mrs r9,cpsr ;@ r9=NZCV flags\n");\r
ot("\n");\r
\r
if (movea) size=2; // movea always expands to 32-bits\r
\r
- EaCalc (0,0x0e00,tea,size);\r
#if SPLIT_MOVEL_PD\r
+ EaCalc (10,0x0e00,tea,size,0,0);\r
if ((tea&0x38)==0x20 && size==2) { // -(An)\r
- ot(" mov r10,r0\n");\r
ot(" mov r11,r1\n");\r
- ot(" add r0,r0,#2\n");\r
- EaWrite(0, 1,tea,1,0x0e00);\r
+ ot(" add r0,r10,#2\n");\r
+ EaWrite(0, 1,tea,1,0x0e00,0,0);\r
EaWrite(10, 11,tea,1,0x0e00,1);\r
} else {\r
- EaWrite(0, 1,tea,size,0x0e00);\r
+ EaWrite(0, 1,tea,size,0x0e00,0,0);\r
}\r
#else\r
- EaWrite(0, 1,tea,size,0x0e00);\r
+ EaCalc (0,0x0e00,tea,size,0,0);\r
+ EaWrite(0, 1,tea,size,0x0e00,0,0);\r
#endif\r
\r
#if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES\r
\r
if((tea&0x38)==0x20) Cycles-=2; // less cycles when dest is -(An)\r
\r
- OpEnd();\r
+ OpEnd(sea,tea);\r
return 0;\r
}\r
\r
\r
if (EaCanRead(sea,-1)==0) return 1; // See if we can do this opcode\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,0);\r
use&=~0x0e00; // Also use 1 handler for target ?0-7\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op);\r
+ OpStart(op,sea,tea);\r
\r
EaCalc (1,0x003f,sea,0); // Lea\r
- EaCalc (0,0x0e00,tea,2,1);\r
- EaWrite(0, 1,tea,2,0x0e00,1);\r
+ EaCalc (0,0x0e00,tea,2);\r
+ EaWrite(0, 1,tea,2,0x0e00);\r
\r
Cycles=Ea_add_ns(g_lea_cycle_table,sea);\r
\r
- OpEnd();\r
+ OpEnd(sea,tea);\r
\r
return 0;\r
}\r
case 1:\r
return 1; // no such op in 68000\r
\r
- case 2: case 3:\r
+ case 2: case 3:\r
if (EaCanRead(ea,size)==0) return 1; // See if we can do this opcode:\r
break;\r
}\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op);\r
+ OpStart(op,ea);\r
Cycles=12;\r
if (type==0) Cycles=(ea>=8)?8:6;\r
\r
if (type==0 || type==1)\r
{\r
OpFlagsToReg(type==0);\r
- EaCalc (0,0x003f,ea,size);\r
- EaWrite(0, 1,ea,size,0x003f);\r
+ EaCalc (0,0x003f,ea,size,0,0);\r
+ EaWrite(0, 1,ea,size,0x003f,0,0);\r
}\r
\r
if (type==2 || type==3)\r
{\r
- EaCalc(0,0x003f,ea,size);\r
- EaRead(0, 0,ea,size,0x003f);\r
+ EaCalcReadNoSE(-1,0,ea,size,0x003f);\r
OpRegToFlags(type==3);\r
if (type==3) {\r
- SuperChange(op);\r
- CheckInterrupt(op);\r
- }\r
+ SuperChange(op,0);\r
+ CheckInterrupt(op);\r
+ }\r
}\r
\r
- OpEnd();\r
-\r
- if (type==3) SuperEnd(op);\r
+ OpEnd(ea);\r
\r
return 0;\r
}\r
size=(op>>6)&1; // ccr or sr?\r
ea=0x3c;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=16;\r
+ OpStart(op,ea); Cycles=16;\r
\r
if (size) SuperCheck(op);\r
\r
- EaCalc(0,0x003f,ea,size);\r
- EaRead(0, 10,ea,size,0x003f);\r
+ EaCalc(10,0x003f,ea,size);\r
+ EaRead(10, 10,ea,size,0x003f);\r
\r
OpFlagsToReg(size);\r
if (type==0) ot(" orr r0,r1,r10\n");\r
if (type==5) ot(" eor r0,r1,r10\n");\r
OpRegToFlags(size);\r
if (size) {\r
- SuperChange(op);\r
+ SuperChange(op,0);\r
CheckInterrupt(op);\r
}\r
\r
- OpEnd();\r
- if (size) SuperEnd(op);\r
+ OpEnd(ea);\r
\r
return 0;\r
}\r
ea=op&0x003f; if (ea<0x10) return 1; // Swap opcode\r
if (EaCanRead(ea,-1)==0) return 1; // See if we can do this opcode:\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,0);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op);\r
+ OpStart(op,ea);\r
\r
ot(" ldr r10,[r7,#0x3c]\n");\r
EaCalc (1,0x003f, ea,0);\r
\r
Cycles=6+Ea_add_ns(g_pea_cycle_table,ea);\r
\r
- OpEnd();\r
+ OpEnd(ea);\r
\r
return 0;\r
}\r
\r
cea=ea; if (change) cea=0x10;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op);\r
+ OpStart(op,ea);\r
\r
- ot(" stmdb sp!,{r9} ;@ Push r9\n"); // can't just use r12 or lr here, because memhandlers touch them\r
ot(" ldrh r11,[r4],#2 ;@ r11=register mask\n");\r
\r
- ot("\n");\r
- ot(";@ Get the address into r9:\n");\r
- EaCalc(9,0x003f,cea,size);\r
-\r
ot(";@ r10=Register Index*4:\n");\r
- if (decr) ot(" mov r10,#0x3c ;@ order reversed for -(An)\n");\r
- else ot(" mov r10,#0\n");\r
+ if (decr) ot(" mov r10,#0x40 ;@ order reversed for -(An)\n");\r
+ else ot(" mov r10,#-4\n");\r
\r
ot("\n");\r
- ot("MoreReg%.4x%s\n",op, ms?"":":");\r
+ ot(";@ Get the address into r6:\n");\r
+ EaCalc(6,0x003f,cea,size);\r
+\r
+ ot("\n");\r
+ ot(" tst r11,r11\n"); // sanity check\r
+ ot(" beq NoRegs%.4x\n",op);\r
\r
- ot(" tst r11,#1\n");\r
- ot(" beq SkipReg%.4x\n",op);\r
+ ot("\n");\r
+ ot("Movemloop%.4x%s\n",op, ms?"":":");\r
+ ot(" add r10,r10,#%d ;@ r10=Next Register\n",decr?-4:4);\r
+ ot(" movs r11,r11,lsr #1\n");\r
+ ot(" bcc Movemloop%.4x\n",op);\r
ot("\n");\r
\r
- if (decr) ot(" sub r9,r9,#%d ;@ Pre-decrement address\n",1<<size);\r
+ if (decr) ot(" sub r6,r6,#%d ;@ Pre-decrement address\n",1<<size);\r
\r
if (dir)\r
{\r
ot(" ;@ Copy memory to register:\n",1<<size);\r
- EaRead (9,0,ea,size,0x003f);\r
+ EaRead (6,0,ea,size,0x003f);\r
ot(" str r0,[r7,r10] ;@ Save value into Dn/An\n");\r
}\r
else\r
{\r
ot(" ;@ Copy register to memory:\n",1<<size);\r
ot(" ldr r1,[r7,r10] ;@ Load value from Dn/An\n");\r
- EaWrite(9,1,ea,size,0x003f);\r
+ EaWrite(6,1,ea,size,0x003f);\r
}\r
\r
- if (decr==0) ot(" add r9,r9,#%d ;@ Post-increment address\n",1<<size);\r
+ if (decr==0) ot(" add r6,r6,#%d ;@ Post-increment address\n",1<<size);\r
\r
ot(" sub r5,r5,#%d ;@ Take some cycles\n",2<<size);\r
- ot("\n");\r
- ot("SkipReg%.4x%s\n",op, ms?"":":");\r
- ot(" movs r11,r11,lsr #1;@ Shift mask:\n");\r
- ot(" add r10,r10,#%d ;@ r10=Next Register\n",decr?-4:4);\r
- ot(" bne MoreReg%.4x\n",op);\r
+ ot(" tst r11,r11\n");\r
+ ot(" bne Movemloop%.4x\n",op);\r
ot("\n");\r
\r
if (change)\r
{\r
ot(";@ Write back address:\n");\r
EaCalc (0,0x0007,8|(ea&7),2);\r
- EaWrite(0, 9,8|(ea&7),2,0x0007);\r
+ EaWrite(0, 6,8|(ea&7),2,0x0007);\r
}\r
\r
- ot(" ldmia sp!,{r9} ;@ Pop r9\n");\r
+ ot("NoRegs%.4x%s\n",op, ms?"":":");\r
+ ot(" ldr r6,=CycloneJumpTab ;@ restore Opcode Jump table\n");\r
ot("\n");\r
\r
if(dir) { // er\r
if (ea==0x3a) Cycles=16; // ($nn,PC)\r
else if (ea==0x3b) Cycles=18; // ($nn,pc,Rn)\r
- else Cycles=12;\r
+ else Cycles=12;\r
} else {\r
Cycles=8;\r
}\r
\r
Cycles+=Ea_add_ns(g_movem_cycle_table,ea);\r
\r
- OpEnd();\r
+ OpEnd(ea);\r
+ ltorg();\r
+ ot("\n");\r
\r
return 0;\r
}\r
if (dir)\r
{\r
ot(" ldr r1,[r7,#0x48] ;@ Get from USP\n\n");\r
- EaCalc (0,0x0007,8,2,1);\r
- EaWrite(0, 1,8,2,0x0007,1);\r
+ EaCalc (0,0x000f,8,2,1);\r
+ EaWrite(0, 1,8,2,0x000f,1);\r
}\r
else\r
{\r
- EaCalc (0,0x0007,8,2,1);\r
- EaRead (0, 0,8,2,0x0007,1);\r
+ EaCalc (0,0x000f,8,2,1);\r
+ EaRead (0, 0,8,2,0x000f,1);\r
ot(" str r0,[r7,#0x48] ;@ Put in USP\n\n");\r
}\r
\r
OpEnd();\r
\r
- SuperEnd(op);\r
-\r
return 0;\r
}\r
\r
// 0000sss1 1z001ddd (to mem)\r
int OpMovep(int op)\r
{\r
- int ea=0;\r
- int size=1,use=0,dir;\r
+ int ea=0,rea=0;\r
+ int size=1,use=0,dir,aadd=0;\r
\r
use=op&0xf1f8;\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler (for all dests, srcs)\r
\r
// Get EA\r
ea = (op&0x0007)|0x28;\r
+ rea= (op&0x0e00)>>9;\r
dir = (op>>7)&1;\r
\r
// Find size extension\r
if(op&0x0040) size=2;\r
\r
- OpStart(op);\r
+ OpStart(op,ea);\r
\r
if(dir) { // reg to mem\r
- EaCalc(11,0x0e00,0,size); // reg number -> r11\r
- EaRead(11,11,0,size,0x0e00); // regval -> r11\r
- EaCalc(10,0x0007,ea,size);\r
- if(size==2) { // if operand is long\r
- ot(" mov r1,r11,lsr #24 ;@ first byte\n");\r
- EaWrite(10,1,ea,0,0x0007); // store first byte\r
- ot(" add r10,r10,#2\n");\r
- ot(" mov r1,r11,lsr #16 ;@ second byte\n");\r
- EaWrite(10,1,ea,0,0x0007); // store second byte\r
- ot(" add r10,r10,#2\n");\r
- }\r
- ot(" mov r1,r11,lsr #8 ;@ first or third byte\n");\r
- EaWrite(10,1,ea,0,0x0007);\r
- ot(" add r10,r10,#2\n");\r
- ot(" and r1,r11,#0xff\n");\r
- EaWrite(10,1,ea,0,0x0007);\r
+ EaCalcReadNoSE(-1,11,rea,size,0x0e00);\r
+\r
+ EaCalc(10,0x000f,ea,size);\r
+ if(size==2) { // if operand is long\r
+ ot(" mov r1,r11,lsr #24 ;@ first byte\n");\r
+ EaWrite(10,1,ea,0,0x000f); // store first byte\r
+ ot(" add r0,r10,#%i\n",(aadd+=2));\r
+ ot(" mov r1,r11,lsr #16 ;@ second byte\n");\r
+ EaWrite(0,1,ea,0,0x000f); // store second byte\r
+ ot(" add r0,r10,#%i\n",(aadd+=2));\r
+ } else {\r
+ ot(" mov r0,r10\n");\r
+ }\r
+ ot(" mov r1,r11,lsr #8 ;@ first or third byte\n");\r
+ EaWrite(0,1,ea,0,0x000f);\r
+ ot(" add r0,r10,#%i\n",(aadd+=2));\r
+ ot(" and r1,r11,#0xff\n");\r
+ EaWrite(0,1,ea,0,0x000f);\r
} else { // mem to reg\r
- EaCalc(10,0x0007,ea,size,1);\r
- EaRead(10,11,ea,0,0x0007,1); // read first byte\r
- ot(" add r10,r10,#2\n");\r
- EaRead(10,1,ea,0,0x0007,1); // read second byte\r
- if(size==2) { // if operand is long\r
+ EaCalc(10,0x000f,ea,size,1);\r
+ EaRead(10,11,ea,0,0x000f,1); // read first byte\r
+ ot(" add r0,r10,#2\n");\r
+ EaRead(0,1,ea,0,0x000f,1); // read second byte\r
+ if(size==2) { // if operand is long\r
ot(" orr r11,r11,r1,lsr #8 ;@ second byte\n");\r
- ot(" add r10,r10,#2\n");\r
- EaRead(10,1,ea,0,0x0007,1);\r
+ ot(" add r0,r10,#4\n");\r
+ EaRead(0,1,ea,0,0x000f,1);\r
ot(" orr r11,r11,r1,lsr #16 ;@ third byte\n");\r
- ot(" add r10,r10,#2\n");\r
- EaRead(10,1,ea,0,0x0007,1);\r
- ot(" orr r0,r11,r1,lsr #24 ;@ fourth byte\n");\r
- } else {\r
- ot(" orr r0,r11,r1,lsr #8 ;@ second byte\n");\r
- }\r
- // store the result\r
- EaCalc(11,0x0e00,0,size,1); // reg number -> r11\r
- EaWrite(11,0,0,size,0x0e00,1);\r
+ ot(" add r0,r10,#6\n");\r
+ EaRead(0,1,ea,0,0x000f,1);\r
+ ot(" orr r1,r11,r1,lsr #24 ;@ fourth byte\n");\r
+ } else {\r
+ ot(" orr r1,r11,r1,lsr #8 ;@ second byte\n");\r
+ }\r
+ // store the result\r
+ EaCalc(11,0x0e00,rea,size,1); // reg number -> r11\r
+ EaWrite(11,1,rea,size,0x0e00,1);\r
}\r
\r
Cycles=(size==2)?24:16;\r
- OpEnd();\r
+ OpEnd(ea);\r
\r
return 0;\r
}\r
// Emit a Stop/Reset opcodes, 01001110 011100t0 imm\r
int OpStopReset(int op)\r
{\r
- int type=(op>>1)&1; // reset/stop\r
+ int type=(op>>1)&1; // stop/reset\r
\r
OpStart(op);\r
\r
if(type) {\r
// copy immediate to SR, stop the CPU and eat all remaining cycles.\r
ot(" ldrh r0,[r4],#2 ;@ Fetch the immediate\n");\r
- SuperChange(op);\r
OpRegToFlags(1);\r
+ SuperChange(op,0);\r
\r
- ot("\n");\r
+ ot("\n");\r
\r
- ot(" mov r0,#1\n");\r
- ot(" str r0,[r7,#0x58] ;@ stopped\n");\r
- ot("\n");\r
+ ot(" mov r0,#1\n");\r
+ ot(" str r0,[r7,#0x58] ;@ stopped\n");\r
+ ot("\n");\r
\r
- ot(" mov r5,#0 ;@ eat cycles\n");\r
+ ot(" mov r5,#0 ;@ eat cycles\n");\r
Cycles = 4;\r
- ot("\n");\r
+ ot("\n");\r
}\r
else\r
{\r
ot(" ldr r11,[r7,#0x90] ;@ ResetCallback\n");\r
ot(" tst r11,r11\n");\r
ot(" movne lr,pc\n");\r
- ot(" movne pc,r11 ;@ call ResetCallback if it is defined\n");\r
+ ot(" bxne r11 ;@ call ResetCallback if it is defined\n");\r
ot(" ldrb r9,[r7,#0x46] ;@ r9 = Load Flags (NZCV)\n");\r
ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
ot(" mov r9,r9,lsl #28\n");\r
+ ot("\n");\r
#endif\r
}\r
\r
OpEnd();\r
- SuperEnd(op);\r
\r
return 0;\r
}\r
+\r