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[picodrive.git] / cpu / DrZ80 / drz80.s
diff --git a/cpu/DrZ80/drz80.s b/cpu/DrZ80/drz80.s
new file mode 100644 (file)
index 0000000..4760650
--- /dev/null
+++ b/cpu/DrZ80/drz80.s
@@ -0,0 +1,8076 @@
+;@ Reesy's Z80 Emulator Version 0.001\r
+\r
+;@ (c) Copyright 2004 Reesy, All rights reserved\r
+;@ DrZ80 is free for non-commercial use.\r
+\r
+;@ For commercial use, separate licencing terms must be obtained.\r
+\r
+      .data\r
+      .align 4\r
+\r
+      .global DrZ80Run\r
+      .global DrZ80Ver\r
+\r
+         .equiv INTERRUPT_MODE,                0               ;@0 = Use internal int handler, 1 = Use Mames int handler\r
+         .equiv FAST_Z80SP,                    1               ;@0 = Use mem functions for stack pointer, 1 = Use direct mem pointer\r
+         .equiv UPDATE_CONTEXT,            0\r
+         .equiv DRZ80_FOR_PICODRIVE,   1\r
+\r
+.if INTERRUPT_MODE\r
+         .extern Interrupt\r
+.endif\r
+\r
+.if DRZ80_FOR_PICODRIVE\r
+         .extern YM2612Read_\r
+         .extern YM2612Read_940\r
+      .extern PicoRead8\r
+      .extern Pico\r
+      .extern z80_write\r
+.endif\r
+\r
+DrZ80Ver: .long 0x0001\r
+\r
+;@ --------------------------- Defines ----------------------------\r
+;@ Make sure that regs/pointers for z80pc to z80sp match up!\r
+\r
+       opcodes    .req r3\r
+       z80_icount .req r4\r
+       cpucontext .req r5\r
+       z80pc      .req r6\r
+       z80a       .req r7\r
+       z80f       .req r8\r
+       z80bc      .req r9\r
+       z80de      .req r10\r
+       z80hl      .req r11\r
+       z80sp      .req r12     \r
+       z80xx      .req lr\r
+\r
+       .equ z80pc_pointer,           0                  ;@  0\r
+       .equ z80a_pointer,            z80pc_pointer+4    ;@  4\r
+       .equ z80f_pointer,            z80a_pointer+4     ;@  8\r
+       .equ z80bc_pointer,           z80f_pointer+4     ;@  \r
+       .equ z80de_pointer,           z80bc_pointer+4\r
+       .equ z80hl_pointer,           z80de_pointer+4\r
+       .equ z80sp_pointer,           z80hl_pointer+4\r
+       .equ z80pc_base,              z80sp_pointer+4\r
+       .equ z80sp_base,              z80pc_base+4\r
+       .equ z80ix,                   z80sp_base+4\r
+       .equ z80iy,                   z80ix+4\r
+       .equ z80i,                    z80iy+4\r
+       .equ z80a2,                   z80i+4\r
+       .equ z80f2,                   z80a2+4\r
+       .equ z80bc2,                  z80f2+4\r
+       .equ z80de2,                  z80bc2+4\r
+       .equ z80hl2,                  z80de2+4\r
+       .equ cycles_pointer,          z80hl2+4     \r
+       .equ previouspc,              cycles_pointer+4     \r
+       .equ z80irq,                  previouspc+4\r
+       .equ z80if,                   z80irq+1\r
+       .equ z80im,                   z80if+1\r
+       .equ z80r,                    z80im+1\r
+       .equ z80irqvector,            z80r+1\r
+       .equ z80irqcallback,          z80irqvector+4\r
+       .equ z80_write8,              z80irqcallback+4\r
+       .equ z80_write16,             z80_write8+4\r
+       .equ z80_in,                  z80_write16+4\r
+       .equ z80_out,                 z80_in+4\r
+       .equ z80_read8,               z80_out+4\r
+       .equ z80_read16,              z80_read8+4\r
+       .equ z80_rebaseSP,            z80_read16+4\r
+       .equ z80_rebasePC,            z80_rebaseSP+4\r
+\r
+       .equ VFlag, 0\r
+       .equ CFlag, 1\r
+       .equ ZFlag, 2\r
+       .equ SFlag, 3\r
+       .equ HFlag, 4\r
+       .equ NFlag, 5\r
+       .equ Flag3, 6\r
+       .equ Flag5, 7\r
+\r
+       .equ Z80_CFlag, 0\r
+       .equ Z80_NFlag, 1\r
+       .equ Z80_VFlag, 2\r
+       .equ Z80_Flag3, 3\r
+       .equ Z80_HFlag, 4\r
+       .equ Z80_Flag5, 5\r
+       .equ Z80_ZFlag, 6\r
+       .equ Z80_SFlag, 7\r
+\r
+       .equ Z80_IF1, 1<<0\r
+       .equ Z80_IF2, 1<<1\r
+       .equ Z80_HALT, 1<<2\r
+\r
+;@---------------------------------------\r
+\r
+.text\r
+\r
+.if DRZ80_FOR_PICODRIVE\r
+.include "port_config.s"\r
+\r
+.macro YM2612Read_and_ret8\r
+       stmfd sp!,{r3,r12,lr}\r
+.if EXTERNAL_YM2612\r
+    ldr r1,=PicoOpt\r
+    ldr r1,[r1]\r
+    tst r1,#0x200\r
+    bne 10f\r
+    bl YM2612Read_\r
+       ldmfd sp!,{r3,r12,pc}\r
+10:\r
+    bl YM2612Read_940\r
+.else\r
+    bl YM2612Read_\r
+.endif\r
+       ldmfd sp!,{r3,r12,pc}\r
+.endm\r
+\r
+.macro YM2612Read_and_ret16\r
+       stmfd sp!,{r3,r12,lr}\r
+.if EXTERNAL_YM2612\r
+    ldr r0,=PicoOpt\r
+    ldr r0,[r0]\r
+    tst r0,#0x200\r
+    bne 10f\r
+    bl YM2612Read_\r
+    orr r0,r0,r0,lsl #8\r
+       ldmfd sp!,{r3,r12,pc}\r
+10:\r
+    bl YM2612Read_940\r
+    orr r0,r0,r0,lsl #8\r
+.else\r
+    bl YM2612Read_\r
+    orr r0,r0,r0,lsl #8\r
+.endif\r
+       ldmfd sp!,{r3,r12,pc}\r
+.endm\r
+\r
+pico_z80_read8: @ addr\r
+    cmp r0,#0x2000         @ Z80 RAM\r
+    ldrlt r1,[cpucontext,#z80sp_base]\r
+    ldrltb r0,[r1,r0]\r
+    bxlt lr\r
+\r
+    cmp r0,#0x8000         @ 68k bank\r
+    blt 1f\r
+    ldr r2,=(Pico+0x22212)\r
+    ldrh r1,[r2]\r
+    bic r0,r0,#0x3f8000\r
+    orr r0,r0,r1,lsl #15\r
+    ldr r1,[r2,#-0xe]      @ ROM size\r
+    cmp r0,r1\r
+    ldrlt r1,[r2,#-0x12]   @ ROM\r
+    eorlt r0,r0,#1         @ our ROM is byteswapped\r
+    ldrltb r0,[r1,r0]\r
+    bxlt lr\r
+       stmfd sp!,{r3,r12,lr}\r
+    bl PicoRead8\r
+       ldmfd sp!,{r3,r12,pc}\r
+1:\r
+    mov r1,r0,lsr #13\r
+    cmp r1,#2              @ YM2612 (0x4000-0x5fff)\r
+    bne 0f\r
+    and r0,r0,#3\r
+       YM2612Read_and_ret8\r
+0:\r
+    cmp r0,#0x4000\r
+    movge r0,#0xff\r
+    bxge lr\r
+    ldr r1,[cpucontext,#z80sp_base]\r
+    bic r0,r0,#0x0fe000    @ Z80 RAM (mirror)\r
+    ldrb r0,[r1,r0]\r
+    bx lr\r
+\r
+pico_z80_read16: @ addr\r
+    cmp r0,#0x2000         @ Z80 RAM\r
+    bge 2f\r
+    ldr r1,[cpucontext,#z80sp_base]\r
+    ldrb r0,[r1,r0]!\r
+    ldrb r1,[r1,#1]\r
+    orr r0,r0,r1,lsl #8\r
+    bx lr\r
+\r
+2:\r
+    cmp r0,#0x8000         @ 68k bank\r
+    blt 1f\r
+    ldr r2,=(Pico+0x22212)\r
+    ldrh r1,[r2]\r
+    bic r0,r0,#0x1f8000\r
+    orr r0,r0,r1,lsl #15\r
+    ldr r1,[r2,#-0xe]      @ ROM size\r
+    cmp r0,r1\r
+    ldr r1,[r2,#-0x12]     @ ROM\r
+    tst r0,#1\r
+    eor r0,r0,#1\r
+    ldrb r0,[r1,r0]!\r
+    ldreqb r1,[r1,#-1]\r
+    ldrneb r1,[r1,#3]      @ this is due to byteswapped ROM\r
+    orr r0,r0,r1,lsl #8\r
+    bx lr\r
+3:\r
+    stmfd sp!,{r3-r5,r12,lr}\r
+    mov r4,r0\r
+    bl PicoRead8\r
+    mov r5,r0\r
+    add r0,r4,#1\r
+    bl PicoRead8\r
+    orr r0,r5,r0,lsl #8\r
+       ldmfd sp!,{r3-r5,r12,pc}\r
+1:\r
+    mov r1,r0,lsr #13\r
+    cmp r1,#2              @ YM2612 (0x4000-0x5fff)\r
+    bne 0f\r
+    and r0,r0,#3\r
+       YM2612Read_and_ret16\r
+0:\r
+    cmp r0,#0x4000\r
+    movge r0,#0xff\r
+    bxge lr\r
+    ldr r1,[cpucontext,#z80sp_base]\r
+    bic r0,r0,#0x0fe000    @ Z80 RAM (mirror)\r
+    ldrb r0,[r1,r0]!\r
+    ldrb r1,[r1,#1]\r
+    orr r0,r0,r1,lsl #8\r
+    bx lr\r
+\r
+pico_z80_write8: @ data, addr\r
+    cmp r1,#0x4000\r
+    bge 1f\r
+    ldr r2,[cpucontext,#z80sp_base]\r
+    bic r1,r1,#0x0fe000    @ Z80 RAM\r
+    strb r0,[r2,r1]\r
+    bx lr\r
+1:\r
+    stmfd sp!,{r3,r12,lr}\r
+    bl z80_write\r
+    ldmfd sp!,{r3,r12,pc}\r
+\r
+pico_z80_write16: @ data, addr\r
+    cmp r1,#0x4000\r
+    bge 1f\r
+    ldr r2,[cpucontext,#z80sp_base]\r
+    bic r1,r1,#0x0fe000    @ Z80 RAM\r
+    strb r0,[r2,r1]!\r
+    mov r0,r0,lsr #8\r
+    strb r0,[r2,#1]\r
+    bx lr\r
+1:\r
+       stmfd sp!,{r3-r5,r12,lr}\r
+    mov r4,r0\r
+    mov r5,r1\r
+       bl z80_write\r
+    mov r0,r4,lsr #8\r
+    add r1,r5,#1\r
+       bl z80_write\r
+       ldmfd sp!,{r3-r5,r12,pc}\r
+\r
+    .pool\r
+.endif\r
+\r
+.macro fetch cycs\r
+       subs z80_icount,z80_icount,#\cycs\r
+.if UPDATE_CONTEXT\r
+    str z80pc,[cpucontext,#z80pc_pointer]\r
+       str z80_icount,[cpucontext,#cycles_pointer]\r
+       ldr r1,[cpucontext,#z80pc_base]\r
+       sub r2,z80pc,r1\r
+       str r2,[cpucontext,#previouspc]\r
+.endif\r
+       ldrplb r0,[z80pc],#1\r
+       ldrpl pc,[opcodes,r0, lsl #2]\r
+       bmi z80_execute_end\r
+.endm\r
+\r
+.macro eatcycles cycs\r
+       sub z80_icount,z80_icount,#\cycs\r
+.if UPDATE_CONTEXT\r
+       str z80_icount,[cpucontext,#cycles_pointer]\r
+.endif\r
+.endm\r
+\r
+.macro readmem8\r
+.if UPDATE_CONTEXT\r
+    str z80pc,[cpucontext,#z80pc_pointer]\r
+.endif\r
+.if DRZ80_FOR_PICODRIVE\r
+    bl pico_z80_read8\r
+.else\r
+    stmfd sp!,{r3,r12}\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_read8]                  ;@ r0 = addr - data returned in r0\r
+       ldmfd sp!,{r3,r12}\r
+.endif\r
+.endm\r
+\r
+.macro readmem8HL\r
+       mov r0,z80hl, lsr #16\r
+       readmem8\r
+.endm\r
+\r
+.macro readmem16\r
+.if UPDATE_CONTEXT\r
+     str z80pc,[cpucontext,#z80pc_pointer]\r
+.endif\r
+.if DRZ80_FOR_PICODRIVE\r
+    bl pico_z80_read16\r
+.else\r
+       stmfd sp!,{r3,r12}\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_read16]\r
+       ldmfd sp!,{r3,r12}\r
+.endif\r
+.endm\r
+\r
+.macro writemem8\r
+.if UPDATE_CONTEXT\r
+     str z80pc,[cpucontext,#z80pc_pointer]\r
+.endif\r
+.if DRZ80_FOR_PICODRIVE\r
+    bl pico_z80_write8\r
+.else\r
+       stmfd sp!,{r3,r12}\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_write8]                 ;@ r0=data r1=addr\r
+       ldmfd sp!,{r3,r12}\r
+.endif\r
+.endm\r
+\r
+.macro writemem8DE\r
+       mov r1,z80de, lsr #16\r
+       writemem8\r
+.endm\r
+\r
+.macro writemem8HL\r
+       mov r1,z80hl, lsr #16\r
+       writemem8\r
+.endm\r
+\r
+.macro writemem16\r
+.if UPDATE_CONTEXT\r
+     str z80pc,[cpucontext,#z80pc_pointer]\r
+.endif\r
+.if DRZ80_FOR_PICODRIVE\r
+    bl pico_z80_write16\r
+.else\r
+       stmfd sp!,{r3,r12}\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_write16]                ;@ r0=data r1=addr\r
+       ldmfd sp!,{r3,r12}\r
+.endif\r
+.endm\r
+\r
+.macro copymem8HL_DE\r
+.if UPDATE_CONTEXT\r
+     str z80pc,[cpucontext,#z80pc_pointer]\r
+.endif\r
+       mov r0,z80hl, lsr #16\r
+.if DRZ80_FOR_PICODRIVE\r
+    bl pico_z80_read8\r
+.else\r
+    stmfd sp!,{r3,r12}\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_read8]                  ;@ r0 = addr - data returned in r0\r
+.endif\r
+.if UPDATE_CONTEXT\r
+     str z80pc,[cpucontext,#z80pc_pointer]\r
+.endif\r
+       mov r1,z80de, lsr #16\r
+.if DRZ80_FOR_PICODRIVE\r
+    bl pico_z80_write8\r
+.else\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_write8]                 ;@ r0=data r1=addr\r
+       ldmfd sp!,{r3,r12}\r
+.endif\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro rebasepc\r
+.if UPDATE_CONTEXT\r
+     str z80pc,[cpucontext,#z80pc_pointer]\r
+.endif\r
+.if DRZ80_FOR_PICODRIVE\r
+    bic r0,r0,#0xfe000\r
+    ldr r1,[cpucontext,#z80pc_base]\r
+    add z80pc,r1,r0\r
+.else\r
+    stmfd sp!,{r3,r12}\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_rebasePC]               ;@ r0=new pc - external function sets z80pc_base and returns new z80pc in r0\r
+       ldmfd sp!,{r3,r12}\r
+       mov z80pc,r0\r
+.endif\r
+.endm\r
+\r
+.macro rebasesp\r
+.if UPDATE_CONTEXT\r
+     str z80pc,[cpucontext,#z80pc_pointer]\r
+.endif\r
+.if DRZ80_FOR_PICODRIVE\r
+    bic r0,r0,#0xfe000\r
+    ldr r1,[cpucontext,#z80sp_base]\r
+    add r0,r1,r0\r
+.else\r
+       stmfd sp!,{r3,r12}\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_rebaseSP]               ;@ external function must rebase sp\r
+       ldmfd sp!,{r3,r12}\r
+.endif\r
+.endm\r
+;@----------------------------------------------------------------------------\r
+\r
+.macro opADC\r
+       movs z80f,z80f,lsr#2                                    ;@ get C\r
+       subcs r0,r0,#0x100\r
+       eor z80f,r0,z80a,lsr#24                                 ;@ prepare for check of half carry\r
+       adcs z80a,z80a,r0,ror#8\r
+       mrs r0,cpsr                                                             ;@ S,Z,V&C\r
+       eor z80f,z80f,z80a,lsr#24\r
+       and z80f,z80f,#1<<HFlag                                 ;@ H, correct\r
+       orr z80f,z80f,r0,lsr#28\r
+.endm\r
+\r
+.macro opADCA\r
+       movs z80f,z80f,lsr#2                                    ;@ get C\r
+       orrcs z80a,z80a,#0x00800000\r
+       adds z80a,z80a,z80a\r
+       mrs z80f,cpsr                                                   ;@ S,Z,V&C\r
+       mov z80f,z80f,lsr#28\r
+       tst z80a,#0x10000000                                    ;@ H, correct\r
+       orrne z80f,z80f,#1<<HFlag\r
+       fetch 4\r
+.endm\r
+\r
+.macro opADCH reg\r
+       mov r0,\reg,lsr#24\r
+       opADC\r
+       fetch 4\r
+.endm\r
+\r
+.macro opADCL reg\r
+       movs z80f,z80f,lsr#2                                    ;@ get C\r
+       adc r0,\reg,\reg,lsr#15\r
+       orrcs z80a,z80a,#0x00800000\r
+       mov r1,z80a,lsl#4                                               ;@ Prepare for check of half carry\r
+       adds z80a,z80a,r0,lsl#23\r
+       mrs z80f,cpsr                                                   ;@ S,Z,V&C\r
+       mov z80f,z80f,lsr#28\r
+       cmn r1,r0,lsl#27\r
+       orrcs z80f,z80f,#1<<HFlag                               ;@ H, correct\r
+       fetch 4\r
+.endm\r
+\r
+.macro opADCb\r
+       opADC\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opADD reg shift\r
+       mov r1,z80a,lsl#4                                               ;@ Prepare for check of half carry\r
+       adds z80a,z80a,\reg,lsl#\shift\r
+       mrs z80f,cpsr                                                   ;@ S,Z,V&C\r
+       mov z80f,z80f,lsr#28\r
+       cmn r1,\reg,lsl#\shift+4\r
+       orrcs z80f,z80f,#1<<HFlag\r
+.endm\r
+\r
+.macro opADDA\r
+       adds z80a,z80a,z80a\r
+       mrs z80f,cpsr                                                   ;@ S,Z,V&C\r
+       mov z80f,z80f,lsr#28\r
+       tst z80a,#0x10000000                                    ;@ H, correct\r
+       orrne z80f,z80f,#1<<HFlag\r
+       fetch 4\r
+.endm\r
+\r
+.macro opADDH reg\r
+       and r0,\reg,#0xFF000000\r
+       opADD r0 0\r
+       fetch 4\r
+.endm\r
+\r
+.macro opADDL reg\r
+       opADD \reg 8\r
+       fetch 4\r
+.endm\r
+\r
+.macro opADDb \r
+       opADD r0 24\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opADC16 reg\r
+       movs z80f,z80f,lsr#2                                    ;@ get C\r
+       adc r0,z80a,\reg,lsr#15\r
+       orrcs z80hl,z80hl,#0x00008000\r
+       mov r1,z80hl,lsl#4\r
+       adds z80hl,z80hl,r0,lsl#15\r
+       mrs z80f,cpsr                                                   ;@ S, Z, V & C\r
+       mov z80f,z80f,lsr#28\r
+       cmn r1,r0,lsl#19\r
+       orrcs z80f,z80f,#1<<HFlag\r
+       fetch 15\r
+.endm\r
+\r
+.macro opADC16HL\r
+       movs z80f,z80f,lsr#2                                    ;@ get C\r
+       orrcs z80hl,z80hl,#0x00008000\r
+       adds z80hl,z80hl,z80hl\r
+       mrs z80f,cpsr                                                   ;@ S, Z, V & C\r
+       mov z80f,z80f,lsr#28\r
+       tst z80hl,#0x10000000                                   ;@ H, correct.\r
+       orrne z80f,z80f,#1<<HFlag\r
+       fetch 15\r
+.endm\r
+\r
+.macro opADD16 reg1 reg2\r
+       mov r1,\reg1,lsl#4                                              ;@ Prepare for check of half carry\r
+       adds \reg1,\reg1,\reg2\r
+       bic z80f,z80f,#(1<<CFlag)|(1<<HFlag)|(1<<NFlag)\r
+       orrcs z80f,z80f,#1<<CFlag\r
+       cmn r1,\reg2,lsl#4\r
+       orrcs z80f,z80f,#1<<HFlag\r
+.endm\r
+\r
+.macro opADD16s reg1 reg2 shift\r
+       mov r1,\reg1,lsl#4                                              ;@ Prepare for check of half carry\r
+       adds \reg1,\reg1,\reg2,lsl#\shift\r
+       bic z80f,z80f,#(1<<CFlag)|(1<<HFlag)|(1<<NFlag)\r
+       orrcs z80f,z80f,#1<<CFlag\r
+       cmn r1,\reg2,lsl#4+\shift\r
+       orrcs z80f,z80f,#1<<HFlag\r
+.endm\r
+\r
+.macro opADD16_2 reg\r
+       adds \reg,\reg,\reg\r
+       bic z80f,z80f,#(1<<CFlag)|(1<<HFlag)|(1<<NFlag)\r
+       orrcs z80f,z80f,#1<<CFlag\r
+       tst \reg,#0x10000000                                    ;@ H, correct.\r
+       orrne z80f,z80f,#1<<HFlag\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opAND reg shift\r
+       and z80a,z80a,\reg,lsl#\shift\r
+       sub r0,opcodes,#0x100\r
+       ldrb z80f,[r0,z80a, lsr #24]\r
+       orr z80f,z80f,#1<<HFlag\r
+.endm\r
+\r
+.macro opANDA\r
+       sub r0,opcodes,#0x100\r
+       ldrb z80f,[r0,z80a, lsr #24]\r
+       orr z80f,z80f,#1<<HFlag\r
+       fetch 4\r
+.endm\r
+\r
+.macro opANDH reg\r
+       opAND \reg 0\r
+       fetch 4\r
+.endm\r
+\r
+.macro opANDL reg\r
+       opAND \reg 8\r
+       fetch 4\r
+.endm\r
+\r
+.macro opANDb\r
+       opAND r0 24\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opBITH reg bit\r
+       and z80f,z80f,#1<<CFlag\r
+       tst \reg,#1<<(24+\bit)\r
+       orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)\r
+       orrne z80f,z80f,#(1<<HFlag)\r
+       fetch 8\r
+.endm\r
+\r
+.macro opBIT7H reg\r
+       and z80f,z80f,#1<<CFlag\r
+       tst \reg,#1<<(24+7)\r
+       orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)\r
+       orrne z80f,z80f,#(1<<HFlag)|(1<<SFlag)\r
+       fetch 8\r
+.endm\r
+\r
+.macro opBITL reg bit\r
+       and z80f,z80f,#1<<CFlag\r
+       tst \reg,#1<<(16+\bit)\r
+       orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)\r
+       orrne z80f,z80f,#(1<<HFlag)\r
+       fetch 8\r
+.endm\r
+\r
+.macro opBIT7L reg\r
+       and z80f,z80f,#1<<CFlag\r
+       tst \reg,#1<<(16+7)\r
+       orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)\r
+       orrne z80f,z80f,#(1<<HFlag)|(1<<SFlag)\r
+       fetch 8\r
+.endm\r
+\r
+.macro opBITb bit\r
+       and z80f,z80f,#1<<CFlag\r
+       tst r0,#1<<\bit\r
+       orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)\r
+       orrne z80f,z80f,#(1<<HFlag)\r
+.endm\r
+\r
+.macro opBIT7b\r
+       and z80f,z80f,#1<<CFlag\r
+       tst r0,#1<<7\r
+       orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)\r
+       orrne z80f,z80f,#(1<<HFlag)|(1<<SFlag)\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opCP reg shift\r
+       mov r1,z80a,lsl#4                                               ;@ prepare for check of half carry\r
+       cmp z80a,\reg,lsl#\shift\r
+       mrs z80f,cpsr\r
+       mov z80f,z80f,lsr#28                                    ;@ S,Z,V&C\r
+       eor z80f,z80f,#(1<<CFlag)|(1<<NFlag)    ;@ invert C and set n\r
+       cmp r1,\reg,lsl#\shift+4\r
+       orrcc z80f,z80f,#1<<HFlag\r
+.endm\r
+\r
+.macro opCPA\r
+       mov z80f,#(1<<ZFlag)|(1<<NFlag)                 ;@ set Z & n\r
+       fetch 4\r
+.endm\r
+\r
+.macro opCPH reg\r
+       and r0,\reg,#0xFF000000\r
+       opCP r0 0\r
+       fetch 4\r
+.endm\r
+\r
+.macro opCPL reg\r
+       opCP \reg 8\r
+       fetch 4\r
+.endm\r
+\r
+.macro opCPb\r
+       opCP r0 24\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opDEC8 reg                                                      ;@for A and memory\r
+       and z80f,z80f,#1<<CFlag                                 ;@save carry\r
+       orr z80f,z80f,#1<<NFlag                                 ;@set n\r
+       tst \reg,#0x0f000000\r
+       orreq z80f,z80f,#1<<HFlag\r
+       subs \reg,\reg,#0x01000000\r
+       orrmi z80f,z80f,#1<<SFlag\r
+       orrvs z80f,z80f,#1<<VFlag\r
+       orreq z80f,z80f,#1<<ZFlag\r
+.endm\r
+\r
+.macro opDEC8H reg                                                     ;@for B, D & H\r
+       and z80f,z80f,#1<<CFlag                                 ;@save carry\r
+       orr z80f,z80f,#1<<NFlag                                 ;@set n\r
+       tst \reg,#0x0f000000\r
+       orreq z80f,z80f,#1<<HFlag\r
+       subs \reg,\reg,#0x01000000\r
+       orrmi z80f,z80f,#1<<SFlag\r
+       orrvs z80f,z80f,#1<<VFlag\r
+       tst \reg,#0xff000000                                    ;@Z\r
+       orreq z80f,z80f,#1<<ZFlag\r
+.endm\r
+\r
+.macro opDEC8L reg                                                     ;@for C, E & L\r
+       mov \reg,\reg,ror#24\r
+       opDEC8H \reg\r
+       mov \reg,\reg,ror#8\r
+.endm\r
+\r
+.macro opDEC8b                                                         ;@for memory\r
+       mov r0,r0,lsl#24\r
+       opDEC8 r0\r
+       mov r0,r0,lsr#24\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opIN\r
+       stmfd sp!,{r3,r12}\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_in]                             ;@ r0=port - data returned in r0\r
+       ldmfd sp!,{r3,r12}\r
+.endm\r
+\r
+.macro opIN_C\r
+       mov r0,z80bc, lsr #16\r
+       opIN\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opINC8 reg                                                      ;@for A and memory\r
+       and z80f,z80f,#1<<CFlag                                 ;@save carry, clear n\r
+       adds \reg,\reg,#0x01000000\r
+       orrmi z80f,z80f,#1<<SFlag\r
+       orrvs z80f,z80f,#1<<VFlag\r
+       orrcs z80f,z80f,#1<<ZFlag                               ;@cs when going from 0xFF to 0x00\r
+       tst \reg,#0x0f000000\r
+       orreq z80f,z80f,#1<<HFlag\r
+.endm\r
+\r
+.macro opINC8H reg                                                     ;@for B, D & H\r
+       opINC8 \reg\r
+.endm\r
+\r
+.macro opINC8L reg                                                     ;@for C, E & L\r
+       mov \reg,\reg,ror#24\r
+       opINC8 \reg\r
+       mov \reg,\reg,ror#8\r
+.endm\r
+\r
+.macro opINC8b                                                         ;@for memory\r
+       mov r0,r0,lsl#24\r
+       opINC8 r0\r
+       mov r0,r0,lsr#24\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opOR reg shift\r
+       orr z80a,z80a,\reg,lsl#\shift\r
+       sub r0,opcodes,#0x100\r
+       ldrb z80f,[r0,z80a, lsr #24]\r
+.endm\r
+\r
+.macro opORA\r
+       sub r0,opcodes,#0x100\r
+       ldrb z80f,[r0,z80a, lsr #24]\r
+       fetch 4\r
+.endm\r
+\r
+.macro opORH reg\r
+       and r0,\reg,#0xFF000000\r
+       opOR r0 0\r
+       fetch 4\r
+.endm\r
+\r
+.macro opORL reg\r
+       opOR \reg 8\r
+       fetch 4\r
+.endm\r
+\r
+.macro opORb\r
+       opOR r0 24\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opOUT\r
+       stmfd sp!,{r3,r12}\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_out]                    ;@ r0=port r1=data\r
+       ldmfd sp!,{r3,r12}\r
+.endm\r
+\r
+.macro opOUT_C\r
+       mov r0,z80bc, lsr #16\r
+       opOUT\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opPOP\r
+.if FAST_Z80SP\r
+.if DRZ80_FOR_PICODRIVE\r
+    @ notaz: try to protect against stack overflows, which tend to happen in Picodrive because of poor timing\r
+    ldr r2,[cpucontext,#z80sp_base]\r
+       ldrb r0,[z80sp],#1\r
+    add r2,r2,#0x2000\r
+    cmp z80sp,r2\r
+@    subge z80sp,z80sp,#0x2000 @ unstable?\r
+       ldrb r1,[z80sp],#1\r
+    cmp z80sp,r2\r
+@    subge z80sp,z80sp,#0x2000\r
+       orr r0,r0,r1, lsl #8\r
+.else\r
+       ldrb r0,[z80sp],#1\r
+       ldrb r1,[z80sp],#1\r
+       orr r0,r0,r1, lsl #8\r
+.endif\r
+.else\r
+       mov r0,z80sp\r
+       readmem16\r
+       add z80sp,z80sp,#2\r
+.endif\r
+.endm\r
+\r
+.macro opPOPreg reg\r
+       opPOP\r
+       mov \reg,r0, lsl #16\r
+       fetch 10\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opPUSHareg reg @ reg > r1\r
+.if FAST_Z80SP\r
+.if DRZ80_FOR_PICODRIVE\r
+    @ notaz: try to protect against stack overflows, which tend to happen in Picodrive because of poor timing\r
+    ldr r0,[cpucontext,#z80sp_base]\r
+    cmp z80sp,r0\r
+    addle z80sp,z80sp,#0x2000\r
+    mov r1,\reg, lsr #8\r
+       strb r1,[z80sp,#-1]!\r
+    cmp z80sp,r0\r
+    addle z80sp,z80sp,#0x2000\r
+       strb \reg,[z80sp,#-1]!\r
+.else\r
+       mov r1,\reg, lsr #8\r
+       strb r1,[z80sp,#-1]!\r
+       strb \reg,[z80sp,#-1]!\r
+.endif\r
+.else\r
+    mov r0,\reg\r
+       sub z80sp,z80sp,#2\r
+       mov r1,z80sp\r
+       writemem16\r
+.endif\r
+.endm\r
+\r
+.macro opPUSHreg reg\r
+.if FAST_Z80SP\r
+.if DRZ80_FOR_PICODRIVE\r
+    ldr r0,[cpucontext,#z80sp_base]\r
+    cmp z80sp,r0\r
+    addle z80sp,z80sp,#0x2000\r
+    mov r1,\reg, lsr #24\r
+       strb r1,[z80sp,#-1]!\r
+    cmp z80sp,r0\r
+    addle z80sp,z80sp,#0x2000\r
+       mov r1,\reg, lsr #16\r
+       strb r1,[z80sp,#-1]!\r
+.else\r
+    mov r1,\reg, lsr #24\r
+       strb r1,[z80sp,#-1]!\r
+       mov r1,\reg, lsr #16\r
+       strb r1,[z80sp,#-1]!\r
+.endif\r
+.else\r
+       mov r0,\reg,lsr #16\r
+       sub z80sp,z80sp,#2\r
+       mov r1,z80sp\r
+       writemem16\r
+.endif\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opRESmemHL bit\r
+.if DRZ80_FOR_PICODRIVE\r
+       mov r0,z80hl, lsr #16\r
+    bl pico_z80_read8\r
+       bic r0,r0,#1<<\bit\r
+       mov r1,z80hl, lsr #16\r
+    bl pico_z80_write8\r
+.else\r
+       mov r0,z80hl, lsr #16\r
+       stmfd sp!,{r3,r12}\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_read8]                  ;@ r0 = addr - data returned in r0\r
+       bic r0,r0,#1<<\bit\r
+       mov r1,z80hl, lsr #16\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_write8]                 ;@ r0=data r1=addr\r
+       ldmfd sp!,{r3,r12}\r
+.endif\r
+    fetch 15\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opRESmem bit\r
+.if DRZ80_FOR_PICODRIVE\r
+       stmfd sp!,{r0}                                                  ;@ save addr as well\r
+    bl pico_z80_read8\r
+       bic r0,r0,#1<<\bit\r
+       ldmfd sp!,{r1}                                                  ;@ restore addr into r1\r
+    bl pico_z80_write8\r
+.else\r
+       stmfd sp!,{r3,r12}\r
+       stmfd sp!,{r0}                                                  ;@ save addr as well\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_read8]                  ;@ r0=addr - data returned in r0\r
+       bic r0,r0,#1<<\bit\r
+       ldmfd sp!,{r1}                                                  ;@ restore addr into r1\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_write8]                 ;@ r0=data r1=addr\r
+       ldmfd sp!,{r3,r12}\r
+.endif\r
+       fetch 23\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opRL reg1 reg2 shift\r
+       movs \reg1,\reg2,lsl \shift\r
+       tst z80f,#1<<CFlag                                              ;@doesn't affect ARM carry, as long as the imidiate value is < 0x100. Watch out!\r
+       orrne \reg1,\reg1,#0x01000000\r
+;@     and r2,z80f,#1<<CFlag\r
+;@     orr $x,$x,r2,lsl#23\r
+       sub r1,opcodes,#0x100\r
+       ldrb z80f,[r1,\reg1,lsr#24]                             ;@get PZS\r
+       orrcs z80f,z80f,#1<<CFlag\r
+.endm\r
+\r
+.macro opRLA\r
+       opRL z80a, z80a, #1\r
+       fetch 8\r
+.endm\r
+\r
+.macro opRLH reg\r
+       and r0,\reg,#0xFF000000                                 ;@mask high to r0\r
+       adds \reg,\reg,r0\r
+       tst z80f,#1<<CFlag                                              ;@doesn't affect ARM carry, as long as the imidiate value is < 0x100. Watch out!\r
+       orrne \reg,\reg,#0x01000000\r
+       sub r1,opcodes,#0x100\r
+       ldrb z80f,[r1,\reg,lsr#24]                              ;@get PZS\r
+       orrcs z80f,z80f,#1<<CFlag\r
+       fetch 8\r
+.endm\r
+\r
+.macro opRLL reg\r
+       opRL r0, \reg, #9\r
+       and \reg,\reg,#0xFF000000                               ;@mask out high\r
+       orr \reg,\reg,r0,lsr#8\r
+       fetch 8\r
+.endm\r
+\r
+.macro opRLb\r
+       opRL r0, r0, #25\r
+       mov r0,r0,lsr#24\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opRLC reg1 reg2 shift\r
+       movs \reg1,\reg2,lsl#\shift\r
+       orrcs \reg1,\reg1,#0x01000000\r
+       sub r1,opcodes,#0x100\r
+       ldrb z80f,[r1,\reg1,lsr#24]\r
+       orrcs z80f,z80f,#1<<CFlag\r
+.endm\r
+\r
+.macro opRLCA\r
+       opRLC z80a, z80a, 1\r
+       fetch 8\r
+.endm\r
+\r
+.macro opRLCH reg\r
+       and r0,\reg,#0xFF000000                                 ;@mask high to r0\r
+       adds \reg,\reg,r0\r
+       orrcs \reg,\reg,#0x01000000\r
+       sub r1,opcodes,#0x100\r
+       ldrb z80f,[r1,\reg,lsr#24]\r
+       orrcs z80f,z80f,#1<<CFlag\r
+       fetch 8\r
+.endm\r
+\r
+.macro opRLCL reg\r
+       opRLC r0, \reg, 9\r
+       and \reg,\reg,#0xFF000000                               ;@mask out high\r
+       orr \reg,\reg,r0,lsr#8\r
+       fetch 8\r
+.endm\r
+\r
+.macro opRLCb\r
+       opRLC r0, r0, 25\r
+       mov r0,r0,lsr#24\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opRR reg1 reg2 shift\r
+       movs \reg1,\reg2,lsr#\shift\r
+       tst z80f,#1<<CFlag                                              ;@doesn't affect ARM carry, as long as the imidiate value is < 0x100. Watch out!\r
+       orrne \reg1,\reg1,#0x00000080\r
+;@     and r2,z80_f,#PSR_C\r
+;@     orr \reg1,\reg1,r2,lsl#6\r
+       sub r1,opcodes,#0x100\r
+       ldrb z80f,[r1,\reg1]\r
+       orrcs z80f,z80f,#1<<CFlag\r
+.endm\r
+\r
+.macro opRRA\r
+       orr z80a,z80a,z80f,lsr#1                                ;@get C\r
+       movs z80a,z80a,ror#25\r
+       mov z80a,z80a,lsl#24\r
+       sub r1,opcodes,#0x100\r
+       ldrb z80f,[r1,z80a,lsr#24]\r
+       orrcs z80f,z80f,#1<<CFlag\r
+       fetch 8\r
+.endm\r
+\r
+.macro opRRH reg\r
+       orr r0,\reg,z80f,lsr#1                                  ;@get C\r
+       movs r0,r0,ror#25\r
+       and \reg,\reg,#0x00FF0000                               ;@mask out low\r
+       orr \reg,\reg,r0,lsl#24\r
+       sub r1,opcodes,#0x100\r
+       ldrb z80f,[r1,\reg,lsr#24]\r
+       orrcs z80f,z80f,#1<<CFlag\r
+       fetch 8\r
+.endm\r
+\r
+.macro opRRL reg\r
+       and r0,\reg,#0x00FF0000                                 ;@mask out low to r0\r
+       opRR r0 r0 17\r
+       and \reg,\reg,#0xFF000000                               ;@mask out high\r
+       orr \reg,\reg,r0,lsl#16\r
+       fetch 8\r
+.endm\r
+\r
+.macro opRRb\r
+       opRR r0 r0 1\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opRRC reg1 reg2 shift\r
+       movs \reg1,\reg2,lsr#\shift\r
+       orrcs \reg1,\reg1,#0x00000080\r
+       sub r1,opcodes,#0x100\r
+       ldrb z80f,[r1,\reg1]\r
+       orrcs z80f,z80f,#1<<CFlag\r
+.endm\r
+\r
+.macro opRRCA\r
+       opRRC z80a, z80a, 25\r
+       mov z80a,z80a,lsl#24\r
+       fetch 8\r
+.endm\r
+\r
+.macro opRRCH reg\r
+       opRRC r0, \reg, 25\r
+       and \reg,\reg,#0x00FF0000                               ;@mask out low\r
+       orr \reg,\reg,r0,lsl#24\r
+       fetch 8\r
+.endm\r
+\r
+.macro opRRCL reg\r
+       and r0,\reg,#0x00FF0000                                 ;@mask low to r0\r
+       opRRC r0, r0, 17\r
+       and \reg,\reg,#0xFF000000                               ;@mask out high\r
+       orr \reg,\reg,r0,lsl#16\r
+       fetch 8\r
+.endm\r
+\r
+.macro opRRCb\r
+       opRRC r0, r0, 1\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opRST addr\r
+       ldr r0,[cpucontext,#z80pc_base]\r
+       sub r2,z80pc,r0\r
+    opPUSHareg r2\r
+       mov r0,#\addr\r
+       rebasepc\r
+       fetch 11\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opSBC\r
+       eor z80f,z80f,#1<<CFlag                                 ;@ invert C\r
+       movs z80f,z80f,lsr#2                                    ;@ get C\r
+       subcc r0,r0,#0x100\r
+       eor z80f,r0,z80a,lsr#24                                 ;@ prepare for check of H\r
+       sbcs z80a,z80a,r0,ror#8\r
+       mrs r0,cpsr\r
+       eor z80f,z80f,z80a,lsr#24\r
+       and z80f,z80f,#1<<HFlag                                 ;@ H, correct\r
+       orr z80f,z80f,r0,lsr#28                                 ;@ S,Z,V&C\r
+       eor z80f,z80f,#(1<<CFlag)|(1<<NFlag)    ;@ invert C and set n.\r
+.endm\r
+\r
+.macro opSBCA\r
+       movs z80f,z80f,lsr#2                                    ;@ get C\r
+       movcc z80a,#0x00000000\r
+       movcs z80a,#0xFF000000\r
+       movcc z80f,#(1<<NFlag)|(1<<ZFlag)\r
+       movcs z80f,#(1<<NFlag)|(1<<SFlag)|(1<<CFlag)|(1<<HFlag)\r
+       fetch 4\r
+.endm\r
+\r
+.macro opSBCH reg\r
+       mov r0,\reg,lsr#24\r
+       opSBC\r
+       fetch 4\r
+.endm\r
+\r
+.macro opSBCL reg\r
+       mov r0,\reg,lsl#8\r
+       eor z80f,z80f,#1<<CFlag                                 ;@ invert C\r
+       movs z80f,z80f,lsr#2                                    ;@ get C\r
+       sbccc r0,r0,#0xFF000000\r
+       mov r1,z80a,lsl#4                                               ;@ prepare for check of H\r
+       sbcs z80a,z80a,r0\r
+       mrs z80f,cpsr\r
+       mov z80f,z80f,lsr#28                                    ;@ S,Z,V&C\r
+       eor z80f,z80f,#(1<<CFlag)|(1<<NFlag)    ;@ invert C and set n.\r
+       cmp r1,r0,lsl#4\r
+       orrcc z80f,z80f,#1<<HFlag                               ;@ H, correct\r
+       fetch 4\r
+.endm\r
+\r
+.macro opSBCb\r
+       opSBC\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opSBC16 reg\r
+       eor z80f,z80f,#1<<CFlag                                 ;@ invert C\r
+       movs z80f,z80f,lsr#2                                    ;@ get C\r
+       sbc r1,r1,r1                                                    ;@ set r1 to -1 or 0.\r
+       orr r0,\reg,r1,lsr#16\r
+       mov r1,z80hl,lsl#4                                              ;@ prepare for check of H\r
+       sbcs z80hl,z80hl,r0\r
+       mrs z80f,cpsr\r
+       mov z80f,z80f,lsr#28                                    ;@ S,Z,V&C\r
+       eor z80f,z80f,#(1<<CFlag)|(1<<NFlag)    ;@ invert C and set n.\r
+       cmp r1,r0,lsl#4\r
+       orrcc z80f,z80f,#1<<HFlag                               ;@ H, correct\r
+       fetch 15\r
+.endm\r
+\r
+.macro opSBC16HL\r
+       movs z80f,z80f,lsr#2                                    ;@ get C\r
+       mov z80hl,#0x00000000\r
+       subcs z80hl,z80hl,#0x00010000\r
+       movcc z80f,#(1<<NFlag)|(1<<ZFlag)\r
+       movcs z80f,#(1<<NFlag)|(1<<SFlag)|(1<<CFlag)|(1<<HFlag)\r
+       fetch 15\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opSETmemHL bit\r
+.if DRZ80_FOR_PICODRIVE\r
+       mov r0,z80hl, lsr #16\r
+    bl pico_z80_read8\r
+       orr r0,r0,#1<<\bit\r
+       mov r1,z80hl, lsr #16\r
+    bl pico_z80_write8\r
+.else\r
+       mov r0,z80hl, lsr #16\r
+       stmfd sp!,{r3,r12}\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_read8]                  ;@ r0 = addr - data returned in r0\r
+       orr r0,r0,#1<<\bit\r
+       mov r1,z80hl, lsr #16\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_write8]                 ;@ r0=data r1=addr\r
+       ldmfd sp!,{r3,r12}\r
+.endif\r
+    fetch 15\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opSETmem bit\r
+.if DRZ80_FOR_PICODRIVE\r
+       stmfd sp!,{r0}  ;@ save addr as well\r
+    bl pico_z80_read8\r
+       orr r0,r0,#1<<\bit\r
+       ldmfd sp!,{r1}  ;@ restore addr into r1\r
+    bl pico_z80_write8\r
+.else\r
+       stmfd sp!,{r3,r12}\r
+       stmfd sp!,{r0}  ;@ save addr as well\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_read8]                  ;@ r0=addr - data returned in r0\r
+       orr r0,r0,#1<<\bit\r
+       ldmfd sp!,{r1}  ;@ restore addr into r1\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_write8]                 ;@ r0=data r1=addr\r
+       ldmfd sp!,{r3,r12}\r
+.endif\r
+       fetch 23\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opSLA reg1 reg2 shift\r
+       movs \reg1,\reg2,lsl#\shift\r
+       sub r1,opcodes,#0x100\r
+       ldrb z80f,[r1,\reg1,lsr#24]\r
+       orrcs z80f,z80f,#1<<CFlag\r
+.endm\r
+\r
+.macro opSLAA\r
+       opSLA z80a, z80a, 1\r
+       fetch 8\r
+.endm\r
+\r
+.macro opSLAH reg\r
+       and r0,\reg,#0xFF000000                                 ;@mask high to r0\r
+       adds \reg,\reg,r0\r
+       sub r1,opcodes,#0x100\r
+       ldrb z80f,[r1,\reg,lsr#24]\r
+       orrcs z80f,z80f,#1<<CFlag\r
+       fetch 8\r
+.endm\r
+\r
+.macro opSLAL reg\r
+       opSLA r0, \reg, 9\r
+       and \reg,\reg,#0xFF000000                               ;@mask out high\r
+       orr \reg,\reg,r0,lsr#8\r
+       fetch 8\r
+.endm\r
+\r
+.macro opSLAb\r
+       opSLA r0, r0, 25\r
+       mov r0,r0,lsr#24\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opSLL reg1 reg2 shift\r
+       movs \reg1,\reg2,lsl#\shift\r
+       orr \reg1,\reg1,#0x01000000\r
+       sub r1,opcodes,#0x100\r
+       ldrb z80f,[r1,\reg1,lsr#24]\r
+       orrcs z80f,z80f,#1<<CFlag\r
+.endm\r
+\r
+.macro opSLLA\r
+       opSLL z80a, z80a, 1\r
+       fetch 8\r
+.endm\r
+\r
+.macro opSLLH reg\r
+       and r0,\reg,#0xFF000000                                 ;@mask high to r0\r
+       adds \reg,\reg,r0\r
+       orr \reg,\reg,#0x01000000\r
+       sub r1,opcodes,#0x100\r
+       ldrb z80f,[r1,\reg,lsr#24]\r
+       orrcs z80f,z80f,#1<<CFlag\r
+       fetch 8\r
+.endm\r
+\r
+.macro opSLLL reg\r
+       opSLL r0, \reg, 9\r
+       and \reg,\reg,#0xFF000000                               ;@mask out high\r
+       orr \reg,\reg,r0,lsr#8\r
+       fetch 8\r
+.endm\r
+\r
+.macro opSLLb\r
+       opSLL r0, r0, 25\r
+       mov r0,r0,lsr#24\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opSRA reg1 reg2\r
+       movs \reg1,\reg2,asr#25\r
+       and \reg1,\reg1,#0xFF\r
+       sub r1,opcodes,#0x100\r
+       ldrb z80f,[r1,\reg1]\r
+       orrcs z80f,z80f,#1<<CFlag\r
+.endm\r
+\r
+.macro opSRAA\r
+       movs r0,z80a,asr#25\r
+       mov z80a,r0,lsl#24\r
+       sub r1,opcodes,#0x100\r
+       ldrb z80f,[r1,z80a,lsr#24]\r
+       orrcs z80f,z80f,#1<<CFlag\r
+       fetch 8\r
+.endm\r
+\r
+.macro opSRAH reg\r
+       movs r0,\reg,asr#25\r
+       and \reg,\reg,#0x00FF0000                               ;@mask out low\r
+       orr \reg,\reg,r0,lsl#24\r
+       sub r1,opcodes,#0x100\r
+       ldrb z80f,[r1,\reg,lsr#24]\r
+       orrcs z80f,z80f,#1<<CFlag\r
+       fetch 8\r
+.endm\r
+\r
+.macro opSRAL reg\r
+       mov r0,\reg,lsl#8\r
+       opSRA r0, r0\r
+       and \reg,\reg,#0xFF000000                               ;@mask out high\r
+       orr \reg,\reg,r0,lsl#16\r
+       fetch 8\r
+.endm\r
+\r
+.macro opSRAb\r
+       mov r0,r0,lsl#24\r
+       opSRA r0, r0\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opSRL reg1 reg2 shift\r
+       movs \reg1,\reg2,lsr#\shift\r
+       sub r1,opcodes,#0x100\r
+       ldrb z80f,[r1,\reg1]\r
+       orrcs z80f,z80f,#1<<CFlag\r
+.endm\r
+\r
+.macro opSRLA\r
+       opSRL z80a, z80a, 25\r
+       mov z80a,z80a,lsl#24\r
+       fetch 8\r
+.endm\r
+\r
+.macro opSRLH reg\r
+       opSRL r0, \reg, 25\r
+       and \reg,\reg,#0x00FF0000                               ;@mask out low\r
+       orr \reg,\reg,r0,lsl#24\r
+       fetch 8\r
+.endm\r
+\r
+.macro opSRLL reg\r
+       mov r0,\reg,lsl#8\r
+       opSRL r0, r0, 25\r
+       and \reg,\reg,#0xFF000000                               ;@mask out high\r
+       orr \reg,\reg,r0,lsl#16\r
+       fetch 8\r
+.endm\r
+\r
+.macro opSRLb\r
+       opSRL r0, r0, 1\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opSUB reg shift\r
+       mov r1,z80a,lsl#4                                               ;@ Prepare for check of half carry\r
+       subs z80a,z80a,\reg,lsl#\shift\r
+       mrs z80f,cpsr\r
+       mov z80f,z80f,lsr#28                                    ;@ S,Z,V&C\r
+       eor z80f,z80f,#(1<<CFlag)|(1<<NFlag)    ;@ invert C and set n\r
+       cmp r1,\reg,lsl#\shift+4\r
+       orrcc z80f,z80f,#1<<HFlag\r
+.endm\r
+\r
+.macro opSUBA\r
+       mov z80a,#0\r
+       mov z80f,#(1<<ZFlag)|(1<<NFlag)                 ;@ set Z & n\r
+       fetch 4\r
+.endm\r
+\r
+.macro opSUBH reg\r
+       and r0,\reg,#0xFF000000\r
+       opSUB r0, 0\r
+       fetch 4\r
+.endm\r
+\r
+.macro opSUBL reg\r
+       opSUB \reg, 8\r
+       fetch 4\r
+.endm\r
+\r
+.macro opSUBb\r
+       opSUB r0, 24\r
+.endm\r
+;@---------------------------------------\r
+\r
+.macro opXOR reg shift\r
+       eor z80a,z80a,\reg,lsl#\shift\r
+       sub r0,opcodes,#0x100\r
+       ldrb z80f,[r0,z80a, lsr #24]\r
+.endm\r
+\r
+.macro opXORA\r
+       mov z80a,#0\r
+       mov z80f,#(1<<ZFlag)|(1<<VFlag)\r
+       fetch 4\r
+.endm\r
+\r
+.macro opXORH reg\r
+       and r0,\reg,#0xFF000000\r
+       opXOR r0, 0\r
+       fetch 4\r
+.endm\r
+\r
+.macro opXORL reg\r
+       opXOR \reg, 8\r
+       fetch 4\r
+.endm\r
+\r
+.macro opXORb\r
+       opXOR r0, 24\r
+.endm\r
+;@---------------------------------------\r
+\r
+\r
+;@ --------------------------- Framework --------------------------\r
+    \r
+.text\r
+\r
+DrZ80Run:\r
+       ;@ r0 = pointer to cpu context\r
+       ;@ r1 = ISTATES to execute  \r
+       ;@#########################################   \r
+       stmdb sp!,{r4-r12,lr}                                   ;@ save registers on stack\r
+       mov cpucontext,r0                                               ;@ setup main memory pointer\r
+       mov z80_icount,r1                                               ;@ setup number of Tstates to execute\r
+\r
+.if INTERRUPT_MODE == 0\r
+       ldrh r0,[cpucontext,#z80irq] @ 0x4C\r
+.endif\r
+       ldmia cpucontext,{z80pc-z80sp}                  ;@ load Z80 registers\r
+\r
+.if INTERRUPT_MODE == 0\r
+       ;@ check ints\r
+       tst r0,#1\r
+       movnes r0,r0,lsr #8\r
+    blne DoInterrupt\r
+.endif\r
+\r
+       ldrb r0,[z80pc],#1    ;@ get first op code\r
+       ldr opcodes,MAIN_opcodes_POINTER2\r
+       ldr pc,[opcodes,r0, lsl #2]  ;@ execute op code\r
+\r
+MAIN_opcodes_POINTER2: .word MAIN_opcodes\r
+\r
+\r
+z80_execute_end:\r
+       ;@ save registers in CPU context\r
+       stmia cpucontext,{z80pc-z80sp}                  ;@ save Z80 registers\r
+    mov r0,z80_icount\r
+       ldmia sp!,{r4-r12,pc}                                   ;@ restore registers from stack and return to C code\r
+\r
+.if INTERRUPT_MODE\r
+Interrupt_local: .word Interrupt\r
+.endif\r
+\r
+DoInterrupt:\r
+.if INTERRUPT_MODE\r
+       ;@ Don't do own int handler, call mames instead\r
+\r
+       ;@ save everything back into DrZ80 context\r
+       stmia cpucontext,{z80pc-z80sp}                  ;@ save Z80 registers\r
+       stmfd sp!,{r3,r4,r5,lr}                                 ;@ save rest of regs on stack\r
+       mov lr,pc\r
+       ldr pc,Interrupt_local\r
+       ldmfd sp!,{r3,r4,r5,lr}                                 ;@ load regs from stack\r
+       ;@ reload regs from DrZ80 context\r
+       ldmia cpucontext,{z80pc-z80sp}                  ;@ load Z80 registers\r
+       mov pc,lr ;@ return\r
+.else\r
+       stmfd sp!,{lr}\r
+\r
+       tst r0,#4 ;@ check halt\r
+       addne z80pc,z80pc,#1\r
+\r
+       ldrb r1,[cpucontext,#z80im]\r
+\r
+    ;@ clear halt and int flags\r
+       eor r0,r0,r0\r
+       strb r0,[cpucontext,#z80if]\r
+\r
+       ;@ now check int mode\r
+    tst r1,#1\r
+    bne DoInterrupt_mode1\r
+    tst r1,#2\r
+    bne DoInterrupt_mode2\r
+    b   DoInterrupt_mode0\r
+\r
+DoInterrupt_mode0:\r
+       ;@ get 3 byte vector\r
+       ldr r2,[cpucontext, #z80irqvector]\r
+       and r1,r2,#0xFF0000\r
+       cmp r1,#0xCD0000  ;@ call\r
+       bne 1f\r
+       ;@ ########\r
+       ;@ # call\r
+       ;@ ########\r
+       ;@ save current pc on stack\r
+       ldr r0,[cpucontext,#z80pc_base]\r
+       sub r0,z80pc,r0\r
+.if FAST_Z80SP\r
+       mov r1,r0, lsr #8\r
+       strb r1,[z80sp,#-1]!\r
+       strb r0,[z80sp,#-1]!\r
+.else\r
+       sub z80sp,z80sp,#2\r
+       mov r1,z80sp\r
+       writemem16\r
+       ldr r2,[cpucontext, #z80irqvector]\r
+.endif\r
+       ;@ jump to vector\r
+       mov r2,r2,lsl#16\r
+       mov r0,r2,lsr#16\r
+       ;@ rebase new pc\r
+       rebasepc\r
+\r
+       b DoInterrupt_end\r
+\r
+1:\r
+       cmp r1,#0xC30000  ;@ jump\r
+       bne DoInterrupt_mode1    ;@ rst\r
+       ;@ #######\r
+       ;@ # jump\r
+       ;@ #######\r
+       ;@ jump to vector\r
+       mov r2,r2,lsl#16\r
+       mov r0,r2,lsr#16\r
+       ;@ rebase new pc\r
+       rebasepc\r
+\r
+       b DoInterrupt_end\r
+\r
+DoInterrupt_mode1:\r
+       ldr r0,[cpucontext,#z80pc_base]\r
+       sub r2,z80pc,r0\r
+    opPUSHareg r2\r
+       mov r0,#0x38\r
+       rebasepc\r
+\r
+       b DoInterrupt_end\r
+\r
+DoInterrupt_mode2:\r
+       ;@ push pc on stack\r
+       ldr r0,[cpucontext,#z80pc_base]\r
+       sub r2,z80pc,r0\r
+    opPUSHareg r2\r
+\r
+       ;@ get 1 byte vector address\r
+       ldrb r0,[cpucontext, #z80irqvector]\r
+       ldr r1,[cpucontext, #z80i]\r
+       orr r0,r0,r1,lsr#16\r
+\r
+       ;@ read new pc from vector address\r
+.if DRZ80_FOR_PICODRIVE\r
+    bl pico_z80_read16\r
+    bic r0,r0,#0xfe000\r
+    ldr r1,[cpucontext,#z80pc_base]\r
+    add z80pc,r1,r0\r
+.if UPDATE_CONTEXT\r
+     str z80pc,[cpucontext,#z80pc_pointer]\r
+.endif\r
+.else\r
+       stmfd sp!,{r3,r12}\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_read16]\r
+\r
+       ;@ rebase new pc\r
+.if UPDATE_CONTEXT\r
+     str z80pc,[cpucontext,#z80pc_pointer]\r
+.endif\r
+       mov lr,pc\r
+       ldr pc,[cpucontext,#z80_rebasePC] ;@ r0=new pc - external function sets z80pc_base and returns new z80pc in r0\r
+       ldmfd sp!,{r3,r12}\r
+       mov z80pc,r0    \r
+.endif\r
+\r
+DoInterrupt_end:\r
+       ;@ interupt accepted so callback irq interface\r
+       ldr r0,[cpucontext, #z80irqcallback]\r
+       tst r0,r0\r
+       ldmeqfd sp!,{pc}\r
+       stmfd sp!,{r3,r12}\r
+       mov lr,pc\r
+       mov pc,r0    ;@ call callback function\r
+       ldmfd sp!,{r3,r12}\r
+       ldmfd sp!,{pc} ;@ return\r
+\r
+.endif\r
+\r
+.data\r
+.align 4\r
+\r
+DAATable: .hword  (0x00<<8)|(1<<ZFlag)|(1<<VFlag)\r
+         .hword  (0x01<<8)                  \r
+         .hword  (0x02<<8)                  \r
+         .hword  (0x03<<8)               |(1<<VFlag)\r
+         .hword  (0x04<<8)                  \r
+         .hword  (0x05<<8)               |(1<<VFlag)\r
+         .hword  (0x06<<8)               |(1<<VFlag)\r
+         .hword  (0x07<<8)                  \r
+         .hword  (0x08<<8)               \r
+         .hword  (0x09<<8)            |(1<<VFlag)\r
+         .hword  (0x10<<8)         |(1<<HFlag)      \r
+         .hword  (0x11<<8)         |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x12<<8)         |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x13<<8)         |(1<<HFlag)      \r
+         .hword  (0x14<<8)         |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x15<<8)         |(1<<HFlag)      \r
+         .hword  (0x10<<8)                  \r
+         .hword  (0x11<<8)               |(1<<VFlag)\r
+         .hword  (0x12<<8)               |(1<<VFlag)\r
+         .hword  (0x13<<8)                  \r
+         .hword  (0x14<<8)               |(1<<VFlag)\r
+         .hword  (0x15<<8)                  \r
+         .hword  (0x16<<8)                  \r
+         .hword  (0x17<<8)               |(1<<VFlag)\r
+         .hword  (0x18<<8)            |(1<<VFlag)\r
+         .hword  (0x19<<8)               \r
+         .hword  (0x20<<8)      |(1<<HFlag)      \r
+         .hword  (0x21<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x22<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x23<<8)      |(1<<HFlag)      \r
+         .hword  (0x24<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x25<<8)      |(1<<HFlag)      \r
+         .hword  (0x20<<8)               \r
+         .hword  (0x21<<8)            |(1<<VFlag)\r
+         .hword  (0x22<<8)            |(1<<VFlag)\r
+         .hword  (0x23<<8)               \r
+         .hword  (0x24<<8)            |(1<<VFlag)\r
+         .hword  (0x25<<8)               \r
+         .hword  (0x26<<8)               \r
+         .hword  (0x27<<8)            |(1<<VFlag)\r
+         .hword  (0x28<<8)         |(1<<VFlag)\r
+         .hword  (0x29<<8)            \r
+         .hword  (0x30<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x31<<8)      |(1<<HFlag)      \r
+         .hword  (0x32<<8)      |(1<<HFlag)      \r
+         .hword  (0x33<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x34<<8)      |(1<<HFlag)      \r
+         .hword  (0x35<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x30<<8)            |(1<<VFlag)\r
+         .hword  (0x31<<8)               \r
+         .hword  (0x32<<8)               \r
+         .hword  (0x33<<8)            |(1<<VFlag)\r
+         .hword  (0x34<<8)               \r
+         .hword  (0x35<<8)            |(1<<VFlag)\r
+         .hword  (0x36<<8)            |(1<<VFlag)\r
+         .hword  (0x37<<8)               \r
+         .hword  (0x38<<8)            \r
+         .hword  (0x39<<8)         |(1<<VFlag)\r
+         .hword  (0x40<<8)         |(1<<HFlag)      \r
+         .hword  (0x41<<8)         |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x42<<8)         |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x43<<8)         |(1<<HFlag)      \r
+         .hword  (0x44<<8)         |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x45<<8)         |(1<<HFlag)      \r
+         .hword  (0x40<<8)                  \r
+         .hword  (0x41<<8)               |(1<<VFlag)\r
+         .hword  (0x42<<8)               |(1<<VFlag)\r
+         .hword  (0x43<<8)                  \r
+         .hword  (0x44<<8)               |(1<<VFlag)\r
+         .hword  (0x45<<8)                  \r
+         .hword  (0x46<<8)                  \r
+         .hword  (0x47<<8)               |(1<<VFlag)\r
+         .hword  (0x48<<8)            |(1<<VFlag)\r
+         .hword  (0x49<<8)               \r
+         .hword  (0x50<<8)         |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x51<<8)         |(1<<HFlag)      \r
+         .hword  (0x52<<8)         |(1<<HFlag)      \r
+         .hword  (0x53<<8)         |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x54<<8)         |(1<<HFlag)      \r
+         .hword  (0x55<<8)         |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x50<<8)               |(1<<VFlag)\r
+         .hword  (0x51<<8)                  \r
+         .hword  (0x52<<8)                  \r
+         .hword  (0x53<<8)               |(1<<VFlag)\r
+         .hword  (0x54<<8)                  \r
+         .hword  (0x55<<8)               |(1<<VFlag)\r
+         .hword  (0x56<<8)               |(1<<VFlag)\r
+         .hword  (0x57<<8)                  \r
+         .hword  (0x58<<8)               \r
+         .hword  (0x59<<8)            |(1<<VFlag)\r
+         .hword  (0x60<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x61<<8)      |(1<<HFlag)      \r
+         .hword  (0x62<<8)      |(1<<HFlag)      \r
+         .hword  (0x63<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x64<<8)      |(1<<HFlag)      \r
+         .hword  (0x65<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x60<<8)            |(1<<VFlag)\r
+         .hword  (0x61<<8)               \r
+         .hword  (0x62<<8)               \r
+         .hword  (0x63<<8)            |(1<<VFlag)\r
+         .hword  (0x64<<8)               \r
+         .hword  (0x65<<8)            |(1<<VFlag)\r
+         .hword  (0x66<<8)            |(1<<VFlag)\r
+         .hword  (0x67<<8)               \r
+         .hword  (0x68<<8)            \r
+         .hword  (0x69<<8)         |(1<<VFlag)\r
+         .hword  (0x70<<8)      |(1<<HFlag)      \r
+         .hword  (0x71<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x72<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x73<<8)      |(1<<HFlag)      \r
+         .hword  (0x74<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x75<<8)      |(1<<HFlag)      \r
+         .hword  (0x70<<8)               \r
+         .hword  (0x71<<8)            |(1<<VFlag)\r
+         .hword  (0x72<<8)            |(1<<VFlag)\r
+         .hword  (0x73<<8)               \r
+         .hword  (0x74<<8)            |(1<<VFlag)\r
+         .hword  (0x75<<8)               \r
+         .hword  (0x76<<8)               \r
+         .hword  (0x77<<8)            |(1<<VFlag)\r
+         .hword  (0x78<<8)         |(1<<VFlag)\r
+         .hword  (0x79<<8)            \r
+         .hword  (0x80<<8)|(1<<SFlag)      |(1<<HFlag)      \r
+         .hword  (0x81<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x82<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x83<<8)|(1<<SFlag)      |(1<<HFlag)      \r
+         .hword  (0x84<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x85<<8)|(1<<SFlag)      |(1<<HFlag)      \r
+         .hword  (0x80<<8)|(1<<SFlag)               \r
+         .hword  (0x81<<8)|(1<<SFlag)            |(1<<VFlag)\r
+         .hword  (0x82<<8)|(1<<SFlag)            |(1<<VFlag)\r
+         .hword  (0x83<<8)|(1<<SFlag)               \r
+         .hword  (0x84<<8)|(1<<SFlag)            |(1<<VFlag)\r
+         .hword  (0x85<<8)|(1<<SFlag)               \r
+         .hword  (0x86<<8)|(1<<SFlag)               \r
+         .hword  (0x87<<8)|(1<<SFlag)            |(1<<VFlag)\r
+         .hword  (0x88<<8)|(1<<SFlag)         |(1<<VFlag)\r
+         .hword  (0x89<<8)|(1<<SFlag)            \r
+         .hword  (0x90<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x91<<8)|(1<<SFlag)      |(1<<HFlag)      \r
+         .hword  (0x92<<8)|(1<<SFlag)      |(1<<HFlag)      \r
+         .hword  (0x93<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x94<<8)|(1<<SFlag)      |(1<<HFlag)      \r
+         .hword  (0x95<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x90<<8)|(1<<SFlag)            |(1<<VFlag)\r
+         .hword  (0x91<<8)|(1<<SFlag)               \r
+         .hword  (0x92<<8)|(1<<SFlag)               \r
+         .hword  (0x93<<8)|(1<<SFlag)            |(1<<VFlag)\r
+         .hword  (0x94<<8)|(1<<SFlag)               \r
+         .hword  (0x95<<8)|(1<<SFlag)            |(1<<VFlag)\r
+         .hword  (0x96<<8)|(1<<SFlag)            |(1<<VFlag)\r
+         .hword  (0x97<<8)|(1<<SFlag)               \r
+         .hword  (0x98<<8)|(1<<SFlag)            \r
+         .hword  (0x99<<8)|(1<<SFlag)         |(1<<VFlag)\r
+         .hword  (0x00<<8)   |(1<<ZFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x01<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x02<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x03<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x04<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x05<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x00<<8)   |(1<<ZFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x01<<8)                     |(1<<CFlag)\r
+         .hword  (0x02<<8)                     |(1<<CFlag)\r
+         .hword  (0x03<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x04<<8)                     |(1<<CFlag)\r
+         .hword  (0x05<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x06<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x07<<8)                     |(1<<CFlag)\r
+         .hword  (0x08<<8)                  |(1<<CFlag)\r
+         .hword  (0x09<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x10<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x11<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x12<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x13<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x14<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x15<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x10<<8)                     |(1<<CFlag)\r
+         .hword  (0x11<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x12<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x13<<8)                     |(1<<CFlag)\r
+         .hword  (0x14<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x15<<8)                     |(1<<CFlag)\r
+         .hword  (0x16<<8)                     |(1<<CFlag)\r
+         .hword  (0x17<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x18<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x19<<8)                  |(1<<CFlag)\r
+         .hword  (0x20<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x21<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x22<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x23<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x24<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x25<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x20<<8)                  |(1<<CFlag)\r
+         .hword  (0x21<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x22<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x23<<8)                  |(1<<CFlag)\r
+         .hword  (0x24<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x25<<8)                  |(1<<CFlag)\r
+         .hword  (0x26<<8)                  |(1<<CFlag)\r
+         .hword  (0x27<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x28<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x29<<8)               |(1<<CFlag)\r
+         .hword  (0x30<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x31<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x32<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x33<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x34<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x35<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x30<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x31<<8)                  |(1<<CFlag)\r
+         .hword  (0x32<<8)                  |(1<<CFlag)\r
+         .hword  (0x33<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x34<<8)                  |(1<<CFlag)\r
+         .hword  (0x35<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x36<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x37<<8)                  |(1<<CFlag)\r
+         .hword  (0x38<<8)               |(1<<CFlag)\r
+         .hword  (0x39<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x40<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x41<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x42<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x43<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x44<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x45<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x40<<8)                     |(1<<CFlag)\r
+         .hword  (0x41<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x42<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x43<<8)                     |(1<<CFlag)\r
+         .hword  (0x44<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x45<<8)                     |(1<<CFlag)\r
+         .hword  (0x46<<8)                     |(1<<CFlag)\r
+         .hword  (0x47<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x48<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x49<<8)                  |(1<<CFlag)\r
+         .hword  (0x50<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x51<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x52<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x53<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x54<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x55<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x50<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x51<<8)                     |(1<<CFlag)\r
+         .hword  (0x52<<8)                     |(1<<CFlag)\r
+         .hword  (0x53<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x54<<8)                     |(1<<CFlag)\r
+         .hword  (0x55<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x56<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x57<<8)                     |(1<<CFlag)\r
+         .hword  (0x58<<8)                  |(1<<CFlag)\r
+         .hword  (0x59<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x60<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x61<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x62<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x63<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x64<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x65<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x60<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x61<<8)                  |(1<<CFlag)\r
+         .hword  (0x62<<8)                  |(1<<CFlag)\r
+         .hword  (0x63<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x64<<8)                  |(1<<CFlag)\r
+         .hword  (0x65<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x66<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x67<<8)                  |(1<<CFlag)\r
+         .hword  (0x68<<8)               |(1<<CFlag)\r
+         .hword  (0x69<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x70<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x71<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x72<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x73<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x74<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x75<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x70<<8)                  |(1<<CFlag)\r
+         .hword  (0x71<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x72<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x73<<8)                  |(1<<CFlag)\r
+         .hword  (0x74<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x75<<8)                  |(1<<CFlag)\r
+         .hword  (0x76<<8)                  |(1<<CFlag)\r
+         .hword  (0x77<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x78<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x79<<8)               |(1<<CFlag)\r
+         .hword  (0x80<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x81<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x82<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x83<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x84<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x85<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x80<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0x81<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x82<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x83<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0x84<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x85<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0x86<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0x87<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x88<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x89<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0x90<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x91<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x92<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x93<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x94<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x95<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x90<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x91<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0x92<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0x93<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x94<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0x95<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x96<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x97<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0x98<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0x99<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xA0<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xA1<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xA2<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xA3<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xA4<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xA5<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xA0<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xA1<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xA2<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xA3<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xA4<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xA5<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xA6<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xA7<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xA8<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xA9<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xB0<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xB1<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xB2<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xB3<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xB4<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xB5<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xB0<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xB1<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xB2<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xB3<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xB4<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xB5<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xB6<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xB7<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xB8<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xB9<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xC0<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xC1<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xC2<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xC3<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xC4<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xC5<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xC0<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xC1<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0xC2<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0xC3<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xC4<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0xC5<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xC6<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xC7<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0xC8<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xC9<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xD0<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xD1<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xD2<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xD3<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xD4<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xD5<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xD0<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0xD1<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xD2<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xD3<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0xD4<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xD5<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0xD6<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0xD7<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xD8<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xD9<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xE0<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xE1<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xE2<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xE3<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xE4<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xE5<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xE0<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xE1<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xE2<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xE3<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xE4<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xE5<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xE6<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xE7<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xE8<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xE9<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xF0<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xF1<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xF2<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xF3<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xF4<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xF5<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xF0<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xF1<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xF2<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xF3<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xF4<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xF5<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xF6<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xF7<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xF8<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xF9<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x00<<8)   |(1<<ZFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x01<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x02<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x03<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x04<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x05<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x00<<8)   |(1<<ZFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x01<<8)                     |(1<<CFlag)\r
+         .hword  (0x02<<8)                     |(1<<CFlag)\r
+         .hword  (0x03<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x04<<8)                     |(1<<CFlag)\r
+         .hword  (0x05<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x06<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x07<<8)                     |(1<<CFlag)\r
+         .hword  (0x08<<8)                  |(1<<CFlag)\r
+         .hword  (0x09<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x10<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x11<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x12<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x13<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x14<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x15<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x10<<8)                     |(1<<CFlag)\r
+         .hword  (0x11<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x12<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x13<<8)                     |(1<<CFlag)\r
+         .hword  (0x14<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x15<<8)                     |(1<<CFlag)\r
+         .hword  (0x16<<8)                     |(1<<CFlag)\r
+         .hword  (0x17<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x18<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x19<<8)                  |(1<<CFlag)\r
+         .hword  (0x20<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x21<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x22<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x23<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x24<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x25<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x20<<8)                  |(1<<CFlag)\r
+         .hword  (0x21<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x22<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x23<<8)                  |(1<<CFlag)\r
+         .hword  (0x24<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x25<<8)                  |(1<<CFlag)\r
+         .hword  (0x26<<8)                  |(1<<CFlag)\r
+         .hword  (0x27<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x28<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x29<<8)               |(1<<CFlag)\r
+         .hword  (0x30<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x31<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x32<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x33<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x34<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x35<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x30<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x31<<8)                  |(1<<CFlag)\r
+         .hword  (0x32<<8)                  |(1<<CFlag)\r
+         .hword  (0x33<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x34<<8)                  |(1<<CFlag)\r
+         .hword  (0x35<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x36<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x37<<8)                  |(1<<CFlag)\r
+         .hword  (0x38<<8)               |(1<<CFlag)\r
+         .hword  (0x39<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x40<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x41<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x42<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x43<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x44<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x45<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x40<<8)                     |(1<<CFlag)\r
+         .hword  (0x41<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x42<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x43<<8)                     |(1<<CFlag)\r
+         .hword  (0x44<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x45<<8)                     |(1<<CFlag)\r
+         .hword  (0x46<<8)                     |(1<<CFlag)\r
+         .hword  (0x47<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x48<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x49<<8)                  |(1<<CFlag)\r
+         .hword  (0x50<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x51<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x52<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x53<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x54<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x55<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x50<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x51<<8)                     |(1<<CFlag)\r
+         .hword  (0x52<<8)                     |(1<<CFlag)\r
+         .hword  (0x53<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x54<<8)                     |(1<<CFlag)\r
+         .hword  (0x55<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x56<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x57<<8)                     |(1<<CFlag)\r
+         .hword  (0x58<<8)                  |(1<<CFlag)\r
+         .hword  (0x59<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x60<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x61<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x62<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x63<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x64<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x65<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x06<<8)               |(1<<VFlag)\r
+         .hword  (0x07<<8)                  \r
+         .hword  (0x08<<8)               \r
+         .hword  (0x09<<8)            |(1<<VFlag)\r
+         .hword  (0x0A<<8)            |(1<<VFlag)\r
+         .hword  (0x0B<<8)               \r
+         .hword  (0x0C<<8)            |(1<<VFlag)\r
+         .hword  (0x0D<<8)               \r
+         .hword  (0x0E<<8)               \r
+         .hword  (0x0F<<8)            |(1<<VFlag)\r
+         .hword  (0x10<<8)         |(1<<HFlag)      \r
+         .hword  (0x11<<8)         |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x12<<8)         |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x13<<8)         |(1<<HFlag)      \r
+         .hword  (0x14<<8)         |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x15<<8)         |(1<<HFlag)      \r
+         .hword  (0x16<<8)                  \r
+         .hword  (0x17<<8)               |(1<<VFlag)\r
+         .hword  (0x18<<8)            |(1<<VFlag)\r
+         .hword  (0x19<<8)               \r
+         .hword  (0x1A<<8)               \r
+         .hword  (0x1B<<8)            |(1<<VFlag)\r
+         .hword  (0x1C<<8)               \r
+         .hword  (0x1D<<8)            |(1<<VFlag)\r
+         .hword  (0x1E<<8)            |(1<<VFlag)\r
+         .hword  (0x1F<<8)               \r
+         .hword  (0x20<<8)      |(1<<HFlag)      \r
+         .hword  (0x21<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x22<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x23<<8)      |(1<<HFlag)      \r
+         .hword  (0x24<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x25<<8)      |(1<<HFlag)      \r
+         .hword  (0x26<<8)               \r
+         .hword  (0x27<<8)            |(1<<VFlag)\r
+         .hword  (0x28<<8)         |(1<<VFlag)\r
+         .hword  (0x29<<8)            \r
+         .hword  (0x2A<<8)            \r
+         .hword  (0x2B<<8)         |(1<<VFlag)\r
+         .hword  (0x2C<<8)            \r
+         .hword  (0x2D<<8)         |(1<<VFlag)\r
+         .hword  (0x2E<<8)         |(1<<VFlag)\r
+         .hword  (0x2F<<8)            \r
+         .hword  (0x30<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x31<<8)      |(1<<HFlag)      \r
+         .hword  (0x32<<8)      |(1<<HFlag)      \r
+         .hword  (0x33<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x34<<8)      |(1<<HFlag)      \r
+         .hword  (0x35<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x36<<8)            |(1<<VFlag)\r
+         .hword  (0x37<<8)               \r
+         .hword  (0x38<<8)            \r
+         .hword  (0x39<<8)         |(1<<VFlag)\r
+         .hword  (0x3A<<8)         |(1<<VFlag)\r
+         .hword  (0x3B<<8)            \r
+         .hword  (0x3C<<8)         |(1<<VFlag)\r
+         .hword  (0x3D<<8)            \r
+         .hword  (0x3E<<8)            \r
+         .hword  (0x3F<<8)         |(1<<VFlag)\r
+         .hword  (0x40<<8)         |(1<<HFlag)      \r
+         .hword  (0x41<<8)         |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x42<<8)         |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x43<<8)         |(1<<HFlag)      \r
+         .hword  (0x44<<8)         |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x45<<8)         |(1<<HFlag)      \r
+         .hword  (0x46<<8)                  \r
+         .hword  (0x47<<8)               |(1<<VFlag)\r
+         .hword  (0x48<<8)            |(1<<VFlag)\r
+         .hword  (0x49<<8)               \r
+         .hword  (0x4A<<8)               \r
+         .hword  (0x4B<<8)            |(1<<VFlag)\r
+         .hword  (0x4C<<8)               \r
+         .hword  (0x4D<<8)            |(1<<VFlag)\r
+         .hword  (0x4E<<8)            |(1<<VFlag)\r
+         .hword  (0x4F<<8)               \r
+         .hword  (0x50<<8)         |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x51<<8)         |(1<<HFlag)      \r
+         .hword  (0x52<<8)         |(1<<HFlag)      \r
+         .hword  (0x53<<8)         |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x54<<8)         |(1<<HFlag)      \r
+         .hword  (0x55<<8)         |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x56<<8)               |(1<<VFlag)\r
+         .hword  (0x57<<8)                  \r
+         .hword  (0x58<<8)               \r
+         .hword  (0x59<<8)            |(1<<VFlag)\r
+         .hword  (0x5A<<8)            |(1<<VFlag)\r
+         .hword  (0x5B<<8)               \r
+         .hword  (0x5C<<8)            |(1<<VFlag)\r
+         .hword  (0x5D<<8)               \r
+         .hword  (0x5E<<8)               \r
+         .hword  (0x5F<<8)            |(1<<VFlag)\r
+         .hword  (0x60<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x61<<8)      |(1<<HFlag)      \r
+         .hword  (0x62<<8)      |(1<<HFlag)      \r
+         .hword  (0x63<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x64<<8)      |(1<<HFlag)      \r
+         .hword  (0x65<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x66<<8)            |(1<<VFlag)\r
+         .hword  (0x67<<8)               \r
+         .hword  (0x68<<8)            \r
+         .hword  (0x69<<8)         |(1<<VFlag)\r
+         .hword  (0x6A<<8)         |(1<<VFlag)\r
+         .hword  (0x6B<<8)            \r
+         .hword  (0x6C<<8)         |(1<<VFlag)\r
+         .hword  (0x6D<<8)            \r
+         .hword  (0x6E<<8)            \r
+         .hword  (0x6F<<8)         |(1<<VFlag)\r
+         .hword  (0x70<<8)      |(1<<HFlag)      \r
+         .hword  (0x71<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x72<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x73<<8)      |(1<<HFlag)      \r
+         .hword  (0x74<<8)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x75<<8)      |(1<<HFlag)      \r
+         .hword  (0x76<<8)               \r
+         .hword  (0x77<<8)            |(1<<VFlag)\r
+         .hword  (0x78<<8)         |(1<<VFlag)\r
+         .hword  (0x79<<8)            \r
+         .hword  (0x7A<<8)            \r
+         .hword  (0x7B<<8)         |(1<<VFlag)\r
+         .hword  (0x7C<<8)            \r
+         .hword  (0x7D<<8)         |(1<<VFlag)\r
+         .hword  (0x7E<<8)         |(1<<VFlag)\r
+         .hword  (0x7F<<8)            \r
+         .hword  (0x80<<8)|(1<<SFlag)      |(1<<HFlag)      \r
+         .hword  (0x81<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x82<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x83<<8)|(1<<SFlag)      |(1<<HFlag)      \r
+         .hword  (0x84<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x85<<8)|(1<<SFlag)      |(1<<HFlag)      \r
+         .hword  (0x86<<8)|(1<<SFlag)               \r
+         .hword  (0x87<<8)|(1<<SFlag)            |(1<<VFlag)\r
+         .hword  (0x88<<8)|(1<<SFlag)         |(1<<VFlag)\r
+         .hword  (0x89<<8)|(1<<SFlag)            \r
+         .hword  (0x8A<<8)|(1<<SFlag)            \r
+         .hword  (0x8B<<8)|(1<<SFlag)         |(1<<VFlag)\r
+         .hword  (0x8C<<8)|(1<<SFlag)            \r
+         .hword  (0x8D<<8)|(1<<SFlag)         |(1<<VFlag)\r
+         .hword  (0x8E<<8)|(1<<SFlag)         |(1<<VFlag)\r
+         .hword  (0x8F<<8)|(1<<SFlag)            \r
+         .hword  (0x90<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x91<<8)|(1<<SFlag)      |(1<<HFlag)      \r
+         .hword  (0x92<<8)|(1<<SFlag)      |(1<<HFlag)      \r
+         .hword  (0x93<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x94<<8)|(1<<SFlag)      |(1<<HFlag)      \r
+         .hword  (0x95<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)\r
+         .hword  (0x96<<8)|(1<<SFlag)            |(1<<VFlag)\r
+         .hword  (0x97<<8)|(1<<SFlag)               \r
+         .hword  (0x98<<8)|(1<<SFlag)            \r
+         .hword  (0x99<<8)|(1<<SFlag)         |(1<<VFlag)\r
+         .hword  (0x9A<<8)|(1<<SFlag)         |(1<<VFlag)\r
+         .hword  (0x9B<<8)|(1<<SFlag)            \r
+         .hword  (0x9C<<8)|(1<<SFlag)         |(1<<VFlag)\r
+         .hword  (0x9D<<8)|(1<<SFlag)            \r
+         .hword  (0x9E<<8)|(1<<SFlag)            \r
+         .hword  (0x9F<<8)|(1<<SFlag)         |(1<<VFlag)\r
+         .hword  (0x00<<8)   |(1<<ZFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x01<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x02<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x03<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x04<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x05<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x06<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x07<<8)                     |(1<<CFlag)\r
+         .hword  (0x08<<8)                  |(1<<CFlag)\r
+         .hword  (0x09<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x0A<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x0B<<8)                  |(1<<CFlag)\r
+         .hword  (0x0C<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x0D<<8)                  |(1<<CFlag)\r
+         .hword  (0x0E<<8)                  |(1<<CFlag)\r
+         .hword  (0x0F<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x10<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x11<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x12<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x13<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x14<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x15<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x16<<8)                     |(1<<CFlag)\r
+         .hword  (0x17<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x18<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x19<<8)                  |(1<<CFlag)\r
+         .hword  (0x1A<<8)                  |(1<<CFlag)\r
+         .hword  (0x1B<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x1C<<8)                  |(1<<CFlag)\r
+         .hword  (0x1D<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x1E<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x1F<<8)                  |(1<<CFlag)\r
+         .hword  (0x20<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x21<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x22<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x23<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x24<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x25<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x26<<8)                  |(1<<CFlag)\r
+         .hword  (0x27<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x28<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x29<<8)               |(1<<CFlag)\r
+         .hword  (0x2A<<8)               |(1<<CFlag)\r
+         .hword  (0x2B<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x2C<<8)               |(1<<CFlag)\r
+         .hword  (0x2D<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x2E<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x2F<<8)               |(1<<CFlag)\r
+         .hword  (0x30<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x31<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x32<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x33<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x34<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x35<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x36<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x37<<8)                  |(1<<CFlag)\r
+         .hword  (0x38<<8)               |(1<<CFlag)\r
+         .hword  (0x39<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x3A<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x3B<<8)               |(1<<CFlag)\r
+         .hword  (0x3C<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x3D<<8)               |(1<<CFlag)\r
+         .hword  (0x3E<<8)               |(1<<CFlag)\r
+         .hword  (0x3F<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x40<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x41<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x42<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x43<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x44<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x45<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x46<<8)                     |(1<<CFlag)\r
+         .hword  (0x47<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x48<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x49<<8)                  |(1<<CFlag)\r
+         .hword  (0x4A<<8)                  |(1<<CFlag)\r
+         .hword  (0x4B<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x4C<<8)                  |(1<<CFlag)\r
+         .hword  (0x4D<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x4E<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x4F<<8)                  |(1<<CFlag)\r
+         .hword  (0x50<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x51<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x52<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x53<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x54<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x55<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x56<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x57<<8)                     |(1<<CFlag)\r
+         .hword  (0x58<<8)                  |(1<<CFlag)\r
+         .hword  (0x59<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x5A<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x5B<<8)                  |(1<<CFlag)\r
+         .hword  (0x5C<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x5D<<8)                  |(1<<CFlag)\r
+         .hword  (0x5E<<8)                  |(1<<CFlag)\r
+         .hword  (0x5F<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x60<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x61<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x62<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x63<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x64<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x65<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x66<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x67<<8)                  |(1<<CFlag)\r
+         .hword  (0x68<<8)               |(1<<CFlag)\r
+         .hword  (0x69<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x6A<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x6B<<8)               |(1<<CFlag)\r
+         .hword  (0x6C<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x6D<<8)               |(1<<CFlag)\r
+         .hword  (0x6E<<8)               |(1<<CFlag)\r
+         .hword  (0x6F<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x70<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x71<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x72<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x73<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x74<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x75<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x76<<8)                  |(1<<CFlag)\r
+         .hword  (0x77<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x78<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x79<<8)               |(1<<CFlag)\r
+         .hword  (0x7A<<8)               |(1<<CFlag)\r
+         .hword  (0x7B<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x7C<<8)               |(1<<CFlag)\r
+         .hword  (0x7D<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x7E<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x7F<<8)               |(1<<CFlag)\r
+         .hword  (0x80<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x81<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x82<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x83<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x84<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x85<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x86<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0x87<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x88<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x89<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0x8A<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0x8B<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x8C<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0x8D<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x8E<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x8F<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0x90<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x91<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x92<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x93<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x94<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x95<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x96<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x97<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0x98<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0x99<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x9A<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x9B<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0x9C<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x9D<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0x9E<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0x9F<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xA0<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xA1<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xA2<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xA3<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xA4<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xA5<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xA6<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xA7<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xA8<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xA9<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xAA<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xAB<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xAC<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xAD<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xAE<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xAF<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xB0<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xB1<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xB2<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xB3<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xB4<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xB5<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xB6<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xB7<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xB8<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xB9<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xBA<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xBB<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xBC<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xBD<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xBE<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xBF<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xC0<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xC1<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xC2<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xC3<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xC4<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xC5<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xC6<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xC7<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0xC8<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xC9<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xCA<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xCB<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xCC<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xCD<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xCE<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xCF<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xD0<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xD1<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xD2<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xD3<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xD4<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xD5<<8)|(1<<SFlag)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xD6<<8)|(1<<SFlag)                  |(1<<CFlag)\r
+         .hword  (0xD7<<8)|(1<<SFlag)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xD8<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xD9<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xDA<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xDB<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xDC<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xDD<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xDE<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xDF<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xE0<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xE1<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xE2<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xE3<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xE4<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xE5<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xE6<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xE7<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xE8<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xE9<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xEA<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xEB<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xEC<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xED<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xEE<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xEF<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xF0<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xF1<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xF2<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xF3<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xF4<<8)|(1<<SFlag)   |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0xF5<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xF6<<8)|(1<<SFlag)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xF7<<8)|(1<<SFlag)               |(1<<CFlag)\r
+         .hword  (0xF8<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xF9<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xFA<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xFB<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xFC<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0xFD<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xFE<<8)|(1<<SFlag)            |(1<<CFlag)\r
+         .hword  (0xFF<<8)|(1<<SFlag)      |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x00<<8)   |(1<<ZFlag)   |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x01<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x02<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x03<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x04<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x05<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x06<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x07<<8)                     |(1<<CFlag)\r
+         .hword  (0x08<<8)                  |(1<<CFlag)\r
+         .hword  (0x09<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x0A<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x0B<<8)                  |(1<<CFlag)\r
+         .hword  (0x0C<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x0D<<8)                  |(1<<CFlag)\r
+         .hword  (0x0E<<8)                  |(1<<CFlag)\r
+         .hword  (0x0F<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x10<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x11<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x12<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x13<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x14<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x15<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x16<<8)                     |(1<<CFlag)\r
+         .hword  (0x17<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x18<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x19<<8)                  |(1<<CFlag)\r
+         .hword  (0x1A<<8)                  |(1<<CFlag)\r
+         .hword  (0x1B<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x1C<<8)                  |(1<<CFlag)\r
+         .hword  (0x1D<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x1E<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x1F<<8)                  |(1<<CFlag)\r
+         .hword  (0x20<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x21<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x22<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x23<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x24<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x25<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x26<<8)                  |(1<<CFlag)\r
+         .hword  (0x27<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x28<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x29<<8)               |(1<<CFlag)\r
+         .hword  (0x2A<<8)               |(1<<CFlag)\r
+         .hword  (0x2B<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x2C<<8)               |(1<<CFlag)\r
+         .hword  (0x2D<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x2E<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x2F<<8)               |(1<<CFlag)\r
+         .hword  (0x30<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x31<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x32<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x33<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x34<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x35<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x36<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x37<<8)                  |(1<<CFlag)\r
+         .hword  (0x38<<8)               |(1<<CFlag)\r
+         .hword  (0x39<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x3A<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x3B<<8)               |(1<<CFlag)\r
+         .hword  (0x3C<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x3D<<8)               |(1<<CFlag)\r
+         .hword  (0x3E<<8)               |(1<<CFlag)\r
+         .hword  (0x3F<<8)         |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x40<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x41<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x42<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x43<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x44<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x45<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x46<<8)                     |(1<<CFlag)\r
+         .hword  (0x47<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x48<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x49<<8)                  |(1<<CFlag)\r
+         .hword  (0x4A<<8)                  |(1<<CFlag)\r
+         .hword  (0x4B<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x4C<<8)                  |(1<<CFlag)\r
+         .hword  (0x4D<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x4E<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x4F<<8)                  |(1<<CFlag)\r
+         .hword  (0x50<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x51<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x52<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x53<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x54<<8)         |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x55<<8)         |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x56<<8)               |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x57<<8)                     |(1<<CFlag)\r
+         .hword  (0x58<<8)                  |(1<<CFlag)\r
+         .hword  (0x59<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x5A<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x5B<<8)                  |(1<<CFlag)\r
+         .hword  (0x5C<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x5D<<8)                  |(1<<CFlag)\r
+         .hword  (0x5E<<8)                  |(1<<CFlag)\r
+         .hword  (0x5F<<8)            |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x60<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x61<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x62<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x63<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x64<<8)      |(1<<HFlag)         |(1<<CFlag)\r
+         .hword  (0x65<<8)      |(1<<HFlag)   |(1<<VFlag)   |(1<<CFlag)\r
+         .hword  (0x00<<8)   |(1<<ZFlag)         |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x01<<8)                  |(1<<NFlag)   \r
+         .hword  (0x02<<8)                  |(1<<NFlag)   \r
+         .hword  (0x03<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x04<<8)                  |(1<<NFlag)   \r
+         .hword  (0x05<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x06<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x07<<8)                  |(1<<NFlag)   \r
+         .hword  (0x08<<8)               |(1<<NFlag)   \r
+         .hword  (0x09<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x04<<8)                  |(1<<NFlag)   \r
+         .hword  (0x05<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x06<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x07<<8)                  |(1<<NFlag)   \r
+         .hword  (0x08<<8)               |(1<<NFlag)   \r
+         .hword  (0x09<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x10<<8)                  |(1<<NFlag)   \r
+         .hword  (0x11<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x12<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x13<<8)                  |(1<<NFlag)   \r
+         .hword  (0x14<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x15<<8)                  |(1<<NFlag)   \r
+         .hword  (0x16<<8)                  |(1<<NFlag)   \r
+         .hword  (0x17<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x18<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x19<<8)               |(1<<NFlag)   \r
+         .hword  (0x14<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x15<<8)                  |(1<<NFlag)   \r
+         .hword  (0x16<<8)                  |(1<<NFlag)   \r
+         .hword  (0x17<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x18<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x19<<8)               |(1<<NFlag)   \r
+         .hword  (0x20<<8)               |(1<<NFlag)   \r
+         .hword  (0x21<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x22<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x23<<8)               |(1<<NFlag)   \r
+         .hword  (0x24<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x25<<8)               |(1<<NFlag)   \r
+         .hword  (0x26<<8)               |(1<<NFlag)   \r
+         .hword  (0x27<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x28<<8)         |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x29<<8)            |(1<<NFlag)   \r
+         .hword  (0x24<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x25<<8)               |(1<<NFlag)   \r
+         .hword  (0x26<<8)               |(1<<NFlag)   \r
+         .hword  (0x27<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x28<<8)         |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x29<<8)            |(1<<NFlag)   \r
+         .hword  (0x30<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x31<<8)               |(1<<NFlag)   \r
+         .hword  (0x32<<8)               |(1<<NFlag)   \r
+         .hword  (0x33<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x34<<8)               |(1<<NFlag)   \r
+         .hword  (0x35<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x36<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x37<<8)               |(1<<NFlag)   \r
+         .hword  (0x38<<8)            |(1<<NFlag)   \r
+         .hword  (0x39<<8)         |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x34<<8)               |(1<<NFlag)   \r
+         .hword  (0x35<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x36<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x37<<8)               |(1<<NFlag)   \r
+         .hword  (0x38<<8)            |(1<<NFlag)   \r
+         .hword  (0x39<<8)         |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x40<<8)                  |(1<<NFlag)   \r
+         .hword  (0x41<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x42<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x43<<8)                  |(1<<NFlag)   \r
+         .hword  (0x44<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x45<<8)                  |(1<<NFlag)   \r
+         .hword  (0x46<<8)                  |(1<<NFlag)   \r
+         .hword  (0x47<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x48<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x49<<8)               |(1<<NFlag)   \r
+         .hword  (0x44<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x45<<8)                  |(1<<NFlag)   \r
+         .hword  (0x46<<8)                  |(1<<NFlag)   \r
+         .hword  (0x47<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x48<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x49<<8)               |(1<<NFlag)   \r
+         .hword  (0x50<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x51<<8)                  |(1<<NFlag)   \r
+         .hword  (0x52<<8)                  |(1<<NFlag)   \r
+         .hword  (0x53<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x54<<8)                  |(1<<NFlag)   \r
+         .hword  (0x55<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x56<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x57<<8)                  |(1<<NFlag)   \r
+         .hword  (0x58<<8)               |(1<<NFlag)   \r
+         .hword  (0x59<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x54<<8)                  |(1<<NFlag)   \r
+         .hword  (0x55<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x56<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x57<<8)                  |(1<<NFlag)   \r
+         .hword  (0x58<<8)               |(1<<NFlag)   \r
+         .hword  (0x59<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x60<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x61<<8)               |(1<<NFlag)   \r
+         .hword  (0x62<<8)               |(1<<NFlag)   \r
+         .hword  (0x63<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x64<<8)               |(1<<NFlag)   \r
+         .hword  (0x65<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x66<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x67<<8)               |(1<<NFlag)   \r
+         .hword  (0x68<<8)            |(1<<NFlag)   \r
+         .hword  (0x69<<8)         |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x64<<8)               |(1<<NFlag)   \r
+         .hword  (0x65<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x66<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x67<<8)               |(1<<NFlag)   \r
+         .hword  (0x68<<8)            |(1<<NFlag)   \r
+         .hword  (0x69<<8)         |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x70<<8)               |(1<<NFlag)   \r
+         .hword  (0x71<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x72<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x73<<8)               |(1<<NFlag)   \r
+         .hword  (0x74<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x75<<8)               |(1<<NFlag)   \r
+         .hword  (0x76<<8)               |(1<<NFlag)   \r
+         .hword  (0x77<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x78<<8)         |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x79<<8)            |(1<<NFlag)   \r
+         .hword  (0x74<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x75<<8)               |(1<<NFlag)   \r
+         .hword  (0x76<<8)               |(1<<NFlag)   \r
+         .hword  (0x77<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x78<<8)         |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x79<<8)            |(1<<NFlag)   \r
+         .hword  (0x80<<8)|(1<<SFlag)               |(1<<NFlag)   \r
+         .hword  (0x81<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x82<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x83<<8)|(1<<SFlag)               |(1<<NFlag)   \r
+         .hword  (0x84<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x85<<8)|(1<<SFlag)               |(1<<NFlag)   \r
+         .hword  (0x86<<8)|(1<<SFlag)               |(1<<NFlag)   \r
+         .hword  (0x87<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x88<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x89<<8)|(1<<SFlag)            |(1<<NFlag)   \r
+         .hword  (0x84<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x85<<8)|(1<<SFlag)               |(1<<NFlag)   \r
+         .hword  (0x86<<8)|(1<<SFlag)               |(1<<NFlag)   \r
+         .hword  (0x87<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x88<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x89<<8)|(1<<SFlag)            |(1<<NFlag)   \r
+         .hword  (0x90<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x91<<8)|(1<<SFlag)               |(1<<NFlag)   \r
+         .hword  (0x92<<8)|(1<<SFlag)               |(1<<NFlag)   \r
+         .hword  (0x93<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x94<<8)|(1<<SFlag)               |(1<<NFlag)   \r
+         .hword  (0x95<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x96<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x97<<8)|(1<<SFlag)               |(1<<NFlag)   \r
+         .hword  (0x98<<8)|(1<<SFlag)            |(1<<NFlag)   \r
+         .hword  (0x99<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x34<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x35<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x36<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x37<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x38<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x39<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x40<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x41<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x42<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x43<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x44<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x45<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x46<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x47<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x48<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x49<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x44<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x45<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x46<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x47<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x48<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x49<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x50<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x51<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x52<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x53<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x54<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x55<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x56<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x57<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x58<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x59<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x54<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x55<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x56<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x57<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x58<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x59<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x60<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x61<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x62<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x63<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x64<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x65<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x66<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x67<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x68<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x69<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x64<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x65<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x66<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x67<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x68<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x69<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x70<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x71<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x72<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x73<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x74<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x75<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x76<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x77<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x78<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x79<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x74<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x75<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x76<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x77<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x78<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x79<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x80<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x81<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x82<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x83<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x84<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x85<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x86<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x87<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x88<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x89<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x84<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x85<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x86<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x87<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x88<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x89<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x90<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x91<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x92<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x93<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x94<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x95<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x96<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x97<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x98<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x99<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x94<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x95<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x96<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x97<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x98<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x99<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA0<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA1<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA2<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA3<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA4<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA5<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA6<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA7<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA8<<8)|(1<<SFlag)         |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA9<<8)|(1<<SFlag)      |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA4<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA5<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA6<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA7<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA8<<8)|(1<<SFlag)         |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA9<<8)|(1<<SFlag)      |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB0<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB1<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB2<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB3<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB4<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB5<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB6<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB7<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB8<<8)|(1<<SFlag)      |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB9<<8)|(1<<SFlag)         |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB4<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB5<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB6<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB7<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB8<<8)|(1<<SFlag)      |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB9<<8)|(1<<SFlag)         |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC0<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC1<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC2<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC3<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC4<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC5<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC6<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC7<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC8<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC9<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC4<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC5<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC6<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC7<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC8<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC9<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD0<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD1<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD2<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD3<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD4<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD5<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD6<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD7<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD8<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD9<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD4<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD5<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD6<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD7<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD8<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD9<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE0<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE1<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE2<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE3<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE4<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE5<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE6<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE7<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE8<<8)|(1<<SFlag)      |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE9<<8)|(1<<SFlag)         |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE4<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE5<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE6<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE7<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE8<<8)|(1<<SFlag)      |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE9<<8)|(1<<SFlag)         |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF0<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF1<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF2<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF3<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF4<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF5<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF6<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF7<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF8<<8)|(1<<SFlag)         |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF9<<8)|(1<<SFlag)      |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF4<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF5<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF6<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF7<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF8<<8)|(1<<SFlag)         |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF9<<8)|(1<<SFlag)      |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x00<<8)   |(1<<ZFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x01<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x02<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x03<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x04<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x05<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x06<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x07<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x08<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x09<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x04<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x05<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x06<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x07<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x08<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x09<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x10<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x11<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x12<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x13<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x14<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x15<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x16<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x17<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x18<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x19<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x14<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x15<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x16<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x17<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x18<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x19<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x20<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x21<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x22<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x23<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x24<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x25<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x26<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x27<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x28<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x29<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x24<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x25<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x26<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x27<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x28<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x29<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x30<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x31<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x32<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x33<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x34<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x35<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x36<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x37<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x38<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x39<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x34<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x35<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x36<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x37<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x38<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x39<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x40<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x41<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x42<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x43<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x44<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x45<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x46<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x47<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x48<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x49<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x44<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x45<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x46<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x47<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x48<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x49<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x50<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x51<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x52<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x53<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x54<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x55<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x56<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x57<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x58<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x59<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x54<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x55<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x56<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x57<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x58<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x59<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x60<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x61<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x62<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x63<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x64<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x65<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x66<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x67<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x68<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x69<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x64<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x65<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x66<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x67<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x68<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x69<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x70<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x71<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x72<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x73<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x74<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x75<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x76<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x77<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x78<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x79<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x74<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x75<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x76<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x77<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x78<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x79<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x80<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x81<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x82<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x83<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x84<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x85<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x86<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x87<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x88<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x89<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x84<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x85<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x86<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x87<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x88<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x89<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x90<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x91<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x92<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x93<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x94<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x95<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x96<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x97<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x98<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x99<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x94<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x95<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x96<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x97<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x98<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x99<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xFA<<8)|(1<<SFlag)   |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0xFB<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0xFC<<8)|(1<<SFlag)   |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0xFD<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0xFE<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0xFF<<8)|(1<<SFlag)   |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x00<<8)   |(1<<ZFlag)         |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x01<<8)                  |(1<<NFlag)   \r
+         .hword  (0x02<<8)                  |(1<<NFlag)   \r
+         .hword  (0x03<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x04<<8)                  |(1<<NFlag)   \r
+         .hword  (0x05<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x06<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x07<<8)                  |(1<<NFlag)   \r
+         .hword  (0x08<<8)               |(1<<NFlag)   \r
+         .hword  (0x09<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x0A<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x0B<<8)         |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x0C<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x0D<<8)         |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x0E<<8)         |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x0F<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x10<<8)                  |(1<<NFlag)   \r
+         .hword  (0x11<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x12<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x13<<8)                  |(1<<NFlag)   \r
+         .hword  (0x14<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x15<<8)                  |(1<<NFlag)   \r
+         .hword  (0x16<<8)                  |(1<<NFlag)   \r
+         .hword  (0x17<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x18<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x19<<8)               |(1<<NFlag)   \r
+         .hword  (0x1A<<8)         |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x1B<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x1C<<8)         |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x1D<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x1E<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x1F<<8)         |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x20<<8)               |(1<<NFlag)   \r
+         .hword  (0x21<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x22<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x23<<8)               |(1<<NFlag)   \r
+         .hword  (0x24<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x25<<8)               |(1<<NFlag)   \r
+         .hword  (0x26<<8)               |(1<<NFlag)   \r
+         .hword  (0x27<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x28<<8)         |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x29<<8)            |(1<<NFlag)   \r
+         .hword  (0x2A<<8)      |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x2B<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x2C<<8)      |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x2D<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x2E<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x2F<<8)      |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x30<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x31<<8)               |(1<<NFlag)   \r
+         .hword  (0x32<<8)               |(1<<NFlag)   \r
+         .hword  (0x33<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x34<<8)               |(1<<NFlag)   \r
+         .hword  (0x35<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x36<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x37<<8)               |(1<<NFlag)   \r
+         .hword  (0x38<<8)            |(1<<NFlag)   \r
+         .hword  (0x39<<8)         |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x3A<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x3B<<8)      |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x3C<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x3D<<8)      |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x3E<<8)      |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x3F<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x40<<8)                  |(1<<NFlag)   \r
+         .hword  (0x41<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x42<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x43<<8)                  |(1<<NFlag)   \r
+         .hword  (0x44<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x45<<8)                  |(1<<NFlag)   \r
+         .hword  (0x46<<8)                  |(1<<NFlag)   \r
+         .hword  (0x47<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x48<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x49<<8)               |(1<<NFlag)   \r
+         .hword  (0x4A<<8)         |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x4B<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x4C<<8)         |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x4D<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x4E<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x4F<<8)         |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x50<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x51<<8)                  |(1<<NFlag)   \r
+         .hword  (0x52<<8)                  |(1<<NFlag)   \r
+         .hword  (0x53<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x54<<8)                  |(1<<NFlag)   \r
+         .hword  (0x55<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x56<<8)               |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x57<<8)                  |(1<<NFlag)   \r
+         .hword  (0x58<<8)               |(1<<NFlag)   \r
+         .hword  (0x59<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x5A<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x5B<<8)         |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x5C<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x5D<<8)         |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x5E<<8)         |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x5F<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x60<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x61<<8)               |(1<<NFlag)   \r
+         .hword  (0x62<<8)               |(1<<NFlag)   \r
+         .hword  (0x63<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x64<<8)               |(1<<NFlag)   \r
+         .hword  (0x65<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x66<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x67<<8)               |(1<<NFlag)   \r
+         .hword  (0x68<<8)            |(1<<NFlag)   \r
+         .hword  (0x69<<8)         |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x6A<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x6B<<8)      |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x6C<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x6D<<8)      |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x6E<<8)      |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x6F<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x70<<8)               |(1<<NFlag)   \r
+         .hword  (0x71<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x72<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x73<<8)               |(1<<NFlag)   \r
+         .hword  (0x74<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x75<<8)               |(1<<NFlag)   \r
+         .hword  (0x76<<8)               |(1<<NFlag)   \r
+         .hword  (0x77<<8)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x78<<8)         |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x79<<8)            |(1<<NFlag)   \r
+         .hword  (0x7A<<8)      |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x7B<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x7C<<8)      |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x7D<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x7E<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x7F<<8)      |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x80<<8)|(1<<SFlag)               |(1<<NFlag)   \r
+         .hword  (0x81<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x82<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x83<<8)|(1<<SFlag)               |(1<<NFlag)   \r
+         .hword  (0x84<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x85<<8)|(1<<SFlag)               |(1<<NFlag)   \r
+         .hword  (0x86<<8)|(1<<SFlag)               |(1<<NFlag)   \r
+         .hword  (0x87<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x88<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x89<<8)|(1<<SFlag)            |(1<<NFlag)   \r
+         .hword  (0x8A<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x8B<<8)|(1<<SFlag)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x8C<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x8D<<8)|(1<<SFlag)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x8E<<8)|(1<<SFlag)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x8F<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<NFlag)   \r
+         .hword  (0x90<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x91<<8)|(1<<SFlag)               |(1<<NFlag)   \r
+         .hword  (0x92<<8)|(1<<SFlag)               |(1<<NFlag)   \r
+         .hword  (0x93<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)   \r
+         .hword  (0x34<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x35<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x36<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x37<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x38<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x39<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x3A<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x3B<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x3C<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x3D<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x3E<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x3F<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x40<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x41<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x42<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x43<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x44<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x45<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x46<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x47<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x48<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x49<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x4A<<8)         |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x4B<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x4C<<8)         |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x4D<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x4E<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x4F<<8)         |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x50<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x51<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x52<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x53<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x54<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x55<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x56<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x57<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x58<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x59<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x5A<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x5B<<8)         |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x5C<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x5D<<8)         |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x5E<<8)         |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x5F<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x60<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x61<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x62<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x63<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x64<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x65<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x66<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x67<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x68<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x69<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x6A<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x6B<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x6C<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x6D<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x6E<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x6F<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x70<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x71<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x72<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x73<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x74<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x75<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x76<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x77<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x78<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x79<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x7A<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x7B<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x7C<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x7D<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x7E<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x7F<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x80<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x81<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x82<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x83<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x84<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x85<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x86<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x87<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x88<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x89<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x8A<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x8B<<8)|(1<<SFlag)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x8C<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x8D<<8)|(1<<SFlag)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x8E<<8)|(1<<SFlag)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x8F<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x90<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x91<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x92<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x93<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x94<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x95<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x96<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x97<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x98<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x99<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x9A<<8)|(1<<SFlag)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x9B<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x9C<<8)|(1<<SFlag)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x9D<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x9E<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x9F<<8)|(1<<SFlag)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA0<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA1<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA2<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA3<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA4<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA5<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA6<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA7<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA8<<8)|(1<<SFlag)         |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xA9<<8)|(1<<SFlag)      |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xAA<<8)|(1<<SFlag)   |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xAB<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xAC<<8)|(1<<SFlag)   |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xAD<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xAE<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xAF<<8)|(1<<SFlag)   |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB0<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB1<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB2<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB3<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB4<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB5<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB6<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB7<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB8<<8)|(1<<SFlag)      |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xB9<<8)|(1<<SFlag)         |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xBA<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xBB<<8)|(1<<SFlag)   |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xBC<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xBD<<8)|(1<<SFlag)   |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xBE<<8)|(1<<SFlag)   |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xBF<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC0<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC1<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC2<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC3<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC4<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC5<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC6<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC7<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC8<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xC9<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xCA<<8)|(1<<SFlag)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xCB<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xCC<<8)|(1<<SFlag)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xCD<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xCE<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xCF<<8)|(1<<SFlag)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD0<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD1<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD2<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD3<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD4<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD5<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD6<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD7<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD8<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xD9<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xDA<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xDB<<8)|(1<<SFlag)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xDC<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xDD<<8)|(1<<SFlag)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xDE<<8)|(1<<SFlag)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xDF<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE0<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE1<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE2<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE3<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE4<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE5<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE6<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE7<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE8<<8)|(1<<SFlag)      |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xE9<<8)|(1<<SFlag)         |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xEA<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xEB<<8)|(1<<SFlag)   |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xEC<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xED<<8)|(1<<SFlag)   |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xEE<<8)|(1<<SFlag)   |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xEF<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF0<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF1<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF2<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF3<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF4<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF5<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF6<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF7<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF8<<8)|(1<<SFlag)         |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xF9<<8)|(1<<SFlag)      |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xFA<<8)|(1<<SFlag)   |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xFB<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xFC<<8)|(1<<SFlag)   |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xFD<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xFE<<8)|(1<<SFlag)   |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0xFF<<8)|(1<<SFlag)   |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x00<<8)   |(1<<ZFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x01<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x02<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x03<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x04<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x05<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x06<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x07<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x08<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x09<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x0A<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x0B<<8)         |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x0C<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x0D<<8)         |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x0E<<8)         |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x0F<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x10<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x11<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x12<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x13<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x14<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x15<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x16<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x17<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x18<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x19<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x1A<<8)         |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x1B<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x1C<<8)         |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x1D<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x1E<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x1F<<8)         |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x20<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x21<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x22<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x23<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x24<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x25<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x26<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x27<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x28<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x29<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x2A<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x2B<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x2C<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x2D<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x2E<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x2F<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x30<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x31<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x32<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x33<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x34<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x35<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x36<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x37<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x38<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x39<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x3A<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x3B<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x3C<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x3D<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x3E<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x3F<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x40<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x41<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x42<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x43<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x44<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x45<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x46<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x47<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x48<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x49<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x4A<<8)         |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x4B<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x4C<<8)         |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x4D<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x4E<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x4F<<8)         |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x50<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x51<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x52<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x53<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x54<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x55<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x56<<8)               |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x57<<8)                  |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x58<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x59<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x5A<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x5B<<8)         |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x5C<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x5D<<8)         |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x5E<<8)         |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x5F<<8)         |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x60<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x61<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x62<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x63<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x64<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x65<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x66<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x67<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x68<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x69<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x6A<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x6B<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x6C<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x6D<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x6E<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x6F<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x70<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x71<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x72<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x73<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x74<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x75<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x76<<8)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x77<<8)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x78<<8)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x79<<8)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x7A<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x7B<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x7C<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x7D<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x7E<<8)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x7F<<8)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x80<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x81<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x82<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x83<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x84<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x85<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x86<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x87<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x88<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x89<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x8A<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x8B<<8)|(1<<SFlag)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x8C<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x8D<<8)|(1<<SFlag)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x8E<<8)|(1<<SFlag)      |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x8F<<8)|(1<<SFlag)      |(1<<HFlag)   |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x90<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x91<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x92<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x93<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x94<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x95<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x96<<8)|(1<<SFlag)            |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x97<<8)|(1<<SFlag)               |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x98<<8)|(1<<SFlag)            |(1<<NFlag)|(1<<CFlag)\r
+         .hword  (0x99<<8)|(1<<SFlag)         |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
+         \r
+.align 4\r
+\r
+AF_Z80:  .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 0\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 1\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 2\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 3\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 4\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 5\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 6\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 7\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 8\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 9\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 10\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 11\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 12\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 13\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 14\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 15\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 16\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 17\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 18\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 19\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 20\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 21\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 22\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 23\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 24\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 25\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 26\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 27\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 28\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 29\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 30\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 31\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 32\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 33\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 34\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 35\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 36\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 37\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 38\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 39\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 40\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 41\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 42\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 43\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 44\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 45\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 46\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 47\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 48\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 49\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 50\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 51\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 52\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 53\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 54\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 55\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 56\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 57\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 58\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 59\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 60\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 61\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 62\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 63\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 64\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 65\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 66\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 67\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 68\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 69\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 70\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 71\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 72\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 73\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 74\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 75\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 76\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 77\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 78\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 79\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 80\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 81\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 82\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 83\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 84\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 85\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 86\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 87\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 88\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 89\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 90\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 91\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 92\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 93\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 94\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 95\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 96\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 97\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 98\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 99\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 100\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 101\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 102\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 103\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 104\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 105\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 106\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 107\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 108\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 109\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 110\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 111\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 112\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 113\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 114\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 115\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 116\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 117\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 118\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 119\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 120\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 121\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 122\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 123\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 124\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 125\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 126\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 127\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 128\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 129\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 130\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 131\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 132\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 133\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 134\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 135\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 136\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 137\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 138\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 139\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 140\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 141\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 142\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 143\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 144\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 145\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 146\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 147\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 148\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 149\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 150\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 151\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 152\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 153\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 154\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 155\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 156\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 157\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 158\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 159\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 160\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 161\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 162\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 163\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 164\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 165\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 166\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 167\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 168\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 169\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 170\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 171\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 172\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 173\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 174\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 175\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 176\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 177\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 178\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 179\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 180\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 181\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 182\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 183\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 184\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 185\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 186\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 187\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 188\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 189\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 190\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 191\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 192\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 193\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 194\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 195\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 196\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 197\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 198\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 199\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 200\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 201\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 202\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 203\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 204\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 205\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 206\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 207\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 208\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 209\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 210\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 211\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 212\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 213\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 214\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 215\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 216\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 217\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 218\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 219\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 220\r
+         .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 221\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 222\r
+         .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 223\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 224\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 225\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 226\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 227\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 228\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 229\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 230\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 231\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 232\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 233\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 234\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 235\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 236\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 237\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 238\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 239\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 240\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 241\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 242\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 243\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 244\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 245\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 246\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 247\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 248\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 249\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 250\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 251\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 252\r
+         .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 253\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 254\r
+         .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 255\r
+\r
+.align 4\r
+\r
+AF_ARM:  .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 0\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 1\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 2\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 3\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 4\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 5\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 6\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 7\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 8\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 9\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 10\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 11\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 12\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 13\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 14\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 15\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 16\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 17\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 18\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 19\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 20\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 21\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 22\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 23\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 24\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 25\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 26\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 27\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 28\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 29\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 30\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 31\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 32\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 33\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 34\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 35\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 36\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 37\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 38\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 39\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 40\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 41\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 42\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 43\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 44\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 45\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 46\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 47\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 48\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 49\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 50\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 51\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 52\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 53\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 54\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 55\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 56\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 57\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 58\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 59\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 60\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 61\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 62\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag)  ;@ 63\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 64\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 65\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 66\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 67\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 68\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 69\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 70\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 71\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 72\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 73\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 74\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 75\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 76\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 77\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 78\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 79\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 80\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 81\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 82\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 83\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 84\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 85\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 86\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 87\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 88\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 89\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 90\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 91\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 92\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 93\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 94\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 95\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 96\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 97\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 98\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 99\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 100\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 101\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 102\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 103\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 104\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 105\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 106\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 107\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 108\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 109\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 110\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 111\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 112\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 113\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 114\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 115\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 116\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 117\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 118\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 119\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 120\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 121\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 122\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 123\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 124\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 125\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 126\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag)  ;@ 127\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 128\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 129\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 130\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 131\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 132\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 133\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 134\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 135\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 136\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 137\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 138\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 139\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 140\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 141\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 142\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 143\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 144\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 145\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 146\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 147\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 148\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 149\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 150\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 151\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 152\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 153\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 154\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 155\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 156\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 157\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 158\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 159\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 160\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 161\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 162\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 163\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 164\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 165\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 166\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 167\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 168\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 169\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 170\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 171\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 172\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 173\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 174\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 175\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 176\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 177\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 178\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 179\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 180\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 181\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 182\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 183\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 184\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 185\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 186\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 187\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 188\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 189\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 190\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag)  ;@ 191\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 192\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 193\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 194\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 195\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 196\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 197\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 198\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 199\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 200\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 201\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 202\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 203\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 204\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 205\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 206\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 207\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 208\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 209\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 210\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 211\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 212\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 213\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 214\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 215\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 216\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 217\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 218\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 219\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 220\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 221\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 222\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 223\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 224\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 225\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 226\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 227\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 228\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 229\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 230\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 231\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 232\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 233\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 234\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 235\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 236\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 237\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 238\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 239\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 240\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 241\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 242\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 243\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 244\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 245\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 246\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 247\r
+         .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 248\r
+         .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 249\r
+         .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 250\r
+         .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 251\r
+         .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 252\r
+         .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 253\r
+         .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 254\r
+         .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag)  ;@ 255\r
+\r
+.align 4\r
+\r
+PZSTable_data: .byte (1<<ZFlag)|(1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0\r
+       .byte  0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag)\r
+       .byte  0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0\r
+       .byte  0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0\r
+       .byte  (1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag)\r
+       .byte  0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0\r
+       .byte  (1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag)\r
+       .byte  (1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag)\r
+       .byte  0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0\r
+       .byte  (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
+       .byte  (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
+       .byte  (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
+       .byte  (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
+       .byte  (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
+       .byte  (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
+       .byte  (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
+       .byte  (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
+       .byte  (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
+       .byte  (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
+       .byte  (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
+       .byte  (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
+       .byte  (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
+       .byte  (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
+       .byte  (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
+       .byte  (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
+       .byte  (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
+       .byte  (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
+       .byte  (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
+       .byte  (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
+       .byte  (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
+       .byte  (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
+       .byte  (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
+       .byte  (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
+       .byte  (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
+       .byte  (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
+       .byte  (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
+       .byte  (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
+       .byte  (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
+       .byte  (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
+       .byte  (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
+       .byte  (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)       \r
+\r
+.align 4\r
+\r
+MAIN_opcodes:  \r
+       .word opcode_0_0,opcode_0_1,opcode_0_2,opcode_0_3,opcode_0_4,opcode_0_5,opcode_0_6,opcode_0_7\r
+       .word opcode_0_8,opcode_0_9,opcode_0_A,opcode_0_B,opcode_0_C,opcode_0_D,opcode_0_E,opcode_0_F\r
+       .word opcode_1_0,opcode_1_1,opcode_1_2,opcode_1_3,opcode_1_4,opcode_1_5,opcode_1_6,opcode_1_7\r
+       .word opcode_1_8,opcode_1_9,opcode_1_A,opcode_1_B,opcode_1_C,opcode_1_D,opcode_1_E,opcode_1_F\r
+       .word opcode_2_0,opcode_2_1,opcode_2_2,opcode_2_3,opcode_2_4,opcode_2_5,opcode_2_6,opcode_2_7\r
+       .word opcode_2_8,opcode_2_9,opcode_2_A,opcode_2_B,opcode_2_C,opcode_2_D,opcode_2_E,opcode_2_F\r
+       .word opcode_3_0,opcode_3_1,opcode_3_2,opcode_3_3,opcode_3_4,opcode_3_5,opcode_3_6,opcode_3_7\r
+       .word opcode_3_8,opcode_3_9,opcode_3_A,opcode_3_B,opcode_3_C,opcode_3_D,opcode_3_E,opcode_3_F\r
+       .word opcode_4_0,opcode_4_1,opcode_4_2,opcode_4_3,opcode_4_4,opcode_4_5,opcode_4_6,opcode_4_7\r
+       .word opcode_4_8,opcode_4_9,opcode_4_A,opcode_4_B,opcode_4_C,opcode_4_D,opcode_4_E,opcode_4_F\r
+       .word opcode_5_0,opcode_5_1,opcode_5_2,opcode_5_3,opcode_5_4,opcode_5_5,opcode_5_6,opcode_5_7\r
+       .word opcode_5_8,opcode_5_9,opcode_5_A,opcode_5_B,opcode_5_C,opcode_5_D,opcode_5_E,opcode_5_F\r
+       .word opcode_6_0,opcode_6_1,opcode_6_2,opcode_6_3,opcode_6_4,opcode_6_5,opcode_6_6,opcode_6_7\r
+       .word opcode_6_8,opcode_6_9,opcode_6_A,opcode_6_B,opcode_6_C,opcode_6_D,opcode_6_E,opcode_6_F\r
+       .word opcode_7_0,opcode_7_1,opcode_7_2,opcode_7_3,opcode_7_4,opcode_7_5,opcode_7_6,opcode_7_7\r
+       .word opcode_7_8,opcode_7_9,opcode_7_A,opcode_7_B,opcode_7_C,opcode_7_D,opcode_7_E,opcode_7_F\r
+       .word opcode_8_0,opcode_8_1,opcode_8_2,opcode_8_3,opcode_8_4,opcode_8_5,opcode_8_6,opcode_8_7\r
+       .word opcode_8_8,opcode_8_9,opcode_8_A,opcode_8_B,opcode_8_C,opcode_8_D,opcode_8_E,opcode_8_F\r
+       .word opcode_9_0,opcode_9_1,opcode_9_2,opcode_9_3,opcode_9_4,opcode_9_5,opcode_9_6,opcode_9_7\r
+       .word opcode_9_8,opcode_9_9,opcode_9_A,opcode_9_B,opcode_9_C,opcode_9_D,opcode_9_E,opcode_9_F\r
+       .word opcode_A_0,opcode_A_1,opcode_A_2,opcode_A_3,opcode_A_4,opcode_A_5,opcode_A_6,opcode_A_7\r
+       .word opcode_A_8,opcode_A_9,opcode_A_A,opcode_A_B,opcode_A_C,opcode_A_D,opcode_A_E,opcode_A_F\r
+       .word opcode_B_0,opcode_B_1,opcode_B_2,opcode_B_3,opcode_B_4,opcode_B_5,opcode_B_6,opcode_B_7\r
+       .word opcode_B_8,opcode_B_9,opcode_B_A,opcode_B_B,opcode_B_C,opcode_B_D,opcode_B_E,opcode_B_F\r
+       .word opcode_C_0,opcode_C_1,opcode_C_2,opcode_C_3,opcode_C_4,opcode_C_5,opcode_C_6,opcode_C_7\r
+       .word opcode_C_8,opcode_C_9,opcode_C_A,opcode_C_B,opcode_C_C,opcode_C_D,opcode_C_E,opcode_C_F\r
+       .word opcode_D_0,opcode_D_1,opcode_D_2,opcode_D_3,opcode_D_4,opcode_D_5,opcode_D_6,opcode_D_7\r
+       .word opcode_D_8,opcode_D_9,opcode_D_A,opcode_D_B,opcode_D_C,opcode_D_D,opcode_D_E,opcode_D_F\r
+       .word opcode_E_0,opcode_E_1,opcode_E_2,opcode_E_3,opcode_E_4,opcode_E_5,opcode_E_6,opcode_E_7\r
+       .word opcode_E_8,opcode_E_9,opcode_E_A,opcode_E_B,opcode_E_C,opcode_E_D,opcode_E_E,opcode_E_F\r
+       .word opcode_F_0,opcode_F_1,opcode_F_2,opcode_F_3,opcode_F_4,opcode_F_5,opcode_F_6,opcode_F_7\r
+       .word opcode_F_8,opcode_F_9,opcode_F_A,opcode_F_B,opcode_F_C,opcode_F_D,opcode_F_E,opcode_F_F\r
+\r
+.align 4\r
+\r
+EI_DUMMY_opcodes:\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@0\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@0\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@1\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@1\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@2\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@2\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@3\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@3\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@4\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@4\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@5\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@5\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@6\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@6\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@7\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@7\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@8\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@8\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@9\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@9\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@A\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@A\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@B\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@B\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@C\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@C\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@D\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@D\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@E\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@E\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@F\r
+       .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@F\r
+\r
+.text\r
+.align 4\r
+\r
+;@NOP\r
+opcode_0_0:\r
+;@LD B,B\r
+opcode_4_0:\r
+;@LD C,C\r
+opcode_4_9:\r
+;@LD D,D\r
+opcode_5_2:\r
+;@LD E,E\r
+opcode_5_B:\r
+;@LD H,H\r
+opcode_6_4:\r
+;@LD L,L\r
+opcode_6_D:\r
+;@LD A,A\r
+opcode_7_F:\r
+       fetch 4\r
+;@LD BC,NN\r
+opcode_0_1:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+       orr r0,r0,r1, lsl #8\r
+       mov z80bc,r0, lsl #16\r
+       fetch 10\r
+;@LD (BC),A\r
+opcode_0_2:\r
+       mov r0,z80a, lsr #24\r
+       mov r1,z80bc, lsr #16\r
+       writemem8\r
+       fetch 7\r
+;@INC BC\r
+opcode_0_3:\r
+       add z80bc,z80bc,#1<<16\r
+       fetch 6\r
+;@INC B\r
+opcode_0_4:\r
+       opINC8H z80bc\r
+       fetch 4\r
+;@DEC B\r
+opcode_0_5:\r
+       opDEC8H z80bc\r
+       fetch 4\r
+;@LD B,N\r
+opcode_0_6:\r
+       ldrb r1,[z80pc],#1\r
+       and z80bc,z80bc,#0xFF<<16\r
+       orr z80bc,z80bc,r1, lsl #24\r
+       fetch 7\r
+;@RLCA\r
+opcode_0_7:\r
+       bic z80f,z80f,#(1<<NFlag)|(1<<HFlag)|(1<<CFlag)\r
+       movs z80a,z80a, lsl #1\r
+       orrcs z80a,z80a,#1<<24\r
+       orrcs z80f,z80f,#1<<CFlag\r
+       fetch 4\r
+;@EX AF,AF'\r
+opcode_0_8:\r
+       add r1,cpucontext,#z80a2\r
+       swp z80a,z80a,[r1]\r
+       add r1,cpucontext,#z80f2\r
+       swp z80f,z80f,[r1]\r
+       fetch 4\r
+;@ADD HL,BC\r
+opcode_0_9:\r
+       opADD16 z80hl z80bc\r
+       fetch 11\r
+;@LD A,(BC)\r
+opcode_0_A:\r
+       mov r0,z80bc, lsr #16\r
+       readmem8\r
+       mov z80a,r0, lsl #24\r
+       fetch 7\r
+;@DEC BC\r
+opcode_0_B:\r
+       sub z80bc,z80bc,#1<<16\r
+       fetch 6\r
+;@INC C\r
+opcode_0_C:\r
+       opINC8L z80bc\r
+       fetch 4\r
+;@DEC C\r
+opcode_0_D:\r
+       opDEC8L z80bc\r
+       fetch 4\r
+;@LD C,N\r
+opcode_0_E:\r
+       ldrb r1,[z80pc],#1\r
+       and z80bc,z80bc,#0xFF<<24\r
+       orr z80bc,z80bc,r1, lsl #16\r
+       fetch 7\r
+;@RRCA\r
+opcode_0_F:\r
+       bic z80f,z80f,#(1<<NFlag)|(1<<HFlag)|(1<<CFlag)\r
+       movs z80a,z80a, lsr #25\r
+       orrcs z80a,z80a,#1<<7\r
+       orrcs z80f,z80f,#1<<CFlag\r
+       mov z80a,z80a, lsl #24\r
+       fetch 4\r
+;@DJNZ $+2\r
+opcode_1_0:\r
+       sub z80bc,z80bc,#1<<24\r
+       tst z80bc,#0xFF<<24\r
+       ldrsb r1,[z80pc],#1\r
+       addne z80pc,z80pc,r1\r
+       subne z80_icount,z80_icount,#5\r
+       fetch 8\r
+\r
+;@LD DE,NN\r
+opcode_1_1:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+       orr r0,r0,r1, lsl #8\r
+       mov z80de,r0, lsl #16\r
+       fetch 10\r
+;@LD (DE),A\r
+opcode_1_2:\r
+       mov r0,z80a, lsr #24\r
+       writemem8DE\r
+       fetch 7\r
+;@INC DE\r
+opcode_1_3:\r
+       add z80de,z80de,#1<<16\r
+       fetch 6\r
+;@INC D\r
+opcode_1_4:\r
+       opINC8H z80de\r
+       fetch 4\r
+;@DEC D\r
+opcode_1_5:\r
+       opDEC8H z80de\r
+       fetch 4\r
+;@LD D,N\r
+opcode_1_6:\r
+       ldrb r1,[z80pc],#1\r
+       and z80de,z80de,#0xFF<<16\r
+       orr z80de,z80de,r1, lsl #24\r
+       fetch 7\r
+;@RLA\r
+opcode_1_7:\r
+       tst z80f,#1<<CFlag\r
+       orrne z80a,z80a,#1<<23\r
+       bic z80f,z80f,#(1<<NFlag)|(1<<HFlag)|(1<<CFlag)\r
+       movs z80a,z80a, lsl #1\r
+       orrcs z80f,z80f,#1<<CFlag\r
+       fetch 4\r
+;@JR $+2\r
+opcode_1_8:\r
+       ldrsb r1,[z80pc],#1\r
+       add z80pc,z80pc,r1\r
+       fetch 12\r
+;@ADD HL,DE\r
+opcode_1_9:\r
+       opADD16 z80hl z80de\r
+       fetch 11\r
+;@LD A,(DE)\r
+opcode_1_A:\r
+       mov r0,z80de, lsr #16\r
+       readmem8\r
+       mov z80a,r0, lsl #24\r
+       fetch 7\r
+;@DEC DE\r
+opcode_1_B:\r
+       sub z80de,z80de,#1<<16\r
+       fetch 6\r
+;@INC E\r
+opcode_1_C:\r
+       opINC8L z80de\r
+       fetch 4\r
+;@DEC E\r
+opcode_1_D:\r
+       opDEC8L z80de\r
+       fetch 4\r
+;@LD E,N\r
+opcode_1_E:\r
+       ldrb r0,[z80pc],#1\r
+       and z80de,z80de,#0xFF<<24\r
+       orr z80de,z80de,r0, lsl #16\r
+       fetch 7\r
+;@RRA\r
+opcode_1_F:\r
+       orr z80a,z80a,z80f,lsr#1                ;@get C\r
+       bic z80f,z80f,#(1<<NFlag)|(1<<HFlag)|(1<<CFlag)\r
+       movs z80a,z80a,ror#25\r
+       orrcs z80f,z80f,#1<<CFlag\r
+       mov z80a,z80a,lsl#24\r
+       fetch 4\r
+;@JR NZ,$+2\r
+opcode_2_0:\r
+       tst z80f,#1<<ZFlag\r
+       beq opcode_1_8\r
+       add z80pc,z80pc,#1\r
+       fetch 7\r
+;@LD HL,NN\r
+opcode_2_1:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+       orr r0,r0,r1, lsl #8\r
+       mov z80hl,r0, lsl #16\r
+       fetch 10\r
+;@LD (NN),HL\r
+opcode_ED_63:\r
+       eatcycles 4\r
+;@LD (NN),HL\r
+opcode_2_2:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+       orr r1,r0,r1, lsl #8\r
+       mov r0,z80hl, lsr #16\r
+       writemem16\r
+       fetch 16\r
+;@INC HL\r
+opcode_2_3:\r
+       add z80hl,z80hl,#1<<16\r
+       fetch 6\r
+;@INC H\r
+opcode_2_4:\r
+       opINC8H z80hl\r
+       fetch 4\r
+;@DEC H\r
+opcode_2_5:\r
+       opDEC8H z80hl\r
+       fetch 4\r
+;@LD H,N\r
+opcode_2_6:\r
+       ldrb r1,[z80pc],#1\r
+       and z80hl,z80hl,#0xFF<<16\r
+       orr z80hl,z80hl,r1, lsl #24\r
+       fetch 7\r
+DAATABLE_LOCAL: .word DAATable\r
+;@DAA\r
+opcode_2_7:\r
+       mov r1,z80a, lsr #24\r
+       tst z80f,#1<<CFlag\r
+       orrne r1,r1,#256\r
+       tst z80f,#1<<HFlag\r
+       orrne r1,r1,#512\r
+       tst z80f,#1<<NFlag\r
+       orrne r1,r1,#1024\r
+       ldr r2,DAATABLE_LOCAL\r
+       add r2,r2,r1, lsl #1\r
+       ldrh r1,[r2]\r
+       and z80f,r1,#0xFF\r
+       and r2,r1,#0xFF<<8\r
+       mov z80a,r2, lsl #16\r
+       fetch 4\r
+;@JR Z,$+2\r
+opcode_2_8:\r
+       tst z80f,#1<<ZFlag\r
+       bne opcode_1_8\r
+       add z80pc,z80pc,#1\r
+       fetch 7\r
+;@ADD HL,HL\r
+opcode_2_9:\r
+       opADD16_2 z80hl\r
+       fetch 11\r
+;@LD HL,(NN)\r
+opcode_ED_6B:\r
+       eatcycles 4\r
+;@LD HL,(NN)\r
+opcode_2_A:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+       orr r0,r0,r1, lsl #8\r
+       readmem16\r
+       mov z80hl,r0, lsl #16\r
+       fetch 16\r
+;@DEC HL\r
+opcode_2_B:\r
+       sub z80hl,z80hl,#1<<16\r
+       fetch 6\r
+;@INC L\r
+opcode_2_C:\r
+       opINC8L z80hl\r
+       fetch 4\r
+;@DEC L\r
+opcode_2_D:\r
+       opDEC8L z80hl\r
+       fetch 4\r
+;@LD L,N\r
+opcode_2_E:\r
+       ldrb r0,[z80pc],#1\r
+       and z80hl,z80hl,#0xFF<<24\r
+       orr z80hl,z80hl,r0, lsl #16\r
+       fetch 7\r
+;@CPL\r
+opcode_2_F:\r
+       eor z80a,z80a,#0xFF<<24\r
+       orr z80f,z80f,#(1<<NFlag)|(1<<HFlag)\r
+       fetch 4\r
+;@JR NC,$+2\r
+opcode_3_0:\r
+       tst z80f,#1<<CFlag\r
+       beq opcode_1_8\r
+       add z80pc,z80pc,#1\r
+       fetch 7\r
+;@LD SP,NN\r
+opcode_3_1:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+\r
+.if FAST_Z80SP\r
+       orr r0,r0,r1, lsl #8\r
+       rebasesp\r
+       mov z80sp,r0\r
+.else\r
+       orr z80sp,r0,r1, lsl #8\r
+.endif\r
+       fetch 10\r
+;@LD (NN),A\r
+opcode_3_2:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+       orr r1,r0,r1, lsl #8\r
+       mov r0,z80a, lsr #24\r
+       writemem8\r
+       fetch 13\r
+;@INC SP\r
+opcode_3_3:\r
+       add z80sp,z80sp,#1\r
+       fetch 6\r
+;@INC (HL)\r
+opcode_3_4:\r
+       readmem8HL\r
+       opINC8b\r
+       writemem8HL\r
+       fetch 11\r
+;@DEC (HL)\r
+opcode_3_5:\r
+       readmem8HL\r
+       opDEC8b\r
+       writemem8HL\r
+       fetch 11\r
+;@LD (HL),N\r
+opcode_3_6:\r
+       ldrb r0,[z80pc],#1\r
+       writemem8HL\r
+       fetch 10\r
+;@SCF\r
+opcode_3_7:\r
+       bic z80f,z80f,#(1<<NFlag)|(1<<HFlag)\r
+       orr z80f,z80f,#1<<CFlag\r
+       fetch 4\r
+;@JR C,$+2\r
+opcode_3_8:\r
+       tst z80f,#1<<CFlag\r
+       bne opcode_1_8\r
+       add z80pc,z80pc,#1\r
+       fetch 8\r
+;@ADD HL,SP\r
+opcode_3_9:\r
+.if FAST_Z80SP\r
+       ldr r0,[cpucontext,#z80sp_base]\r
+       sub r0,z80sp,r0\r
+       opADD16s z80hl r0 16\r
+.else\r
+       opADD16s z80hl z80sp 16\r
+.endif\r
+       fetch 11\r
+;@LD A,(NN)\r
+opcode_3_A:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+       orr r0,r0,r1, lsl #8\r
+       readmem8\r
+       mov z80a,r0, lsl #24\r
+       fetch 11\r
+;@DEC SP\r
+opcode_3_B:\r
+       sub z80sp,z80sp,#1\r
+       fetch 6\r
+;@INC A\r
+opcode_3_C:\r
+       opINC8 z80a\r
+       fetch 4\r
+;@DEC A\r
+opcode_3_D:\r
+       opDEC8 z80a\r
+       fetch 4\r
+;@LD A,N\r
+opcode_3_E:\r
+       ldrb r0,[z80pc],#1\r
+       mov z80a,r0, lsl #24\r
+       fetch 7\r
+;@CCF\r
+opcode_3_F:\r
+       bic z80f,z80f,#(1<<NFlag)|(1<<HFlag)\r
+       tst z80f,#1<<CFlag\r
+       orrne z80f,z80f,#1<<HFlag\r
+       eor z80f,z80f,#1<<CFlag\r
+       fetch 4\r
+\r
+;@LD B,C\r
+opcode_4_1:\r
+       and z80bc,z80bc,#0xFF<<16\r
+       orr z80bc,z80bc,z80bc, lsl #8\r
+       fetch 4\r
+;@LD B,D\r
+opcode_4_2:\r
+       and z80bc,z80bc,#0xFF<<16\r
+       and r1,z80de,#0xFF<<24\r
+       orr z80bc,z80bc,r1\r
+       fetch 4\r
+;@LD B,E\r
+opcode_4_3:\r
+       and z80bc,z80bc,#0xFF<<16\r
+       and r1,z80de,#0xFF<<16\r
+       orr z80bc,z80bc,r1, lsl #8\r
+       fetch 4\r
+;@LD B,H\r
+opcode_4_4:\r
+       and z80bc,z80bc,#0xFF<<16\r
+       and r1,z80hl,#0xFF<<24\r
+       orr z80bc,z80bc,r1\r
+       fetch 4\r
+;@LD B,L\r
+opcode_4_5:\r
+       and z80bc,z80bc,#0xFF<<16\r
+       and r1,z80hl,#0xFF<<16\r
+       orr z80bc,z80bc,r1, lsl #8\r
+       fetch 4\r
+;@LD B,(HL)\r
+opcode_4_6:\r
+       readmem8HL\r
+       and z80bc,z80bc,#0xFF<<16\r
+       orr z80bc,z80bc,r0, lsl #24\r
+       fetch 7\r
+;@LD B,A\r
+opcode_4_7:\r
+       and z80bc,z80bc,#0xFF<<16\r
+       orr z80bc,z80bc,z80a\r
+       fetch 4\r
+;@LD C,B\r
+opcode_4_8:\r
+       and z80bc,z80bc,#0xFF<<24\r
+       orr z80bc,z80bc,z80bc, lsr #8\r
+       fetch 4\r
+;@LD C,D\r
+opcode_4_A:\r
+       and z80bc,z80bc,#0xFF<<24\r
+       and r1,z80de,#0xFF<<24\r
+       orr z80bc,z80bc,r1, lsr #8\r
+       fetch 4\r
+;@LD C,E\r
+opcode_4_B:\r
+       and z80bc,z80bc,#0xFF<<24\r
+       and r1,z80de,#0xFF<<16\r
+       orr z80bc,z80bc,r1 \r
+       fetch 4\r
+;@LD C,H\r
+opcode_4_C:\r
+       and z80bc,z80bc,#0xFF<<24\r
+       and r1,z80hl,#0xFF<<24\r
+       orr z80bc,z80bc,r1, lsr #8\r
+       fetch 4\r
+;@LD C,L\r
+opcode_4_D:\r
+       and z80bc,z80bc,#0xFF<<24\r
+       and r1,z80hl,#0xFF<<16\r
+       orr z80bc,z80bc,r1 \r
+       fetch 4\r
+;@LD C,(HL)\r
+opcode_4_E:\r
+       readmem8HL\r
+       and z80bc,z80bc,#0xFF<<24\r
+       orr z80bc,z80bc,r0, lsl #16\r
+       fetch 7\r
+;@LD C,A\r
+opcode_4_F:\r
+       and z80bc,z80bc,#0xFF<<24\r
+       orr z80bc,z80bc,z80a, lsr #8\r
+       fetch 4\r
+;@LD D,B\r
+opcode_5_0:\r
+       and z80de,z80de,#0xFF<<16\r
+       and r1,z80bc,#0xFF<<24\r
+       orr z80de,z80de,r1\r
+       fetch 4\r
+;@LD D,C\r
+opcode_5_1:\r
+       and z80de,z80de,#0xFF<<16\r
+       orr z80de,z80de,z80bc, lsl #8\r
+       fetch 4\r
+;@LD D,E\r
+opcode_5_3:\r
+       and z80de,z80de,#0xFF<<16\r
+       orr z80de,z80de,z80de, lsl #8\r
+       fetch 4\r
+;@LD D,H\r
+opcode_5_4:\r
+       and z80de,z80de,#0xFF<<16\r
+       and r1,z80hl,#0xFF<<24\r
+       orr z80de,z80de,r1\r
+       fetch 4\r
+;@LD D,L\r
+opcode_5_5:\r
+       and z80de,z80de,#0xFF<<16\r
+       orr z80de,z80de,z80hl, lsl #8\r
+       fetch 4\r
+;@LD D,(HL)\r
+opcode_5_6:\r
+       readmem8HL\r
+       and z80de,z80de,#0xFF<<16\r
+       orr z80de,z80de,r0, lsl #24\r
+       fetch 7\r
+;@LD D,A\r
+opcode_5_7:\r
+       and z80de,z80de,#0xFF<<16\r
+       orr z80de,z80de,z80a\r
+       fetch 4\r
+;@LD E,B\r
+opcode_5_8:\r
+       and z80de,z80de,#0xFF<<24\r
+       and r1,z80bc,#0xFF<<24\r
+       orr z80de,z80de,r1, lsr #8\r
+       fetch 4\r
+;@LD E,C\r
+opcode_5_9:\r
+       and z80de,z80de,#0xFF<<24\r
+       and r1,z80bc,#0xFF<<16\r
+       orr z80de,z80de,r1 \r
+       fetch 4\r
+;@LD E,D\r
+opcode_5_A:\r
+       and z80de,z80de,#0xFF<<24\r
+       orr z80de,z80de,z80de, lsr #8\r
+       fetch 4\r
+;@LD E,H\r
+opcode_5_C:\r
+       and z80de,z80de,#0xFF<<24\r
+       and r1,z80hl,#0xFF<<24\r
+       orr z80de,z80de,r1, lsr #8\r
+       fetch 4\r
+;@LD E,L\r
+opcode_5_D:\r
+       and z80de,z80de,#0xFF<<24\r
+       and r1,z80hl,#0xFF<<16\r
+       orr z80de,z80de,r1 \r
+       fetch 4\r
+;@LD E,(HL)\r
+opcode_5_E:\r
+       readmem8HL\r
+       and z80de,z80de,#0xFF<<24\r
+       orr z80de,z80de,r0, lsl #16\r
+       fetch 7\r
+;@LD E,A\r
+opcode_5_F:\r
+       and z80de,z80de,#0xFF<<24\r
+       orr z80de,z80de,z80a, lsr #8\r
+       fetch 4\r
+\r
+;@LD H,B\r
+opcode_6_0:\r
+       and z80hl,z80hl,#0xFF<<16\r
+       and r1,z80bc,#0xFF<<24\r
+       orr z80hl,z80hl,r1\r
+       fetch 4\r
+;@LD H,C\r
+opcode_6_1:\r
+       and z80hl,z80hl,#0xFF<<16\r
+       orr z80hl,z80hl,z80bc, lsl #8\r
+       fetch 4\r
+;@LD H,D\r
+opcode_6_2:\r
+       and z80hl,z80hl,#0xFF<<16\r
+       and r1,z80de,#0xFF<<24\r
+       orr z80hl,z80hl,r1\r
+       fetch 4\r
+;@LD H,E\r
+opcode_6_3:\r
+       and z80hl,z80hl,#0xFF<<16\r
+       orr z80hl,z80hl,z80de, lsl #8\r
+       fetch 4\r
+;@LD H,L\r
+opcode_6_5:\r
+       and z80hl,z80hl,#0xFF<<16\r
+       orr z80hl,z80hl,z80hl, lsl #8\r
+       fetch 4\r
+;@LD H,(HL)\r
+opcode_6_6:\r
+       readmem8HL\r
+       and z80hl,z80hl,#0xFF<<16\r
+       orr z80hl,z80hl,r0, lsl #24\r
+       fetch 7\r
+;@LD H,A\r
+opcode_6_7:\r
+       and z80hl,z80hl,#0xFF<<16\r
+       orr z80hl,z80hl,z80a\r
+       fetch 4\r
+\r
+;@LD L,B\r
+opcode_6_8:\r
+       and z80hl,z80hl,#0xFF<<24\r
+       and r1,z80bc,#0xFF<<24\r
+       orr z80hl,z80hl,r1, lsr #8\r
+       fetch 4\r
+;@LD L,C\r
+opcode_6_9:\r
+       and z80hl,z80hl,#0xFF<<24\r
+       and r1,z80bc,#0xFF<<16\r
+       orr z80hl,z80hl,r1\r
+       fetch 4\r
+;@LD L,D\r
+opcode_6_A:\r
+       and z80hl,z80hl,#0xFF<<24\r
+       and r1,z80de,#0xFF<<24\r
+       orr z80hl,z80hl,r1, lsr #8\r
+       fetch 4\r
+;@LD L,E\r
+opcode_6_B:\r
+       and z80hl,z80hl,#0xFF<<24\r
+       and r1,z80de,#0xFF<<16\r
+       orr z80hl,z80hl,r1\r
+       fetch 4\r
+;@LD L,H\r
+opcode_6_C:\r
+       and z80hl,z80hl,#0xFF<<24\r
+       orr z80hl,z80hl,z80hl, lsr #8\r
+       fetch 4\r
+;@LD L,(HL)\r
+opcode_6_E:\r
+       readmem8HL\r
+       and z80hl,z80hl,#0xFF<<24\r
+       orr z80hl,z80hl,r0, lsl #16\r
+       fetch 7\r
+;@LD L,A\r
+opcode_6_F:\r
+       and z80hl,z80hl,#0xFF<<24\r
+       orr z80hl,z80hl,z80a, lsr #8\r
+       fetch 4\r
+\r
+;@LD (HL),B\r
+opcode_7_0:\r
+       mov r0,z80bc, lsr #24\r
+       writemem8HL\r
+       fetch 7\r
+;@LD (HL),C\r
+opcode_7_1:\r
+       mov r0,z80bc, lsr #16\r
+       and r0,r0,#0xFF\r
+       writemem8HL\r
+       fetch 7\r
+;@LD (HL),D\r
+opcode_7_2:\r
+       mov r0,z80de, lsr #24\r
+       writemem8HL\r
+       fetch 7\r
+;@LD (HL),E\r
+opcode_7_3:\r
+       mov r0,z80de, lsr #16\r
+       and r0,r0,#0xFF\r
+       writemem8HL\r
+       fetch 7\r
+;@LD (HL),H\r
+opcode_7_4:\r
+       mov r0,z80hl, lsr #24\r
+       writemem8HL\r
+       fetch 7\r
+;@LD (HL),L\r
+opcode_7_5:\r
+       mov r1,z80hl, lsr #16\r
+       and r0,r1,#0xFF\r
+       writemem8\r
+       fetch 7\r
+;@HALT\r
+opcode_7_6:\r
+       sub z80pc,z80pc,#1\r
+       ldrb r0,[cpucontext,#z80if]\r
+       orr r0,r0,#Z80_HALT\r
+       strb r0,[cpucontext,#z80if]\r
+       b z80_execute_end\r
+;@LD (HL),A\r
+opcode_7_7:\r
+       mov r0,z80a, lsr #24\r
+       writemem8HL\r
+       fetch 7\r
+\r
+;@LD A,B\r
+opcode_7_8:\r
+       and z80a,z80bc,#0xFF<<24\r
+       fetch 4\r
+;@LD A,C\r
+opcode_7_9:\r
+       mov z80a,z80bc, lsl #8\r
+       fetch 4\r
+;@LD A,D\r
+opcode_7_A:\r
+       and z80a,z80de,#0xFF<<24\r
+       fetch 4\r
+;@LD A,E\r
+opcode_7_B:\r
+       mov z80a,z80de, lsl #8\r
+       fetch 4\r
+;@LD A,H\r
+opcode_7_C:\r
+       and z80a,z80hl,#0xFF<<24\r
+       fetch 4\r
+;@LD A,L\r
+opcode_7_D:\r
+       mov z80a,z80hl, lsl #8\r
+       fetch 4\r
+;@LD A,(HL)\r
+opcode_7_E:\r
+       readmem8HL\r
+       mov z80a,r0, lsl #24\r
+       fetch 7\r
+\r
+;@ADD A,B\r
+opcode_8_0:\r
+       opADDH z80bc\r
+;@ADD A,C\r
+opcode_8_1:\r
+       opADDL z80bc\r
+;@ADD A,D\r
+opcode_8_2:\r
+       opADDH z80de\r
+;@ADD A,E\r
+opcode_8_3:\r
+       opADDL z80de\r
+;@ADD A,H\r
+opcode_8_4:\r
+       opADDH z80hl\r
+;@ADD A,L\r
+opcode_8_5:\r
+       opADDL z80hl\r
+;@ADD A,(HL)\r
+opcode_8_6:\r
+       readmem8HL\r
+       opADDb\r
+       fetch 7\r
+;@ADD A,A\r
+opcode_8_7:\r
+       opADDA\r
+\r
+;@ADC A,B\r
+opcode_8_8:\r
+       opADCH z80bc\r
+;@ADC A,C\r
+opcode_8_9:\r
+       opADCL z80bc\r
+;@ADC A,D\r
+opcode_8_A:\r
+       opADCH z80de\r
+;@ADC A,E\r
+opcode_8_B:\r
+       opADCL z80de\r
+;@ADC A,H\r
+opcode_8_C:\r
+       opADCH z80hl\r
+;@ADC A,L\r
+opcode_8_D:\r
+       opADCL z80hl\r
+;@ADC A,(HL)\r
+opcode_8_E:\r
+       readmem8HL\r
+       opADCb\r
+       fetch 7\r
+;@ADC A,A\r
+opcode_8_F:\r
+       opADCA\r
+\r
+;@SUB B\r
+opcode_9_0:\r
+       opSUBH z80bc\r
+;@SUB C\r
+opcode_9_1:\r
+       opSUBL z80bc\r
+;@SUB D\r
+opcode_9_2:\r
+       opSUBH z80de\r
+;@SUB E\r
+opcode_9_3:\r
+       opSUBL z80de\r
+;@SUB H\r
+opcode_9_4:\r
+       opSUBH z80hl\r
+;@SUB L\r
+opcode_9_5:\r
+       opSUBL z80hl\r
+;@SUB (HL)\r
+opcode_9_6:\r
+       readmem8HL\r
+       opSUBb\r
+       fetch 7\r
+;@SUB A\r
+opcode_9_7:\r
+       opSUBA\r
+\r
+;@SBC B \r
+opcode_9_8:\r
+       opSBCH z80bc\r
+;@SBC C\r
+opcode_9_9:\r
+       opSBCL z80bc\r
+;@SBC D\r
+opcode_9_A:\r
+       opSBCH z80de\r
+;@SBC E\r
+opcode_9_B:\r
+       opSBCL z80de\r
+;@SBC H\r
+opcode_9_C:\r
+       opSBCH z80hl\r
+;@SBC L\r
+opcode_9_D:\r
+       opSBCL z80hl\r
+;@SBC (HL)\r
+opcode_9_E:\r
+       readmem8HL\r
+       opSBCb\r
+       fetch 7\r
+;@SBC A\r
+opcode_9_F:\r
+       opSBCA\r
+\r
+;@AND B\r
+opcode_A_0:\r
+       opANDH z80bc\r
+;@AND C\r
+opcode_A_1:\r
+       opANDL z80bc\r
+;@AND D\r
+opcode_A_2:\r
+       opANDH z80de\r
+;@AND E\r
+opcode_A_3:\r
+       opANDL z80de\r
+;@AND H\r
+opcode_A_4:\r
+       opANDH z80hl\r
+;@AND L\r
+opcode_A_5:\r
+       opANDL z80hl\r
+;@AND (HL)\r
+opcode_A_6:\r
+       readmem8HL\r
+       opANDb\r
+       fetch 7\r
+;@AND A\r
+opcode_A_7:\r
+       opANDA\r
+\r
+;@XOR B\r
+opcode_A_8:\r
+       opXORH z80bc\r
+;@XOR C\r
+opcode_A_9:\r
+       opXORL z80bc\r
+;@XOR D\r
+opcode_A_A:\r
+       opXORH z80de\r
+;@XOR E\r
+opcode_A_B:\r
+       opXORL z80de\r
+;@XOR H\r
+opcode_A_C:\r
+       opXORH z80hl\r
+;@XOR L\r
+opcode_A_D:\r
+       opXORL z80hl\r
+;@XOR (HL)\r
+opcode_A_E:\r
+       readmem8HL\r
+       opXORb\r
+       fetch 7\r
+;@XOR A\r
+opcode_A_F:\r
+       opXORA\r
+\r
+;@OR B\r
+opcode_B_0:\r
+       opORH z80bc\r
+;@OR C\r
+opcode_B_1:\r
+       opORL z80bc\r
+;@OR D\r
+opcode_B_2:\r
+       opORH z80de\r
+;@OR E\r
+opcode_B_3:\r
+       opORL z80de\r
+;@OR H\r
+opcode_B_4:\r
+       opORH z80hl\r
+;@OR L\r
+opcode_B_5:\r
+       opORL z80hl\r
+;@OR (HL)\r
+opcode_B_6:\r
+       readmem8HL\r
+       opORb\r
+       fetch 7\r
+;@OR A\r
+opcode_B_7:\r
+       opORA\r
+\r
+;@CP B\r
+opcode_B_8:\r
+       opCPH z80bc\r
+;@CP C\r
+opcode_B_9:\r
+       opCPL z80bc\r
+;@CP D\r
+opcode_B_A:\r
+       opCPH z80de\r
+;@CP E\r
+opcode_B_B:\r
+       opCPL z80de\r
+;@CP H\r
+opcode_B_C:\r
+       opCPH z80hl\r
+;@CP L\r
+opcode_B_D:\r
+       opCPL z80hl\r
+;@CP (HL)\r
+opcode_B_E:\r
+       readmem8HL\r
+       opCPb\r
+       fetch 7\r
+;@CP A\r
+opcode_B_F:\r
+       opCPA\r
+\r
+;@RET NZ\r
+opcode_C_0:\r
+       tst z80f,#1<<ZFlag\r
+       beq opcode_C_9          ;@unconditional RET\r
+       fetch 5\r
+\r
+;@POP BC\r
+opcode_C_1:\r
+       opPOPreg z80bc\r
+\r
+;@JP NZ,$+3\r
+opcode_C_2:\r
+       tst z80f,#1<<ZFlag\r
+       beq opcode_C_3          ;@unconditional JP\r
+       add z80pc,z80pc,#2\r
+       fetch 10\r
+;@JP $+3\r
+opcode_C_3:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+       orr r0,r0,r1, lsl #8\r
+       rebasepc\r
+       fetch 10\r
+;@CALL NZ,NN\r
+opcode_C_4:\r
+       tst z80f,#1<<ZFlag\r
+       beq opcode_C_D          ;@unconditional CALL\r
+       add z80pc,z80pc,#2\r
+       fetch 10\r
+\r
+;@PUSH BC\r
+opcode_C_5:\r
+       opPUSHreg z80bc\r
+       fetch 11\r
+;@ADD A,N\r
+opcode_C_6:\r
+       ldrb r0,[z80pc],#1\r
+       opADDb\r
+       fetch 7\r
+;@RST 0\r
+opcode_C_7:\r
+       opRST 0x00\r
+\r
+;@RET Z\r
+opcode_C_8:\r
+       tst z80f,#1<<ZFlag\r
+       bne opcode_C_9          ;@unconditional RET\r
+       fetch 5\r
+;@RET\r
+opcode_C_9:\r
+    opPOP\r
+       rebasepc\r
+       fetch 10\r
+;@JP Z,$+3\r
+opcode_C_A:\r
+       tst z80f,#1<<ZFlag\r
+       bne opcode_C_3  ;@unconditional JP\r
+       add z80pc,z80pc,#2\r
+       fetch 10\r
+\r
+;@This reads this opcodes_CB lookup table to find the location of\r
+;@the CB sub for the intruction and then branches to that location\r
+opcode_C_B:\r
+       ldrb r0,[z80pc],#1\r
+       ldr pc,[pc,r0, lsl #2]\r
+opcodes_CB:    .word 0x00000000\r
+                       .word opcode_CB_00,opcode_CB_01,opcode_CB_02,opcode_CB_03,opcode_CB_04,opcode_CB_05,opcode_CB_06,opcode_CB_07\r
+                       .word opcode_CB_08,opcode_CB_09,opcode_CB_0A,opcode_CB_0B,opcode_CB_0C,opcode_CB_0D,opcode_CB_0E,opcode_CB_0F\r
+                       .word opcode_CB_10,opcode_CB_11,opcode_CB_12,opcode_CB_13,opcode_CB_14,opcode_CB_15,opcode_CB_16,opcode_CB_17\r
+                       .word opcode_CB_18,opcode_CB_19,opcode_CB_1A,opcode_CB_1B,opcode_CB_1C,opcode_CB_1D,opcode_CB_1E,opcode_CB_1F\r
+                       .word opcode_CB_20,opcode_CB_21,opcode_CB_22,opcode_CB_23,opcode_CB_24,opcode_CB_25,opcode_CB_26,opcode_CB_27\r
+                       .word opcode_CB_28,opcode_CB_29,opcode_CB_2A,opcode_CB_2B,opcode_CB_2C,opcode_CB_2D,opcode_CB_2E,opcode_CB_2F\r
+                       .word opcode_CB_30,opcode_CB_31,opcode_CB_32,opcode_CB_33,opcode_CB_34,opcode_CB_35,opcode_CB_36,opcode_CB_37\r
+                       .word opcode_CB_38,opcode_CB_39,opcode_CB_3A,opcode_CB_3B,opcode_CB_3C,opcode_CB_3D,opcode_CB_3E,opcode_CB_3F\r
+                       .word opcode_CB_40,opcode_CB_41,opcode_CB_42,opcode_CB_43,opcode_CB_44,opcode_CB_45,opcode_CB_46,opcode_CB_47\r
+                       .word opcode_CB_48,opcode_CB_49,opcode_CB_4A,opcode_CB_4B,opcode_CB_4C,opcode_CB_4D,opcode_CB_4E,opcode_CB_4F\r
+                       .word opcode_CB_50,opcode_CB_51,opcode_CB_52,opcode_CB_53,opcode_CB_54,opcode_CB_55,opcode_CB_56,opcode_CB_57\r
+                       .word opcode_CB_58,opcode_CB_59,opcode_CB_5A,opcode_CB_5B,opcode_CB_5C,opcode_CB_5D,opcode_CB_5E,opcode_CB_5F\r
+                       .word opcode_CB_60,opcode_CB_61,opcode_CB_62,opcode_CB_63,opcode_CB_64,opcode_CB_65,opcode_CB_66,opcode_CB_67\r
+                       .word opcode_CB_68,opcode_CB_69,opcode_CB_6A,opcode_CB_6B,opcode_CB_6C,opcode_CB_6D,opcode_CB_6E,opcode_CB_6F\r
+                       .word opcode_CB_70,opcode_CB_71,opcode_CB_72,opcode_CB_73,opcode_CB_74,opcode_CB_75,opcode_CB_76,opcode_CB_77\r
+                       .word opcode_CB_78,opcode_CB_79,opcode_CB_7A,opcode_CB_7B,opcode_CB_7C,opcode_CB_7D,opcode_CB_7E,opcode_CB_7F\r
+                       .word opcode_CB_80,opcode_CB_81,opcode_CB_82,opcode_CB_83,opcode_CB_84,opcode_CB_85,opcode_CB_86,opcode_CB_87\r
+                       .word opcode_CB_88,opcode_CB_89,opcode_CB_8A,opcode_CB_8B,opcode_CB_8C,opcode_CB_8D,opcode_CB_8E,opcode_CB_8F\r
+                       .word opcode_CB_90,opcode_CB_91,opcode_CB_92,opcode_CB_93,opcode_CB_94,opcode_CB_95,opcode_CB_96,opcode_CB_97\r
+                       .word opcode_CB_98,opcode_CB_99,opcode_CB_9A,opcode_CB_9B,opcode_CB_9C,opcode_CB_9D,opcode_CB_9E,opcode_CB_9F\r
+                       .word opcode_CB_A0,opcode_CB_A1,opcode_CB_A2,opcode_CB_A3,opcode_CB_A4,opcode_CB_A5,opcode_CB_A6,opcode_CB_A7\r
+                       .word opcode_CB_A8,opcode_CB_A9,opcode_CB_AA,opcode_CB_AB,opcode_CB_AC,opcode_CB_AD,opcode_CB_AE,opcode_CB_AF\r
+                       .word opcode_CB_B0,opcode_CB_B1,opcode_CB_B2,opcode_CB_B3,opcode_CB_B4,opcode_CB_B5,opcode_CB_B6,opcode_CB_B7\r
+                       .word opcode_CB_B8,opcode_CB_B9,opcode_CB_BA,opcode_CB_BB,opcode_CB_BC,opcode_CB_BD,opcode_CB_BE,opcode_CB_BF\r
+                       .word opcode_CB_C0,opcode_CB_C1,opcode_CB_C2,opcode_CB_C3,opcode_CB_C4,opcode_CB_C5,opcode_CB_C6,opcode_CB_C7\r
+                       .word opcode_CB_C8,opcode_CB_C9,opcode_CB_CA,opcode_CB_CB,opcode_CB_CC,opcode_CB_CD,opcode_CB_CE,opcode_CB_CF\r
+                       .word opcode_CB_D0,opcode_CB_D1,opcode_CB_D2,opcode_CB_D3,opcode_CB_D4,opcode_CB_D5,opcode_CB_D6,opcode_CB_D7\r
+                       .word opcode_CB_D8,opcode_CB_D9,opcode_CB_DA,opcode_CB_DB,opcode_CB_DC,opcode_CB_DD,opcode_CB_DE,opcode_CB_DF\r
+                       .word opcode_CB_E0,opcode_CB_E1,opcode_CB_E2,opcode_CB_E3,opcode_CB_E4,opcode_CB_E5,opcode_CB_E6,opcode_CB_E7\r
+                       .word opcode_CB_E8,opcode_CB_E9,opcode_CB_EA,opcode_CB_EB,opcode_CB_EC,opcode_CB_ED,opcode_CB_EE,opcode_CB_EF\r
+                       .word opcode_CB_F0,opcode_CB_F1,opcode_CB_F2,opcode_CB_F3,opcode_CB_F4,opcode_CB_F5,opcode_CB_F6,opcode_CB_F7\r
+                       .word opcode_CB_F8,opcode_CB_F9,opcode_CB_FA,opcode_CB_FB,opcode_CB_FC,opcode_CB_FD,opcode_CB_FE,opcode_CB_FF\r
+\r
+;@CALL Z,NN\r
+opcode_C_C:\r
+       tst z80f,#1<<ZFlag\r
+       bne opcode_C_D          ;@unconditional CALL\r
+       add z80pc,z80pc,#2\r
+       fetch 10\r
+;@CALL NN\r
+opcode_C_D:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+       ldr r2,[cpucontext,#z80pc_base]\r
+       sub r2,z80pc,r2\r
+       orr z80pc,r0,r1, lsl #8\r
+    opPUSHareg r2\r
+    mov r0,z80pc\r
+       rebasepc\r
+       fetch 17\r
+;@ADC A,N\r
+opcode_C_E:\r
+       ldrb r0,[z80pc],#1\r
+       opADCb\r
+       fetch 7\r
+;@RST 8H\r
+opcode_C_F:\r
+       opRST 0x08\r
+\r
+;@RET NC\r
+opcode_D_0:\r
+       tst z80f,#1<<CFlag\r
+       beq opcode_C_9          ;@unconditional RET\r
+       fetch 5\r
+;@POP DE\r
+opcode_D_1:\r
+       opPOPreg z80de\r
+\r
+;@JP NC, $+3\r
+opcode_D_2 :\r
+       tst z80f,#1<<CFlag\r
+       beq opcode_C_3          ;@unconditional JP\r
+       add z80pc,z80pc,#2\r
+       fetch 10\r
+;@OUT (N),A\r
+opcode_D_3:\r
+       ldrb r0,[z80pc],#1\r
+       orr r0,r0,z80a,lsr#16\r
+       mov r1,z80a, lsr #24\r
+       opOUT\r
+       fetch 11\r
+;@CALL NC,NN\r
+opcode_D_4:\r
+       tst z80f,#1<<CFlag\r
+       beq opcode_C_D          ;@unconditional CALL\r
+       add z80pc,z80pc,#2\r
+       fetch 10\r
+;@PUSH DE\r
+opcode_D_5:\r
+       opPUSHreg z80de\r
+       fetch 11\r
+;@SUB N\r
+opcode_D_6:\r
+       ldrb r0,[z80pc],#1\r
+       opSUBb\r
+       fetch 7\r
+\r
+;@RST 10H\r
+opcode_D_7:\r
+       opRST 0x10\r
+\r
+;@RET C\r
+opcode_D_8:\r
+       tst z80f,#1<<CFlag\r
+       bne opcode_C_9          ;@unconditional RET\r
+       fetch 5\r
+;@EXX\r
+opcode_D_9:\r
+       add r1,cpucontext,#z80bc2\r
+       swp z80bc,z80bc,[r1]\r
+       add r1,cpucontext,#z80de2\r
+       swp z80de,z80de,[r1]\r
+       add r1,cpucontext,#z80hl2\r
+       swp z80hl,z80hl,[r1]\r
+       fetch 4\r
+;@JP C,$+3\r
+opcode_D_A:\r
+       tst z80f,#1<<CFlag\r
+       bne opcode_C_3          ;@unconditional JP\r
+       add z80pc,z80pc,#2\r
+       fetch 10\r
+;@IN A,(N)\r
+opcode_D_B:\r
+       ldrb r0,[z80pc],#1\r
+       orr r0,r0,z80a,lsr#16\r
+       opIN\r
+       mov z80a,r0, lsl #24    ;@ r0 = data read\r
+       fetch 11\r
+;@CALL C,NN\r
+opcode_D_C:\r
+       tst z80f,#1<<CFlag\r
+       bne opcode_C_D          ;@unconditional CALL\r
+       add z80pc,z80pc,#2\r
+       fetch 10\r
+\r
+;@opcodes_DD\r
+opcode_D_D:\r
+       add z80xx,cpucontext,#z80ix\r
+       b opcode_D_D_F_D\r
+opcode_F_D:\r
+       add z80xx,cpucontext,#z80iy\r
+opcode_D_D_F_D:\r
+       ldrb r0,[z80pc],#1\r
+       ldr pc,[pc,r0, lsl #2]\r
+opcodes_DD:    .word 0x00000000\r
+                       .word opcode_0_0,  opcode_0_1,  opcode_0_2,  opcode_0_3,  opcode_0_4,  opcode_0_5,  opcode_0_6,  opcode_0_7\r
+                       .word opcode_0_8,  opcode_DD_09,opcode_0_A,  opcode_0_B,  opcode_0_C,  opcode_0_D,  opcode_0_E,  opcode_0_F\r
+                       .word opcode_1_0,  opcode_1_1,  opcode_1_2,  opcode_1_3,  opcode_1_4,  opcode_1_5,  opcode_1_6,  opcode_1_7\r
+                       .word opcode_1_8,  opcode_DD_19,opcode_1_A,  opcode_1_B,  opcode_1_C,  opcode_1_D,  opcode_1_E,  opcode_1_F\r
+                       .word opcode_2_0,  opcode_DD_21,opcode_DD_22,opcode_DD_23,opcode_DD_24,opcode_DD_25,opcode_DD_26,opcode_2_7\r
+                       .word opcode_2_8,  opcode_DD_29,opcode_DD_2A,opcode_DD_2B,opcode_DD_2C,opcode_DD_2D,opcode_DD_2E,opcode_2_F\r
+                       .word opcode_3_0,  opcode_3_1,  opcode_3_2,  opcode_3_3,  opcode_DD_34,opcode_DD_35,opcode_DD_36,opcode_3_7\r
+                       .word opcode_3_8,  opcode_DD_39,opcode_3_A,  opcode_3_B,  opcode_3_C,  opcode_3_D,  opcode_3_E,  opcode_3_F\r
+                       .word opcode_4_0,  opcode_4_1,  opcode_4_2,  opcode_4_3,  opcode_DD_44,opcode_DD_45,opcode_DD_46,opcode_4_7\r
+                       .word opcode_4_8,  opcode_4_9,  opcode_4_A,  opcode_4_B,  opcode_DD_4C,opcode_DD_4D,opcode_DD_4E,opcode_4_F\r
+                       .word opcode_5_0,  opcode_5_1,  opcode_5_2,  opcode_5_3,  opcode_DD_54,opcode_DD_55,opcode_DD_56,opcode_5_7\r
+                       .word opcode_5_8,  opcode_5_9,  opcode_5_A,  opcode_5_B,  opcode_DD_5C,opcode_DD_5D,opcode_DD_5E,opcode_5_F\r
+                       .word opcode_DD_60,opcode_DD_61,opcode_DD_62,opcode_DD_63,opcode_DD_64,opcode_DD_65,opcode_DD_66,opcode_DD_67\r
+                       .word opcode_DD_68,opcode_DD_69,opcode_DD_6A,opcode_DD_6B,opcode_DD_6C,opcode_DD_6D,opcode_DD_6E,opcode_DD_6F\r
+                       .word opcode_DD_70,opcode_DD_71,opcode_DD_72,opcode_DD_73,opcode_DD_74,opcode_DD_75,opcode_7_6,  opcode_DD_77\r
+                       .word opcode_7_8,  opcode_7_9,  opcode_7_A,  opcode_7_B,  opcode_DD_7C,opcode_DD_7D,opcode_DD_7E,opcode_7_F\r
+                       .word opcode_8_0,  opcode_8_1,  opcode_8_2,  opcode_8_3,  opcode_DD_84,opcode_DD_85,opcode_DD_86,opcode_8_7\r
+                       .word opcode_8_8,  opcode_8_9,  opcode_8_A,  opcode_8_B,  opcode_DD_8C,opcode_DD_8D,opcode_DD_8E,opcode_8_F\r
+                       .word opcode_9_0,  opcode_9_1,  opcode_9_2,  opcode_9_3,  opcode_DD_94,opcode_DD_95,opcode_DD_96,opcode_9_7\r
+                       .word opcode_9_8,  opcode_9_9,  opcode_9_A,  opcode_9_B,  opcode_DD_9C,opcode_DD_9D,opcode_DD_9E,opcode_9_F\r
+                       .word opcode_A_0,  opcode_A_1,  opcode_A_2,  opcode_A_3,  opcode_DD_A4,opcode_DD_A5,opcode_DD_A6,opcode_A_7\r
+                       .word opcode_A_8,  opcode_A_9,  opcode_A_A,  opcode_A_B,  opcode_DD_AC,opcode_DD_AD,opcode_DD_AE,opcode_A_F\r
+                       .word opcode_B_0,  opcode_B_1,  opcode_B_2,  opcode_B_3,  opcode_DD_B4,opcode_DD_B5,opcode_DD_B6,opcode_B_7\r
+                       .word opcode_B_8,  opcode_B_9,  opcode_B_A,  opcode_B_B,  opcode_DD_BC,opcode_DD_BD,opcode_DD_BE,opcode_B_F\r
+                       .word opcode_C_0,  opcode_C_1,  opcode_C_2,  opcode_C_3,  opcode_C_4,  opcode_C_5,  opcode_C_6,  opcode_C_7\r
+                       .word opcode_C_8,  opcode_C_9,  opcode_C_A,  opcode_DD_CB,opcode_C_C,  opcode_C_D,  opcode_C_E,  opcode_C_F\r
+                       .word opcode_D_0,  opcode_D_1,  opcode_D_2,  opcode_D_3,  opcode_D_4,  opcode_D_5,  opcode_D_6,  opcode_D_7\r
+                       .word opcode_D_8,  opcode_D_9,  opcode_D_A,  opcode_D_B,  opcode_D_C,  opcode_D_D,  opcode_D_E,  opcode_D_F\r
+                       .word opcode_E_0,  opcode_DD_E1,opcode_E_2,  opcode_DD_E3,opcode_E_4,  opcode_DD_E5,opcode_E_6,  opcode_E_7\r
+                       .word opcode_E_8,  opcode_DD_E9,opcode_E_A,  opcode_E_B,  opcode_E_C,  opcode_E_D,  opcode_E_E,  opcode_E_F\r
+                       .word opcode_F_0,  opcode_F_1,  opcode_F_2,  opcode_F_3,  opcode_F_4,  opcode_F_5,  opcode_F_6,  opcode_F_7\r
+                       .word opcode_F_8,  opcode_DD_F9,opcode_F_A,  opcode_F_B,  opcode_F_C,  opcode_F_D,  opcode_F_E,  opcode_F_F\r
+\r
+;@SBC A,N\r
+opcode_D_E:\r
+       ldrb r0,[z80pc],#1\r
+       opSBCb\r
+       fetch 7\r
+;@RST 18H\r
+opcode_D_F:\r
+       opRST 0x18\r
+\r
+;@RET PO\r
+opcode_E_0:\r
+       tst z80f,#1<<VFlag\r
+       beq opcode_C_9          ;@unconditional RET\r
+       fetch 5\r
+;@POP HL\r
+opcode_E_1:\r
+       opPOPreg z80hl\r
+\r
+;@JP PO,$+3\r
+opcode_E_2:\r
+       tst z80f,#1<<VFlag\r
+       beq opcode_C_3          ;@unconditional JP\r
+       add z80pc,z80pc,#2\r
+       fetch 10\r
+;@EX (SP),HL\r
+opcode_E_3:\r
+.if FAST_Z80SP\r
+       ldrb r0,[z80sp]\r
+       ldrb r1,[z80sp,#1]\r
+       orr r0,r0,r1, lsl #8\r
+       mov r1,z80hl, lsr #24\r
+       strb r1,[z80sp,#1]\r
+       mov r1,z80hl, lsr #16\r
+       strb r1,[z80sp]\r
+       mov z80hl,r0, lsl #16\r
+.else\r
+       mov r0,z80sp\r
+       readmem16\r
+       mov r1,r0\r
+       mov r0,z80hl,lsr#16\r
+       mov z80hl,r1,lsl#16\r
+       mov r1,z80sp\r
+       writemem16\r
+.endif\r
+       fetch 19\r
+;@CALL PO,NN\r
+opcode_E_4:\r
+       tst z80f,#1<<VFlag\r
+       beq opcode_C_D          ;@unconditional CALL\r
+       add z80pc,z80pc,#2\r
+       fetch 10\r
+;@PUSH HL\r
+opcode_E_5:\r
+       opPUSHreg z80hl\r
+       fetch 11\r
+;@AND N\r
+opcode_E_6:\r
+       ldrb r0,[z80pc],#1\r
+       opANDb\r
+       fetch 7\r
+;@RST 20H\r
+opcode_E_7:\r
+       opRST 0x20\r
+\r
+;@RET PE\r
+opcode_E_8:\r
+       tst z80f,#1<<VFlag\r
+       bne opcode_C_9          ;@unconditional RET\r
+       fetch 5\r
+;@JP (HL)\r
+opcode_E_9:\r
+       mov r0,z80hl, lsr #16\r
+       rebasepc\r
+       fetch 4\r
+;@JP PE,$+3\r
+opcode_E_A:\r
+       tst z80f,#1<<VFlag\r
+       bne opcode_C_3          ;@unconditional JP\r
+       add z80pc,z80pc,#2\r
+       fetch 10\r
+;@EX DE,HL\r
+opcode_E_B:\r
+       mov r1,z80de\r
+       mov z80de,z80hl\r
+       mov z80hl,r1\r
+       fetch 4\r
+;@CALL PE,NN\r
+opcode_E_C:\r
+       tst z80f,#1<<VFlag\r
+       bne opcode_C_D          ;@unconditional CALL\r
+       add z80pc,z80pc,#2\r
+       fetch 10\r
+\r
+;@This should be caught at start\r
+opcode_E_D:\r
+       ldrb r1,[z80pc],#1\r
+       ldr pc,[pc,r1, lsl #2]\r
+opcodes_ED:    .word 0x00000000\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_40,opcode_ED_41,opcode_ED_42,opcode_ED_43,opcode_ED_44,opcode_ED_45,opcode_ED_46,opcode_ED_47\r
+                       .word opcode_ED_48,opcode_ED_49,opcode_ED_4A,opcode_ED_4B,opcode_ED_44,opcode_ED_4D,opcode_ED_46,opcode_ED_4F\r
+                       .word opcode_ED_50,opcode_ED_51,opcode_ED_52,opcode_ED_53,opcode_ED_44,opcode_ED_45,opcode_ED_56,opcode_ED_57\r
+                       .word opcode_ED_58,opcode_ED_59,opcode_ED_5A,opcode_ED_5B,opcode_ED_44,opcode_ED_45,opcode_ED_5E,opcode_ED_5F\r
+                       .word opcode_ED_60,opcode_ED_61,opcode_ED_62,opcode_ED_63,opcode_ED_44,opcode_ED_45,opcode_ED_46,opcode_ED_67\r
+                       .word opcode_ED_68,opcode_ED_69,opcode_ED_6A,opcode_ED_6B,opcode_ED_44,opcode_ED_45,opcode_ED_46,opcode_ED_6F\r
+                       .word opcode_ED_70,opcode_ED_71,opcode_ED_72,opcode_ED_73,opcode_ED_44,opcode_ED_45,opcode_ED_56,opcode_ED_NF\r
+                       .word opcode_ED_78,opcode_ED_79,opcode_ED_7A,opcode_ED_7B,opcode_ED_44,opcode_ED_45,opcode_ED_5E,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_A0,opcode_ED_A1,opcode_ED_A2,opcode_ED_A3,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_A8,opcode_ED_A9,opcode_ED_AA,opcode_ED_AB,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_B0,opcode_ED_B1,opcode_ED_B2,opcode_ED_B3,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_B8,opcode_ED_B9,opcode_ED_BA,opcode_ED_BB,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+                       .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
+\r
+;@XOR N\r
+opcode_E_E:\r
+       ldrb r0,[z80pc],#1\r
+       opXORb\r
+       fetch 7\r
+;@RST 28H\r
+opcode_E_F:\r
+       opRST 0x28\r
+\r
+;@RET P\r
+opcode_F_0:\r
+       tst z80f,#1<<SFlag\r
+       beq opcode_C_9          ;@unconditional RET\r
+       fetch 5\r
+;@POP AF\r
+opcode_F_1:\r
+.if FAST_Z80SP\r
+       ldrb z80f,[z80sp],#1\r
+       sub r0,opcodes,#0x200\r
+       ldrb z80f,[r0,z80f]\r
+       ldrb z80a,[z80sp],#1\r
+       mov z80a,z80a, lsl #24\r
+.else\r
+       mov r0,z80sp\r
+       readmem16\r
+       add z80sp,z80sp,#2\r
+       and z80a,r0,#0xFF00\r
+       mov z80a,z80a,lsl#16\r
+       and z80f,r0,#0xFF\r
+       sub r0,opcodes,#0x200\r
+       ldrb z80f,[r0,z80f]\r
+.endif\r
+       fetch 10\r
+;@JP P,$+3\r
+opcode_F_2:\r
+       tst z80f,#1<<SFlag\r
+       beq opcode_C_3          ;@unconditional JP\r
+       add z80pc,z80pc,#2\r
+       fetch 10\r
+;@DI\r
+opcode_F_3:\r
+       ldrb r1,[cpucontext,#z80if]\r
+       bic r1,r1,#(Z80_IF1)|(Z80_IF2)\r
+       strb r1,[cpucontext,#z80if]\r
+       fetch 4\r
+;@CALL P,NN\r
+opcode_F_4:\r
+       tst z80f,#1<<SFlag\r
+       beq opcode_C_D          ;@unconditional CALL\r
+       add z80pc,z80pc,#2\r
+       fetch 10\r
+;@PUSH AF\r
+opcode_F_5:\r
+       sub r0,opcodes,#0x300\r
+       ldrb r0,[r0,z80f]\r
+       orr r2,r0,z80a,lsr#16\r
+    opPUSHareg r2\r
+       fetch 11\r
+;@OR N\r
+opcode_F_6:\r
+       ldrb r0,[z80pc],#1\r
+       opORb\r
+       fetch 7\r
+;@RST 30H\r
+opcode_F_7:\r
+       opRST 0x30\r
+\r
+;@RET M\r
+opcode_F_8:\r
+       tst z80f,#1<<SFlag\r
+       bne opcode_C_9          ;@unconditional RET\r
+       fetch 5\r
+;@LD SP,HL\r
+opcode_F_9:\r
+.if FAST_Z80SP\r
+       mov r0,z80hl, lsr #16\r
+       rebasesp\r
+       mov z80sp,r0\r
+.else\r
+       mov z80sp,z80hl, lsr #16\r
+.endif\r
+       fetch 4\r
+;@JP M,$+3\r
+opcode_F_A:\r
+       tst z80f,#1<<SFlag\r
+       bne opcode_C_3          ;@unconditional JP\r
+       add z80pc,z80pc,#2\r
+       fetch 10\r
+MAIN_opcodes_POINTER: .word MAIN_opcodes\r
+EI_DUMMY_opcodes_POINTER: .word EI_DUMMY_opcodes\r
+;@EI\r
+opcode_F_B:\r
+       ldrb r1,[cpucontext,#z80if]\r
+       tst r1,#Z80_IF1\r
+       bne ei_return_exit\r
+\r
+       orr r1,r1,#(Z80_IF1)|(Z80_IF2)\r
+       strb r1,[cpucontext,#z80if]\r
+\r
+       mov r2,opcodes\r
+       ldr opcodes,EI_DUMMY_opcodes_POINTER\r
+       ldr pc,[r2,r0, lsl #2]\r
+\r
+ei_return:\r
+       ;@point that program returns from EI to check interupts\r
+       ;@an interupt can not be taken directly after a EI opcode\r
+       ;@ reset z80pc and opcode pointer\r
+       ldrh r0,[cpucontext,#z80irq] @ 0x4C\r
+       sub z80pc,z80pc,#1\r
+       ldr opcodes,MAIN_opcodes_POINTER\r
+       ;@ check ints\r
+       tst r0,#1\r
+       movnes r0,r0,lsr #8\r
+    blne DoInterrupt\r
+       ;@ continue\r
+ei_return_exit:\r
+       fetch 4\r
+\r
+;@CALL M,NN\r
+opcode_F_C:\r
+       tst z80f,#1<<SFlag\r
+       bne opcode_C_D          ;@unconditional CALL\r
+       add z80pc,z80pc,#2\r
+       fetch 10\r
+\r
+;@SHOULD BE CAUGHT AT START - FD SECTION\r
+\r
+;@CP N\r
+opcode_F_E:\r
+       ldrb r0,[z80pc],#1\r
+       opCPb\r
+       fetch 7\r
+;@RST 38H\r
+opcode_F_F:\r
+       opRST 0x38\r
+\r
+\r
+;@##################################\r
+;@##################################\r
+;@###  opcodes CB  #########################\r
+;@##################################\r
+;@##################################\r
+\r
+\r
+;@RLC B\r
+opcode_CB_00:\r
+       opRLCH z80bc\r
+;@RLC C\r
+opcode_CB_01:\r
+       opRLCL z80bc\r
+;@RLC D\r
+opcode_CB_02:\r
+       opRLCH z80de\r
+;@RLC E\r
+opcode_CB_03:\r
+       opRLCL z80de\r
+;@RLC H\r
+opcode_CB_04:\r
+       opRLCH z80hl\r
+;@RLC L\r
+opcode_CB_05:\r
+       opRLCL z80hl\r
+;@RLC (HL)\r
+opcode_CB_06:\r
+       readmem8HL\r
+       opRLCb\r
+       writemem8HL\r
+       fetch 15\r
+;@RLC A\r
+opcode_CB_07:\r
+       opRLCA\r
+\r
+;@RRC B\r
+opcode_CB_08:\r
+       opRRCH z80bc\r
+;@RRC C\r
+opcode_CB_09:\r
+       opRRCL z80bc\r
+;@RRC D\r
+opcode_CB_0A:\r
+       opRRCH z80de\r
+;@RRC E\r
+opcode_CB_0B:\r
+       opRRCL z80de\r
+;@RRC H\r
+opcode_CB_0C:\r
+       opRRCH z80hl\r
+;@RRC L\r
+opcode_CB_0D:\r
+       opRRCL z80hl\r
+;@RRC (HL)\r
+opcode_CB_0E :\r
+       readmem8HL\r
+       opRRCb\r
+       writemem8HL\r
+       fetch 15\r
+;@RRC A\r
+opcode_CB_0F:\r
+       opRRCA\r
+\r
+;@RL B\r
+opcode_CB_10:\r
+       opRLH z80bc\r
+;@RL C\r
+opcode_CB_11:\r
+       opRLL z80bc\r
+;@RL D\r
+opcode_CB_12:\r
+       opRLH z80de\r
+;@RL E\r
+opcode_CB_13:\r
+       opRLL z80de\r
+;@RL H\r
+opcode_CB_14:\r
+       opRLH z80hl\r
+;@RL L\r
+opcode_CB_15:\r
+       opRLL z80hl\r
+;@RL (HL)\r
+opcode_CB_16:\r
+       readmem8HL\r
+       opRLb\r
+       writemem8HL\r
+       fetch 15\r
+;@RL A\r
+opcode_CB_17:\r
+       opRLA\r
+\r
+;@RR B \r
+opcode_CB_18:\r
+       opRRH z80bc\r
+;@RR C\r
+opcode_CB_19:\r
+       opRRL z80bc\r
+;@RR D\r
+opcode_CB_1A:\r
+       opRRH z80de\r
+;@RR E\r
+opcode_CB_1B:\r
+       opRRL z80de\r
+;@RR H\r
+opcode_CB_1C:\r
+       opRRH z80hl\r
+;@RR L\r
+opcode_CB_1D:\r
+       opRRL z80hl\r
+;@RR (HL)\r
+opcode_CB_1E:\r
+       readmem8HL\r
+       opRRb\r
+       writemem8HL\r
+       fetch 15\r
+;@RR A\r
+opcode_CB_1F:\r
+       opRRA\r
+\r
+;@SLA B\r
+opcode_CB_20:\r
+       opSLAH z80bc\r
+;@SLA C\r
+opcode_CB_21:\r
+       opSLAL z80bc\r
+;@SLA D\r
+opcode_CB_22:\r
+       opSLAH z80de\r
+;@SLA E\r
+opcode_CB_23:\r
+       opSLAL z80de\r
+;@SLA H\r
+opcode_CB_24:\r
+       opSLAH z80hl\r
+;@SLA L\r
+opcode_CB_25:\r
+       opSLAL z80hl\r
+;@SLA (HL)\r
+opcode_CB_26:\r
+       readmem8HL\r
+       opSLAb\r
+       writemem8HL\r
+       fetch 15\r
+;@SLA A\r
+opcode_CB_27:\r
+       opSLAA\r
+\r
+;@SRA B\r
+opcode_CB_28:\r
+       opSRAH z80bc\r
+;@SRA C\r
+opcode_CB_29:\r
+       opSRAL z80bc\r
+;@SRA D\r
+opcode_CB_2A:\r
+       opSRAH z80de\r
+;@SRA E\r
+opcode_CB_2B:\r
+       opSRAL z80de\r
+;@SRA H\r
+opcode_CB_2C:\r
+       opSRAH z80hl\r
+;@SRA L\r
+opcode_CB_2D:\r
+       opSRAL z80hl\r
+;@SRA (HL)\r
+opcode_CB_2E:\r
+       readmem8HL\r
+       opSRAb\r
+       writemem8HL\r
+       fetch 15\r
+;@SRA A\r
+opcode_CB_2F:\r
+       opSRAA\r
+\r
+;@SLL B\r
+opcode_CB_30:\r
+       opSLLH z80bc\r
+;@SLL C\r
+opcode_CB_31:\r
+       opSLLL z80bc\r
+;@SLL D\r
+opcode_CB_32:\r
+       opSLLH z80de\r
+;@SLL E\r
+opcode_CB_33:\r
+       opSLLL z80de\r
+;@SLL H\r
+opcode_CB_34:\r
+       opSLLH z80hl\r
+;@SLL L\r
+opcode_CB_35:\r
+       opSLLL z80hl\r
+;@SLL (HL)\r
+opcode_CB_36:\r
+       readmem8HL\r
+       opSLLb\r
+       writemem8HL\r
+       fetch 15\r
+;@SLL A\r
+opcode_CB_37:\r
+       opSLLA\r
+\r
+;@SRL B\r
+opcode_CB_38:\r
+       opSRLH z80bc\r
+;@SRL C\r
+opcode_CB_39:\r
+       opSRLL z80bc\r
+;@SRL D\r
+opcode_CB_3A:\r
+       opSRLH z80de\r
+;@SRL E\r
+opcode_CB_3B:\r
+       opSRLL z80de\r
+;@SRL H\r
+opcode_CB_3C:\r
+       opSRLH z80hl\r
+;@SRL L\r
+opcode_CB_3D:\r
+       opSRLL z80hl\r
+;@SRL (HL)\r
+opcode_CB_3E:\r
+       readmem8HL\r
+       opSRLb\r
+       writemem8HL\r
+       fetch 15\r
+;@SRL A\r
+opcode_CB_3F:\r
+       opSRLA\r
+\r
+\r
+;@BIT 0,B\r
+opcode_CB_40:\r
+       opBITH z80bc 0\r
+;@BIT 0,C\r
+opcode_CB_41:\r
+       opBITL z80bc 0\r
+;@BIT 0,D\r
+opcode_CB_42:\r
+       opBITH z80de 0\r
+;@BIT 0,E\r
+opcode_CB_43:\r
+       opBITL z80de 0\r
+;@BIT 0,H\r
+opcode_CB_44:\r
+       opBITH z80hl 0\r
+;@BIT 0,L\r
+opcode_CB_45:\r
+       opBITL z80hl 0\r
+;@BIT 0,(HL)\r
+opcode_CB_46:\r
+       readmem8HL\r
+       opBITb 0\r
+       fetch 12\r
+;@BIT 0,A\r
+opcode_CB_47:\r
+       opBITH z80a 0\r
+\r
+;@BIT 1,B\r
+opcode_CB_48:\r
+       opBITH z80bc 1\r
+;@BIT 1,C\r
+opcode_CB_49:\r
+       opBITL z80bc 1\r
+;@BIT 1,D\r
+opcode_CB_4A:\r
+       opBITH z80de 1\r
+;@BIT 1,E\r
+opcode_CB_4B:\r
+       opBITL z80de 1\r
+;@BIT 1,H\r
+opcode_CB_4C:\r
+       opBITH z80hl 1\r
+;@BIT 1,L\r
+opcode_CB_4D:\r
+       opBITL z80hl 1\r
+;@BIT 1,(HL)\r
+opcode_CB_4E:\r
+       readmem8HL\r
+       opBITb 1\r
+       fetch 12\r
+;@BIT 1,A\r
+opcode_CB_4F:\r
+       opBITH z80a 1\r
+\r
+;@BIT 2,B\r
+opcode_CB_50:\r
+       opBITH z80bc 2\r
+;@BIT 2,C\r
+opcode_CB_51:\r
+       opBITL z80bc 2\r
+;@BIT 2,D\r
+opcode_CB_52:\r
+       opBITH z80de 2\r
+;@BIT 2,E\r
+opcode_CB_53:\r
+       opBITL z80de 2\r
+;@BIT 2,H\r
+opcode_CB_54:\r
+       opBITH z80hl 2\r
+;@BIT 2,L\r
+opcode_CB_55:\r
+       opBITL z80hl 2\r
+;@BIT 2,(HL)\r
+opcode_CB_56:\r
+       readmem8HL\r
+       opBITb 2\r
+       fetch 12\r
+;@BIT 2,A\r
+opcode_CB_57:\r
+       opBITH z80a 2\r
+\r
+;@BIT 3,B\r
+opcode_CB_58:\r
+       opBITH z80bc 3\r
+;@BIT 3,C\r
+opcode_CB_59:\r
+       opBITL z80bc 3\r
+;@BIT 3,D\r
+opcode_CB_5A:\r
+       opBITH z80de 3\r
+;@BIT 3,E\r
+opcode_CB_5B:\r
+       opBITL z80de 3\r
+;@BIT 3,H\r
+opcode_CB_5C:\r
+       opBITH z80hl 3\r
+;@BIT 3,L\r
+opcode_CB_5D:\r
+       opBITL z80hl 3\r
+;@BIT 3,(HL)\r
+opcode_CB_5E:\r
+       readmem8HL\r
+       opBITb 3\r
+       fetch 12\r
+;@BIT 3,A\r
+opcode_CB_5F:\r
+       opBITH z80a 3\r
+\r
+;@BIT 4,B\r
+opcode_CB_60:\r
+       opBITH z80bc 4\r
+;@BIT 4,C\r
+opcode_CB_61:\r
+       opBITL z80bc 4\r
+;@BIT 4,D\r
+opcode_CB_62:\r
+       opBITH z80de 4\r
+;@BIT 4,E\r
+opcode_CB_63:\r
+       opBITL z80de 4\r
+;@BIT 4,H\r
+opcode_CB_64:\r
+       opBITH z80hl 4\r
+;@BIT 4,L\r
+opcode_CB_65:\r
+       opBITL z80hl 4\r
+;@BIT 4,(HL)\r
+opcode_CB_66:\r
+       readmem8HL\r
+       opBITb 4\r
+       fetch 12\r
+;@BIT 4,A\r
+opcode_CB_67:\r
+       opBITH z80a 4\r
+\r
+;@BIT 5,B\r
+opcode_CB_68:\r
+       opBITH z80bc 5\r
+;@BIT 5,C\r
+opcode_CB_69:\r
+       opBITL z80bc 5\r
+;@BIT 5,D\r
+opcode_CB_6A:\r
+       opBITH z80de 5\r
+;@BIT 5,E\r
+opcode_CB_6B:\r
+       opBITL z80de 5\r
+;@BIT 5,H\r
+opcode_CB_6C:\r
+       opBITH z80hl 5\r
+;@BIT 5,L\r
+opcode_CB_6D:\r
+       opBITL z80hl 5\r
+;@BIT 5,(HL)\r
+opcode_CB_6E:\r
+       readmem8HL\r
+       opBITb 5\r
+       fetch 12\r
+;@BIT 5,A\r
+opcode_CB_6F:\r
+       opBITH z80a 5\r
+\r
+;@BIT 6,B\r
+opcode_CB_70:\r
+       opBITH z80bc 6\r
+;@BIT 6,C\r
+opcode_CB_71:\r
+       opBITL z80bc 6\r
+;@BIT 6,D\r
+opcode_CB_72:\r
+       opBITH z80de 6\r
+;@BIT 6,E\r
+opcode_CB_73:\r
+       opBITL z80de 6\r
+;@BIT 6,H\r
+opcode_CB_74:\r
+       opBITH z80hl 6\r
+;@BIT 6,L\r
+opcode_CB_75:\r
+       opBITL z80hl 6\r
+;@BIT 6,(HL)\r
+opcode_CB_76:\r
+       readmem8HL\r
+       opBITb 6\r
+       fetch 12\r
+;@BIT 6,A\r
+opcode_CB_77:\r
+       opBITH z80a 6\r
+\r
+;@BIT 7,B\r
+opcode_CB_78:\r
+       opBIT7H z80bc\r
+;@BIT 7,C\r
+opcode_CB_79:\r
+       opBIT7L z80bc\r
+;@BIT 7,D\r
+opcode_CB_7A:\r
+       opBIT7H z80de\r
+;@BIT 7,E\r
+opcode_CB_7B:\r
+       opBIT7L z80de\r
+;@BIT 7,H\r
+opcode_CB_7C:\r
+       opBIT7H z80hl\r
+;@BIT 7,L\r
+opcode_CB_7D:\r
+       opBIT7L z80hl\r
+;@BIT 7,(HL)\r
+opcode_CB_7E:\r
+       readmem8HL\r
+       opBIT7b\r
+       fetch 12\r
+;@BIT 7,A\r
+opcode_CB_7F:\r
+       opBIT7H z80a\r
+\r
+;@RES 0,B\r
+opcode_CB_80:\r
+       bic z80bc,z80bc,#1<<24\r
+       fetch 8\r
+;@RES 0,C\r
+opcode_CB_81:\r
+       bic z80bc,z80bc,#1<<16\r
+       fetch 8\r
+;@RES 0,D\r
+opcode_CB_82:\r
+       bic z80de,z80de,#1<<24\r
+       fetch 8\r
+;@RES 0,E\r
+opcode_CB_83:\r
+       bic z80de,z80de,#1<<16\r
+       fetch 8\r
+;@RES 0,H\r
+opcode_CB_84:\r
+       bic z80hl,z80hl,#1<<24\r
+       fetch 8\r
+;@RES 0,L\r
+opcode_CB_85:\r
+       bic z80hl,z80hl,#1<<16\r
+       fetch 8\r
+;@RES 0,(HL)\r
+opcode_CB_86:\r
+       opRESmemHL 0\r
+;@RES 0,A\r
+opcode_CB_87:\r
+       bic z80a,z80a,#1<<24\r
+       fetch 8\r
+\r
+;@RES 1,B\r
+opcode_CB_88:\r
+       bic z80bc,z80bc,#1<<25\r
+       fetch 8\r
+;@RES 1,C\r
+opcode_CB_89:\r
+       bic z80bc,z80bc,#1<<17\r
+       fetch 8\r
+;@RES 1,D\r
+opcode_CB_8A:\r
+       bic z80de,z80de,#1<<25\r
+       fetch 8\r
+;@RES 1,E\r
+opcode_CB_8B:\r
+       bic z80de,z80de,#1<<17\r
+       fetch 8\r
+;@RES 1,H\r
+opcode_CB_8C:\r
+       bic z80hl,z80hl,#1<<25\r
+       fetch 8\r
+;@RES 1,L\r
+opcode_CB_8D:\r
+       bic z80hl,z80hl,#1<<17\r
+       fetch 8\r
+;@RES 1,(HL)\r
+opcode_CB_8E:\r
+       opRESmemHL 1\r
+;@RES 1,A\r
+opcode_CB_8F:\r
+       bic z80a,z80a,#1<<25\r
+       fetch 8\r
+\r
+;@RES 2,B\r
+opcode_CB_90:\r
+       bic z80bc,z80bc,#1<<26\r
+       fetch 8\r
+;@RES 2,C\r
+opcode_CB_91:\r
+       bic z80bc,z80bc,#1<<18\r
+       fetch 8\r
+;@RES 2,D\r
+opcode_CB_92:\r
+       bic z80de,z80de,#1<<26\r
+       fetch 8\r
+;@RES 2,E\r
+opcode_CB_93:\r
+       bic z80de,z80de,#1<<18\r
+       fetch 8\r
+;@RES 2,H\r
+opcode_CB_94:\r
+       bic z80hl,z80hl,#1<<26\r
+       fetch 8\r
+;@RES 2,L\r
+opcode_CB_95:\r
+       bic z80hl,z80hl,#1<<18\r
+       fetch 8\r
+;@RES 2,(HL)\r
+opcode_CB_96:\r
+       opRESmemHL 2\r
+;@RES 2,A\r
+opcode_CB_97:\r
+       bic z80a,z80a,#1<<26\r
+       fetch 8\r
+\r
+;@RES 3,B\r
+opcode_CB_98:\r
+       bic z80bc,z80bc,#1<<27\r
+       fetch 8\r
+;@RES 3,C\r
+opcode_CB_99:\r
+       bic z80bc,z80bc,#1<<19\r
+       fetch 8\r
+;@RES 3,D\r
+opcode_CB_9A:\r
+       bic z80de,z80de,#1<<27\r
+       fetch 8\r
+;@RES 3,E\r
+opcode_CB_9B:\r
+       bic z80de,z80de,#1<<19\r
+       fetch 8\r
+;@RES 3,H\r
+opcode_CB_9C:\r
+       bic z80hl,z80hl,#1<<27\r
+       fetch 8\r
+;@RES 3,L\r
+opcode_CB_9D:\r
+       bic z80hl,z80hl,#1<<19\r
+       fetch 8\r
+;@RES 3,(HL)\r
+opcode_CB_9E:\r
+       opRESmemHL 3\r
+;@RES 3,A\r
+opcode_CB_9F:\r
+       bic z80a,z80a,#1<<27\r
+       fetch 8\r
+\r
+;@RES 4,B\r
+opcode_CB_A0:\r
+       bic z80bc,z80bc,#1<<28\r
+       fetch 8\r
+;@RES 4,C\r
+opcode_CB_A1:\r
+       bic z80bc,z80bc,#1<<20\r
+       fetch 8\r
+;@RES 4,D\r
+opcode_CB_A2:\r
+       bic z80de,z80de,#1<<28\r
+       fetch 8\r
+;@RES 4,E\r
+opcode_CB_A3:\r
+       bic z80de,z80de,#1<<20\r
+       fetch 8\r
+;@RES 4,H\r
+opcode_CB_A4:\r
+       bic z80hl,z80hl,#1<<28\r
+       fetch 8\r
+;@RES 4,L\r
+opcode_CB_A5:\r
+       bic z80hl,z80hl,#1<<20\r
+       fetch 8\r
+;@RES 4,(HL)\r
+opcode_CB_A6:\r
+       opRESmemHL 4\r
+;@RES 4,A\r
+opcode_CB_A7:\r
+       bic z80a,z80a,#1<<28\r
+       fetch 8\r
+\r
+;@RES 5,B\r
+opcode_CB_A8:\r
+       bic z80bc,z80bc,#1<<29\r
+       fetch 8\r
+;@RES 5,C\r
+opcode_CB_A9:\r
+       bic z80bc,z80bc,#1<<21\r
+       fetch 8\r
+;@RES 5,D\r
+opcode_CB_AA:\r
+       bic z80de,z80de,#1<<29\r
+       fetch 8\r
+;@RES 5,E\r
+opcode_CB_AB:\r
+       bic z80de,z80de,#1<<21\r
+       fetch 8\r
+;@RES 5,H\r
+opcode_CB_AC:\r
+       bic z80hl,z80hl,#1<<29\r
+       fetch 8\r
+;@RES 5,L\r
+opcode_CB_AD:\r
+       bic z80hl,z80hl,#1<<21\r
+       fetch 8\r
+;@RES 5,(HL)\r
+opcode_CB_AE:\r
+       opRESmemHL 5\r
+;@RES 5,A\r
+opcode_CB_AF:\r
+       bic z80a,z80a,#1<<29\r
+       fetch 8\r
+\r
+;@RES 6,B\r
+opcode_CB_B0:\r
+       bic z80bc,z80bc,#1<<30\r
+       fetch 8\r
+;@RES 6,C\r
+opcode_CB_B1:\r
+       bic z80bc,z80bc,#1<<22\r
+       fetch 8\r
+;@RES 6,D\r
+opcode_CB_B2:\r
+       bic z80de,z80de,#1<<30\r
+       fetch 8\r
+;@RES 6,E\r
+opcode_CB_B3:\r
+       bic z80de,z80de,#1<<22\r
+       fetch 8\r
+;@RES 6,H\r
+opcode_CB_B4:\r
+       bic z80hl,z80hl,#1<<30\r
+       fetch 8\r
+;@RES 6,L\r
+opcode_CB_B5:\r
+       bic z80hl,z80hl,#1<<22\r
+       fetch 8\r
+;@RES 6,(HL)\r
+opcode_CB_B6:\r
+       opRESmemHL 6\r
+;@RES 6,A\r
+opcode_CB_B7:\r
+       bic z80a,z80a,#1<<30\r
+       fetch 8\r
+\r
+;@RES 7,B\r
+opcode_CB_B8:\r
+       bic z80bc,z80bc,#1<<31\r
+       fetch 8\r
+;@RES 7,C\r
+opcode_CB_B9:\r
+       bic z80bc,z80bc,#1<<23\r
+       fetch 8\r
+;@RES 7,D\r
+opcode_CB_BA:\r
+       bic z80de,z80de,#1<<31\r
+       fetch 8\r
+;@RES 7,E\r
+opcode_CB_BB:\r
+       bic z80de,z80de,#1<<23\r
+       fetch 8\r
+;@RES 7,H\r
+opcode_CB_BC:\r
+       bic z80hl,z80hl,#1<<31\r
+       fetch 8\r
+;@RES 7,L\r
+opcode_CB_BD:\r
+       bic z80hl,z80hl,#1<<23\r
+       fetch 8\r
+;@RES 7,(HL)\r
+opcode_CB_BE:\r
+       opRESmemHL 7\r
+;@RES 7,A\r
+opcode_CB_BF:\r
+       bic z80a,z80a,#1<<31\r
+       fetch 8\r
+\r
+;@SET 0,B\r
+opcode_CB_C0:\r
+       orr z80bc,z80bc,#1<<24\r
+       fetch 8\r
+;@SET 0,C\r
+opcode_CB_C1:\r
+       orr z80bc,z80bc,#1<<16\r
+       fetch 8\r
+;@SET 0,D\r
+opcode_CB_C2:\r
+       orr z80de,z80de,#1<<24\r
+       fetch 8\r
+;@SET 0,E\r
+opcode_CB_C3:\r
+       orr z80de,z80de,#1<<16\r
+       fetch 8\r
+;@SET 0,H\r
+opcode_CB_C4:\r
+       orr z80hl,z80hl,#1<<24\r
+       fetch 8\r
+;@SET 0,L\r
+opcode_CB_C5:\r
+       orr z80hl,z80hl,#1<<16\r
+       fetch 8\r
+;@SET 0,(HL)\r
+opcode_CB_C6:\r
+       opSETmemHL 0\r
+;@SET 0,A\r
+opcode_CB_C7:\r
+       orr z80a,z80a,#1<<24\r
+       fetch 8\r
+\r
+;@SET 1,B\r
+opcode_CB_C8:\r
+       orr z80bc,z80bc,#1<<25\r
+       fetch 8\r
+;@SET 1,C\r
+opcode_CB_C9:\r
+       orr z80bc,z80bc,#1<<17\r
+       fetch 8\r
+;@SET 1,D\r
+opcode_CB_CA:\r
+       orr z80de,z80de,#1<<25\r
+       fetch 8\r
+;@SET 1,E\r
+opcode_CB_CB:\r
+       orr z80de,z80de,#1<<17\r
+       fetch 8\r
+;@SET 1,H\r
+opcode_CB_CC:\r
+       orr z80hl,z80hl,#1<<25\r
+       fetch 8\r
+;@SET 1,L\r
+opcode_CB_CD:\r
+       orr z80hl,z80hl,#1<<17\r
+       fetch 8\r
+;@SET 1,(HL)\r
+opcode_CB_CE:\r
+       opSETmemHL 1\r
+;@SET 1,A\r
+opcode_CB_CF:\r
+       orr z80a,z80a,#1<<25\r
+       fetch 8\r
+\r
+;@SET 2,B\r
+opcode_CB_D0:\r
+       orr z80bc,z80bc,#1<<26\r
+       fetch 8\r
+;@SET 2,C\r
+opcode_CB_D1:\r
+       orr z80bc,z80bc,#1<<18\r
+       fetch 8\r
+;@SET 2,D\r
+opcode_CB_D2:\r
+       orr z80de,z80de,#1<<26\r
+       fetch 8\r
+;@SET 2,E\r
+opcode_CB_D3:\r
+       orr z80de,z80de,#1<<18\r
+       fetch 8\r
+;@SET 2,H\r
+opcode_CB_D4:\r
+       orr z80hl,z80hl,#1<<26\r
+       fetch 8\r
+;@SET 2,L\r
+opcode_CB_D5:\r
+       orr z80hl,z80hl,#1<<18\r
+       fetch 8\r
+;@SET 2,(HL)\r
+opcode_CB_D6:\r
+       opSETmemHL 2\r
+;@SET 2,A\r
+opcode_CB_D7:\r
+       orr z80a,z80a,#1<<26\r
+       fetch 8\r
+\r
+;@SET 3,B\r
+opcode_CB_D8:\r
+       orr z80bc,z80bc,#1<<27\r
+       fetch 8\r
+;@SET 3,C\r
+opcode_CB_D9:\r
+       orr z80bc,z80bc,#1<<19\r
+       fetch 8\r
+;@SET 3,D\r
+opcode_CB_DA:\r
+       orr z80de,z80de,#1<<27\r
+       fetch 8\r
+;@SET 3,E\r
+opcode_CB_DB:\r
+       orr z80de,z80de,#1<<19\r
+       fetch 8\r
+;@SET 3,H\r
+opcode_CB_DC:\r
+       orr z80hl,z80hl,#1<<27\r
+       fetch 8\r
+;@SET 3,L\r
+opcode_CB_DD:\r
+       orr z80hl,z80hl,#1<<19\r
+       fetch 8\r
+;@SET 3,(HL)\r
+opcode_CB_DE:\r
+       opSETmemHL 3\r
+;@SET 3,A\r
+opcode_CB_DF:\r
+       orr z80a,z80a,#1<<27\r
+       fetch 8\r
+\r
+;@SET 4,B\r
+opcode_CB_E0:\r
+       orr z80bc,z80bc,#1<<28\r
+       fetch 8\r
+;@SET 4,C\r
+opcode_CB_E1:\r
+       orr z80bc,z80bc,#1<<20\r
+       fetch 8\r
+;@SET 4,D\r
+opcode_CB_E2:\r
+       orr z80de,z80de,#1<<28\r
+       fetch 8\r
+;@SET 4,E\r
+opcode_CB_E3:\r
+       orr z80de,z80de,#1<<20\r
+       fetch 8\r
+;@SET 4,H\r
+opcode_CB_E4:\r
+       orr z80hl,z80hl,#1<<28\r
+       fetch 8\r
+;@SET 4,L\r
+opcode_CB_E5:\r
+       orr z80hl,z80hl,#1<<20\r
+       fetch 8\r
+;@SET 4,(HL)\r
+opcode_CB_E6:\r
+       opSETmemHL 4\r
+;@SET 4,A\r
+opcode_CB_E7:\r
+       orr z80a,z80a,#1<<28\r
+       fetch 8\r
+\r
+;@SET 5,B\r
+opcode_CB_E8:\r
+       orr z80bc,z80bc,#1<<29\r
+       fetch 8\r
+;@SET 5,C\r
+opcode_CB_E9:\r
+       orr z80bc,z80bc,#1<<21\r
+       fetch 8\r
+;@SET 5,D\r
+opcode_CB_EA:\r
+       orr z80de,z80de,#1<<29\r
+       fetch 8\r
+;@SET 5,E\r
+opcode_CB_EB:\r
+       orr z80de,z80de,#1<<21\r
+       fetch 8\r
+;@SET 5,H\r
+opcode_CB_EC:\r
+       orr z80hl,z80hl,#1<<29\r
+       fetch 8\r
+;@SET 5,L\r
+opcode_CB_ED:\r
+       orr z80hl,z80hl,#1<<21\r
+       fetch 8\r
+;@SET 5,(HL)\r
+opcode_CB_EE:\r
+       opSETmemHL 5\r
+;@SET 5,A\r
+opcode_CB_EF:\r
+       orr z80a,z80a,#1<<29\r
+       fetch 8\r
+\r
+;@SET 6,B\r
+opcode_CB_F0:\r
+       orr z80bc,z80bc,#1<<30\r
+       fetch 8\r
+;@SET 6,C\r
+opcode_CB_F1:\r
+       orr z80bc,z80bc,#1<<22\r
+       fetch 8\r
+;@SET 6,D\r
+opcode_CB_F2:\r
+       orr z80de,z80de,#1<<30\r
+       fetch 8\r
+;@SET 6,E\r
+opcode_CB_F3:\r
+       orr z80de,z80de,#1<<22\r
+       fetch 8\r
+;@SET 6,H\r
+opcode_CB_F4:\r
+       orr z80hl,z80hl,#1<<30\r
+       fetch 8\r
+;@SET 6,L\r
+opcode_CB_F5:\r
+       orr z80hl,z80hl,#1<<22\r
+       fetch 8\r
+;@SET 6,(HL)\r
+opcode_CB_F6:\r
+       opSETmemHL 6\r
+;@SET 6,A\r
+opcode_CB_F7:\r
+       orr z80a,z80a,#1<<30\r
+       fetch 8\r
+\r
+;@SET 7,B\r
+opcode_CB_F8:\r
+       orr z80bc,z80bc,#1<<31\r
+       fetch 8\r
+;@SET 7,C\r
+opcode_CB_F9:\r
+       orr z80bc,z80bc,#1<<23\r
+       fetch 8\r
+;@SET 7,D\r
+opcode_CB_FA:\r
+       orr z80de,z80de,#1<<31\r
+       fetch 8\r
+;@SET 7,E\r
+opcode_CB_FB:\r
+       orr z80de,z80de,#1<<23\r
+       fetch 8\r
+;@SET 7,H\r
+opcode_CB_FC:\r
+       orr z80hl,z80hl,#1<<31\r
+       fetch 8\r
+;@SET 7,L\r
+opcode_CB_FD:\r
+       orr z80hl,z80hl,#1<<23\r
+       fetch 8\r
+;@SET 7,(HL)\r
+opcode_CB_FE:\r
+       opSETmemHL 7\r
+;@SET 7,A\r
+opcode_CB_FF:\r
+       orr z80a,z80a,#1<<31\r
+       fetch 8\r
+\r
+\r
+\r
+;@##################################\r
+;@##################################\r
+;@###  opcodes DD  #########################\r
+;@##################################\r
+;@##################################\r
+;@Because the DD opcodes are not a complete range from 00-FF I have\r
+;@created this sub routine that will catch any undocumented ops\r
+;@halt the emulator and mov the current instruction to r0\r
+;@at a later stage I may change to display a text message on the screen\r
+opcode_DD_NF:\r
+       eatcycles 4\r
+       ldr pc,[opcodes,r0, lsl #2]\r
+;@     mov r2,#0x10*4\r
+;@     cmp r2,z80xx\r
+;@     bne opcode_FD_NF\r
+;@     mov r0,#0xDD00\r
+;@     orr r0,r0,r1\r
+;@     b end_loop\r
+;@opcode_FD_NF:\r
+;@     mov r0,#0xFD00\r
+;@     orr r0,r0,r1\r
+;@     b end_loop\r
+opcode_DD_NF2:\r
+       mov r0,#0xDD0000\r
+       orr r0,r0,#0xCB00\r
+       orr r0,r0,r1\r
+       b end_loop\r
+\r
+;@ADD IX,BC\r
+opcode_DD_09:\r
+       ldr r0,[z80xx]\r
+       opADD16 r0 z80bc\r
+       str r0,[z80xx]\r
+       fetch 15\r
+;@ADD IX,DE\r
+opcode_DD_19:\r
+       ldr r0,[z80xx]\r
+       opADD16 r0 z80de\r
+       str r0,[z80xx]\r
+       fetch 15\r
+;@LD IX,NN\r
+opcode_DD_21:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+       orr r0,r0,r1, lsl #8\r
+       strh r0,[z80xx,#2]\r
+       fetch 14\r
+;@LD (NN),IX\r
+opcode_DD_22:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+       orr r1,r0,r1, lsl #8\r
+       ldrh r0,[z80xx,#2]\r
+       writemem16\r
+       fetch 20\r
+;@INC IX\r
+opcode_DD_23:\r
+       ldr r0,[z80xx]\r
+       add r0,r0,#1<<16\r
+       str r0,[z80xx]\r
+       fetch 10\r
+;@INC I  (IX)\r
+opcode_DD_24:\r
+       ldr r0,[z80xx]\r
+       opINC8H r0\r
+       str r0,[z80xx]\r
+       fetch 8\r
+;@DEC I  (IX)\r
+opcode_DD_25:\r
+       ldr r0,[z80xx]\r
+       opDEC8H r0\r
+       str r0,[z80xx]\r
+       fetch 8\r
+;@LD I,N  (IX)\r
+opcode_DD_26:\r
+       ldrb r0,[z80pc],#1\r
+       strb r0,[z80xx,#3]\r
+       fetch 11\r
+;@ADD IX,IX\r
+opcode_DD_29:\r
+       ldr r0,[z80xx]\r
+       opADD16_2 r0\r
+       str r0,[z80xx]\r
+       fetch 15\r
+;@LD IX,(NN)\r
+opcode_DD_2A:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+       orr r0,r0,r1, lsl #8\r
+       stmfd sp!,{z80xx}\r
+       readmem16\r
+       ldmfd sp!,{z80xx}\r
+       strh r0,[z80xx,#2]\r
+       fetch 20\r
+;@DEC IX\r
+opcode_DD_2B:\r
+       ldr r0,[z80xx]\r
+       sub r0,r0,#1<<16\r
+       str r0,[z80xx]\r
+       fetch 10\r
+;@INC X  (IX)\r
+opcode_DD_2C:\r
+       ldr r0,[z80xx]\r
+       opINC8L r0\r
+       str r0,[z80xx]\r
+       fetch 8\r
+;@DEC X  (IX)\r
+opcode_DD_2D:\r
+       ldr r0,[z80xx]\r
+       opDEC8L r0\r
+       str r0,[z80xx]\r
+       fetch 8\r
+;@LD X,N  (IX)\r
+opcode_DD_2E:\r
+       ldrb r0,[z80pc],#1\r
+       strb r0,[z80xx,#2]\r
+       fetch 11\r
+;@INC (IX+N)\r
+opcode_DD_34:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r0,r0,r1, lsr #16\r
+       stmfd sp!,{r0}  ;@ save addr\r
+       readmem8\r
+       opINC8b\r
+       ldmfd sp!,{r1}  ;@ restore addr into r1\r
+       writemem8\r
+       fetch 23\r
+;@DEC (IX+N)\r
+opcode_DD_35:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r0,r0,r1, lsr #16\r
+       stmfd sp!,{r0}  ;@ save addr\r
+       readmem8\r
+       opDEC8b\r
+       ldmfd sp!,{r1}  ;@ restore addr into r1\r
+       writemem8\r
+       fetch 23\r
+;@LD (IX+N),N\r
+opcode_DD_36:\r
+       ldrsb r2,[z80pc],#1\r
+       ldrb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r1,r2,r1, lsr #16\r
+       writemem8\r
+       fetch 19\r
+;@ADD IX,SP\r
+opcode_DD_39:\r
+       ldr r0,[z80xx]\r
+.if FAST_Z80SP\r
+       ldr r2,[cpucontext,#z80sp_base]\r
+       sub r2,z80sp,r2\r
+       opADD16s r0 r2 16\r
+.else\r
+       opADD16s r0 z80sp 16\r
+.endif\r
+       str r0,[z80xx]\r
+       fetch 15\r
+;@LD B,I ( IX )\r
+opcode_DD_44:\r
+       ldrb r0,[z80xx,#3]\r
+       and z80bc,z80bc,#0xFF<<16\r
+       orr z80bc,z80bc,r0, lsl #24\r
+       fetch 8\r
+;@LD B,X ( IX )\r
+opcode_DD_45:\r
+       ldrb r0,[z80xx,#2]\r
+       and z80bc,z80bc,#0xFF<<16\r
+       orr z80bc,z80bc,r0, lsl #24\r
+       fetch 8\r
+;@LD B,(IX,N)\r
+opcode_DD_46:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r0,r0,r1, lsr #16\r
+       readmem8\r
+       and z80bc,z80bc,#0xFF<<16\r
+       orr z80bc,z80bc,r0, lsl #24\r
+       fetch 19\r
+;@LD C,I  (IX)\r
+opcode_DD_4C:\r
+       ldrb r0,[z80xx,#3]\r
+       and z80bc,z80bc,#0xFF<<24\r
+       orr z80bc,z80bc,r0, lsl #16\r
+       fetch 8\r
+;@LD C,X  (IX)\r
+opcode_DD_4D:\r
+       ldrb r0,[z80xx,#2]\r
+       and z80bc,z80bc,#0xFF<<24\r
+       orr z80bc,z80bc,r0, lsl #16\r
+       fetch 8\r
+;@LD C,(IX,N)\r
+opcode_DD_4E:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r0,r0,r1, lsr #16\r
+       readmem8\r
+       and z80bc,z80bc,#0xFF<<24\r
+       orr z80bc,z80bc,r0, lsl #16\r
+       fetch 19\r
+\r
+;@LD D,I  (IX)\r
+opcode_DD_54:\r
+       ldrb r0,[z80xx,#3]\r
+       and z80de,z80de,#0xFF<<16\r
+       orr z80de,z80de,r0, lsl #24\r
+       fetch 8\r
+;@LD D,X  (IX)\r
+opcode_DD_55:\r
+       ldrb r0,[z80xx,#2]\r
+       and z80de,z80de,#0xFF<<16\r
+       orr z80de,z80de,r0, lsl #24\r
+       fetch 8\r
+;@LD D,(IX,N)\r
+opcode_DD_56:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r0,r0,r1, lsr #16\r
+       readmem8\r
+       and z80de,z80de,#0xFF<<16\r
+       orr z80de,z80de,r0, lsl #24\r
+       fetch 19\r
+;@LD E,I  (IX)\r
+opcode_DD_5C:\r
+       ldrb r0,[z80xx,#3]\r
+       and z80de,z80de,#0xFF<<24\r
+       orr z80de,z80de,r0, lsl #16\r
+       fetch 8\r
+;@LD E,X  (IX)\r
+opcode_DD_5D:\r
+       ldrb r0,[z80xx,#2]\r
+       and z80de,z80de,#0xFF<<24\r
+       orr z80de,z80de,r0, lsl #16\r
+       fetch 8\r
+;@LD E,(IX,N)\r
+opcode_DD_5E:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r0,r0,r1, lsr #16\r
+       readmem8\r
+       and z80de,z80de,#0xFF<<24\r
+       orr z80de,z80de,r0, lsl #16\r
+       fetch 19\r
+;@LD I,B  (IX)\r
+opcode_DD_60:\r
+       mov r0,z80bc,lsr#24\r
+       strb r0,[z80xx,#3]\r
+       fetch 8\r
+;@LD I,C  (IX)\r
+opcode_DD_61:\r
+       mov r0,z80bc,lsr#16\r
+       strb r0,[z80xx,#3]\r
+       fetch 8\r
+;@LD I,D  (IX)\r
+opcode_DD_62:\r
+       mov r0,z80de,lsr#24\r
+       strb r0,[z80xx,#3]\r
+       fetch 8\r
+;@LD I,E  (IX)\r
+opcode_DD_63:\r
+       mov r0,z80de,lsr#16\r
+       strb r0,[z80xx,#3]\r
+       fetch 8\r
+;@LD I,I  (IX)\r
+opcode_DD_64:\r
+       fetch 8\r
+;@LD I,X  (IX)\r
+opcode_DD_65:\r
+       ldrb r0,[z80xx,#2]\r
+       strb r0,[z80xx,#3]\r
+       fetch 8\r
+;@LD H,(IX,N)\r
+opcode_DD_66:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r0,r0,r1, lsr #16\r
+       readmem8\r
+       and z80hl,z80hl,#0xFF<<16\r
+       orr z80hl,z80hl,r0, lsl #24\r
+       fetch 19\r
+;@LD I,A  (IX)\r
+opcode_DD_67:\r
+       mov r0,z80a,lsr#24\r
+       strb r0,[z80xx,#3]\r
+       fetch 8\r
+;@LD X,B  (IX)\r
+opcode_DD_68:\r
+       mov r0,z80bc,lsr#24\r
+       strb r0,[z80xx,#2]\r
+       fetch 8\r
+;@LD X,C  (IX)\r
+opcode_DD_69:\r
+       mov r0,z80bc,lsr#16\r
+       strb r0,[z80xx,#2]\r
+       fetch 8\r
+;@LD X,D  (IX)\r
+opcode_DD_6A:\r
+       mov r0,z80de,lsr#24\r
+       strb r0,[z80xx,#2]\r
+       fetch 8\r
+;@LD X,E  (IX)\r
+opcode_DD_6B:\r
+       mov r0,z80de,lsr#16\r
+       strb r0,[z80xx,#2]\r
+       fetch 8\r
+;@LD X,I  (IX)\r
+opcode_DD_6C:\r
+       ldrb r0,[z80xx,#3]\r
+       strb r0,[z80xx,#2]\r
+       fetch 8\r
+;@LD X,X  (IX)\r
+opcode_DD_6D:\r
+       fetch 8\r
+;@LD L,(IX,N)\r
+opcode_DD_6E:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r0,r0,r1, lsr #16\r
+       readmem8\r
+       and z80hl,z80hl,#0xFF<<24\r
+       orr z80hl,z80hl,r0, lsl #16\r
+       fetch 19\r
+;@LD X,A  (IX)\r
+opcode_DD_6F:\r
+       mov r0,z80a,lsr#24\r
+       strb r0,[z80xx,#2]\r
+       fetch 8\r
+\r
+;@LD (IX,N),B\r
+opcode_DD_70:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r1,r0,r1, lsr #16\r
+       mov r0,z80bc, lsr #24\r
+       writemem8\r
+       fetch 19\r
+;@LD (IX,N),C\r
+opcode_DD_71:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r1,r0,r1, lsr #16\r
+       mov r0,z80bc, lsr #16\r
+       and r0,r0,#0xFF\r
+       writemem8\r
+       fetch 19\r
+;@LD (IX,N),D\r
+opcode_DD_72:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r1,r0,r1, lsr #16\r
+       mov r0,z80de, lsr #24\r
+       writemem8\r
+       fetch 19\r
+;@LD (IX,N),E\r
+opcode_DD_73:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r1,r0,r1, lsr #16\r
+       mov r0,z80de, lsr #16\r
+       and r0,r0,#0xFF\r
+       writemem8\r
+       fetch 19\r
+;@LD (IX,N),H\r
+opcode_DD_74:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r1,r0,r1, lsr #16\r
+       mov r0,z80hl, lsr #24\r
+       writemem8\r
+       fetch 19\r
+;@LD (IX,N),L\r
+opcode_DD_75:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r1,r0,r1, lsr #16\r
+       mov r0,z80hl, lsr #16\r
+       and r0,r0,#0xFF\r
+       writemem8\r
+       fetch 19\r
+;@LD (IX,N),A\r
+opcode_DD_77:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r1,r0,r1, lsr #16\r
+       mov r0,z80a, lsr #24\r
+       writemem8\r
+       fetch 19\r
+\r
+;@LD A,I  from (IX)\r
+opcode_DD_7C:\r
+       ldrb r0,[z80xx,#3]\r
+       mov z80a,r0, lsl #24\r
+       fetch 8\r
+;@LD A,X  from (IX)\r
+opcode_DD_7D:\r
+       ldrb r0,[z80xx,#2]\r
+       mov z80a,r0, lsl #24\r
+       fetch 8\r
+;@LD A,(IX,N)\r
+opcode_DD_7E:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r0,r0,r1, lsr #16\r
+       readmem8\r
+       mov z80a,r0, lsl #24\r
+       fetch 19\r
+\r
+;@ADD A,I  ( IX)\r
+opcode_DD_84:\r
+       ldrb r0,[z80xx,#3]\r
+       opADDb\r
+       fetch 8\r
+;@ADD A,X  ( IX)\r
+opcode_DD_85:\r
+       ldrb r0,[z80xx,#2]\r
+       opADDb\r
+       fetch 8\r
+;@ADD A,(IX+N)\r
+opcode_DD_86:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r0,r0,r1, lsr #16\r
+       readmem8\r
+       opADDb\r
+       fetch 19\r
+\r
+;@ADC A,I  (IX)\r
+opcode_DD_8C:\r
+       ldrb r0,[z80xx,#3]\r
+       opADCb\r
+       fetch 8\r
+;@ADC A,X  (IX)\r
+opcode_DD_8D:\r
+       ldrb r0,[z80xx,#2]\r
+       opADCb\r
+       fetch 8\r
+;@ADC A,(IX+N)\r
+opcode_DD_8E:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r0,r0,r1, lsr #16\r
+       readmem8\r
+       opADCb\r
+       fetch 19\r
+\r
+;@SUB A,I  (IX)\r
+opcode_DD_94:\r
+       ldrb r0,[z80xx,#3]\r
+       opSUBb\r
+       fetch 8\r
+;@SUB A,X  (IX)\r
+opcode_DD_95:\r
+       ldrb r0,[z80xx,#2]\r
+       opSUBb\r
+       fetch 8\r
+;@SUB A,(IX+N)\r
+opcode_DD_96:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r0,r0,r1, lsr #16\r
+       readmem8\r
+       opSUBb\r
+       fetch 19\r
+\r
+;@SBC A,I  (IX)\r
+opcode_DD_9C:\r
+       ldrb r0,[z80xx,#3]\r
+       opSBCb\r
+       fetch 8\r
+;@SBC A,X  (IX)\r
+opcode_DD_9D:\r
+       ldrb r0,[z80xx,#2]\r
+       opSBCb\r
+       fetch 8\r
+;@SBC A,(IX+N)\r
+opcode_DD_9E:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r0,r0,r1, lsr #16\r
+       readmem8\r
+       opSBCb\r
+       fetch 19\r
+\r
+;@AND I  (IX)\r
+opcode_DD_A4:\r
+       ldrb r0,[z80xx,#3]\r
+       opANDb\r
+       fetch 8\r
+;@AND X  (IX)\r
+opcode_DD_A5:\r
+       ldrb r0,[z80xx,#2]\r
+       opANDb\r
+       fetch 8\r
+;@AND (IX+N)\r
+opcode_DD_A6:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r0,r0,r1, lsr #16\r
+       readmem8\r
+       opANDb\r
+       fetch 19\r
+\r
+;@XOR I  (IX)\r
+opcode_DD_AC:\r
+       ldrb r0,[z80xx,#3]\r
+       opXORb\r
+       fetch 8\r
+;@XOR X  (IX)\r
+opcode_DD_AD:\r
+       ldrb r0,[z80xx,#2]\r
+       opXORb\r
+       fetch 8\r
+;@XOR (IX+N)\r
+opcode_DD_AE:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r0,r0,r1, lsr #16\r
+       readmem8\r
+       opXORb\r
+       fetch 19\r
+\r
+;@OR I  (IX)\r
+opcode_DD_B4:\r
+       ldrb r0,[z80xx,#3]\r
+       opORb\r
+       fetch 8\r
+;@OR X  (IX)\r
+opcode_DD_B5:\r
+       ldrb r0,[z80xx,#2]\r
+       opORb\r
+       fetch 8\r
+;@OR (IX+N)\r
+opcode_DD_B6:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r0,r0,r1, lsr #16\r
+       readmem8\r
+       opORb\r
+       fetch 19\r
+\r
+;@CP I  (IX)\r
+opcode_DD_BC:\r
+       ldrb r0,[z80xx,#3]\r
+       opCPb\r
+       fetch 8\r
+;@CP X  (IX)\r
+opcode_DD_BD:\r
+       ldrb r0,[z80xx,#2]\r
+       opCPb\r
+       fetch 8\r
+;@CP (IX+N)\r
+opcode_DD_BE:\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r0,r0,r1, lsr #16\r
+       readmem8\r
+       opCPb\r
+       fetch 19\r
+\r
+\r
+opcodes_DD_CB_LOCAL: .word opcodes_DD_CB\r
+opcode_DD_CB:\r
+;@Looks up the opcode on the opcodes_DD_CB table and then \r
+;@moves the PC to the location of the subroutine\r
+       ldrsb r0,[z80pc],#1\r
+       ldr r1,[z80xx]\r
+       add r0,r0,r1, lsr #16\r
+\r
+       ldrb r1,[z80pc],#1\r
+       ldr pc,[pc,r1, lsl #2]\r
+               .word 0x00\r
+opcodes_DD_CB:\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_06,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_0E,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_16,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_1E,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_26,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_2E,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_36,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_3E,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_46,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_4E,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_56,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_5E,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_66,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_6E,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_76,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_7E,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_86,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_8E,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_96,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_9E,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_A6,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_AE,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_B6,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_BE,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_C6,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_CE,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_D6,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_DE,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_E6,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_EE,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_F6,opcode_DD_NF2\r
+               .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_FE,opcode_DD_NF2\r
+\r
+;@RLC (IX+N) \r
+opcode_DD_CB_06:\r
+       stmfd sp!,{r0}          ;@ save addr\r
+       readmem8\r
+       opRLCb\r
+       ldmfd sp!,{r1}          ;@ restore addr into r1\r
+       writemem8\r
+       fetch 23\r
+;@RRC (IX+N) \r
+opcode_DD_CB_0E:\r
+       stmfd sp!,{r0}          ;@ save addr\r
+       readmem8\r
+       opRRCb\r
+       ldmfd sp!,{r1}          ;@ restore addr into r1\r
+       writemem8\r
+       fetch 23\r
+;@RL (IX+N) \r
+opcode_DD_CB_16:\r
+       stmfd sp!,{r0}          ;@ save addr\r
+       readmem8\r
+       opRLb\r
+       ldmfd sp!,{r1}          ;@ restore addr into r1\r
+       writemem8\r
+       fetch 23\r
+;@RR (IX+N) \r
+opcode_DD_CB_1E:\r
+       stmfd sp!,{r0}          ;@ save addr \r
+       readmem8\r
+       opRRb\r
+       ldmfd sp!,{r1}          ;@ restore addr into r1\r
+       writemem8\r
+       fetch 23\r
+\r
+;@SLA (IX+N) \r
+opcode_DD_CB_26:\r
+       stmfd sp!,{r0}          ;@ save addr \r
+       readmem8\r
+       opSLAb\r
+       ldmfd sp!,{r1}          ;@ restore addr into r1\r
+       writemem8\r
+       fetch 23\r
+;@SRA (IX+N) \r
+opcode_DD_CB_2E:\r
+       stmfd sp!,{r0}          ;@ save addr \r
+       readmem8\r
+       opSRAb\r
+       ldmfd sp!,{r1}          ;@ restore addr into r1\r
+       writemem8\r
+       fetch 23\r
+;@SLL (IX+N) \r
+opcode_DD_CB_36:\r
+       stmfd sp!,{r0}          ;@ save addr \r
+       readmem8\r
+       opSLLb\r
+       ldmfd sp!,{r1}          ;@ restore addr into r1\r
+       writemem8\r
+       fetch 23\r
+;@SRL (IX+N)\r
+opcode_DD_CB_3E:\r
+       stmfd sp!,{r0}          ;@ save addr \r
+       readmem8\r
+       opSRLb\r
+       ldmfd sp!,{r1}          ;@ restore addr into r1\r
+       writemem8\r
+       fetch 23\r
+\r
+;@BIT 0,(IX+N) \r
+opcode_DD_CB_46:\r
+       readmem8\r
+       opBITb 0\r
+       fetch 20\r
+;@BIT 1,(IX+N) \r
+opcode_DD_CB_4E:\r
+       readmem8\r
+       opBITb 1\r
+       fetch 20\r
+;@BIT 2,(IX+N) \r
+opcode_DD_CB_56:\r
+       readmem8\r
+       opBITb 2\r
+       fetch 20\r
+;@BIT 3,(IX+N) \r
+opcode_DD_CB_5E:\r
+       readmem8\r
+       opBITb 3\r
+       fetch 20\r
+;@BIT 4,(IX+N) \r
+opcode_DD_CB_66:\r
+       readmem8\r
+       opBITb 4\r
+       fetch 20\r
+;@BIT 5,(IX+N) \r
+opcode_DD_CB_6E:\r
+       readmem8\r
+       opBITb 5\r
+       fetch 20\r
+;@BIT 6,(IX+N) \r
+opcode_DD_CB_76:\r
+       readmem8\r
+       opBITb 6\r
+       fetch 20\r
+;@BIT 7,(IX+N) \r
+opcode_DD_CB_7E:\r
+       readmem8\r
+       opBIT7b\r
+       fetch 20\r
+;@RES 0,(IX+N) \r
+opcode_DD_CB_86:\r
+       opRESmem 0\r
+;@RES 1,(IX+N) \r
+opcode_DD_CB_8E:\r
+       opRESmem 1\r
+;@RES 2,(IX+N) \r
+opcode_DD_CB_96:\r
+       opRESmem 2\r
+;@RES 3,(IX+N) \r
+opcode_DD_CB_9E:\r
+       opRESmem 3\r
+;@RES 4,(IX+N) \r
+opcode_DD_CB_A6:\r
+       opRESmem 4\r
+;@RES 5,(IX+N) \r
+opcode_DD_CB_AE:\r
+       opRESmem 5\r
+;@RES 6,(IX+N) \r
+opcode_DD_CB_B6:\r
+       opRESmem 6\r
+;@RES 7,(IX+N) \r
+opcode_DD_CB_BE:\r
+       opRESmem 7\r
+\r
+;@SET 0,(IX+N) \r
+opcode_DD_CB_C6:\r
+       opSETmem 0\r
+;@SET 1,(IX+N) \r
+opcode_DD_CB_CE:\r
+       opSETmem 1\r
+;@SET 2,(IX+N) \r
+opcode_DD_CB_D6:\r
+       opSETmem 2\r
+;@SET 3,(IX+N) \r
+opcode_DD_CB_DE:\r
+       opSETmem 3\r
+;@SET 4,(IX+N) \r
+opcode_DD_CB_E6:\r
+       opSETmem 4\r
+;@SET 5,(IX+N) \r
+opcode_DD_CB_EE:\r
+       opSETmem 5\r
+;@SET 6,(IX+N) \r
+opcode_DD_CB_F6:\r
+       opSETmem 6\r
+;@SET 7,(IX+N) \r
+opcode_DD_CB_FE:\r
+       opSETmem 7\r
+\r
+\r
+\r
+;@POP IX\r
+opcode_DD_E1:\r
+.if FAST_Z80SP\r
+       opPOP\r
+.else\r
+       mov r0,z80sp\r
+       stmfd sp!,{z80xx}\r
+       readmem16\r
+       ldmfd sp!,{z80xx}\r
+       add z80sp,z80sp,#2\r
+.endif\r
+       strh r0,[z80xx,#2]\r
+       fetch 14\r
+;@EX (SP),IX\r
+opcode_DD_E3:\r
+.if FAST_Z80SP\r
+       ldrb r0,[z80sp]\r
+       ldrb r1,[z80sp,#1]\r
+       orr r2,r0,r1, lsl #8\r
+       ldrh r1,[z80xx,#2]\r
+       mov r0,r1, lsr #8\r
+       strb r0,[z80sp,#1]\r
+       strb r1,[z80sp]\r
+       strh r2,[z80xx,#2]\r
+.else\r
+       mov r0,z80sp\r
+       stmfd sp!,{z80xx}\r
+       readmem16\r
+       ldmfd sp!,{z80xx}\r
+       mov r2,r0\r
+       ldrh r0,[z80xx,#2]\r
+       strh r2,[z80xx,#2]\r
+       mov r1,z80sp\r
+       writemem16\r
+.endif\r
+       fetch 23\r
+;@PUSH IX\r
+opcode_DD_E5:\r
+       ldr r2,[z80xx]\r
+       opPUSHreg r2\r
+       fetch 15\r
+;@JP (IX)\r
+opcode_DD_E9:\r
+       ldrh r0,[z80xx,#2]\r
+       rebasepc\r
+       fetch 8\r
+;@LD SP,IX\r
+opcode_DD_F9:\r
+.if FAST_Z80SP\r
+       ldrh r0,[z80xx,#2]\r
+       rebasesp\r
+       mov z80sp,r0\r
+.else\r
+       ldrh z80sp,[z80xx,#2]\r
+.endif\r
+       fetch 10\r
+\r
+;@##################################\r
+;@##################################\r
+;@###  opcodes ED  #########################\r
+;@##################################\r
+;@##################################\r
+\r
+opcode_ED_NF:\r
+       fetch 8\r
+;@     ldrb r0,[z80pc],#1\r
+;@     ldr pc,[opcodes,r0, lsl #2]\r
+;@     mov r0,#0xED00\r
+;@     orr r0,r0,r1\r
+;@     b end_loop\r
+\r
+;@IN B,(C)\r
+opcode_ED_40:\r
+       opIN_C\r
+       and z80bc,z80bc,#0xFF<<16\r
+       orr z80bc,z80bc,r0, lsl #24\r
+       sub r1,opcodes,#0x100\r
+       ldrb r0,[r1,r0]\r
+       and z80f,z80f,#1<<CFlag\r
+       orr z80f,z80f,r0\r
+       fetch 12\r
+;@OUT (C),B\r
+opcode_ED_41:\r
+       mov r1,z80bc, lsr #24\r
+       opOUT_C\r
+       fetch 12\r
+\r
+;@SBC HL,BC\r
+opcode_ED_42:\r
+       opSBC16 z80bc\r
+\r
+;@LD (NN),BC\r
+opcode_ED_43:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+       orr r1,r0,r1, lsl #8\r
+       mov r0,z80bc, lsr #16\r
+       writemem16\r
+       fetch 20\r
+;@NEG\r
+opcode_ED_44:\r
+       rsbs z80a,z80a,#0\r
+       mrs z80f,cpsr\r
+       mov z80f,z80f,lsr#28                                    ;@S,Z,V&C\r
+       eor z80f,z80f,#(1<<CFlag)|(1<<NFlag)    ;@invert C and set n.\r
+       tst z80a,#0x0F000000                                    ;@H, correct\r
+       orrne z80f,z80f,#1<<HFlag\r
+       fetch 8\r
+ \r
+;@RETN, moved to ED_4D\r
+;@opcode_ED_45:\r
+\r
+;@IM 0\r
+opcode_ED_46:\r
+       strb z80a,[cpucontext,#z80im]\r
+       fetch 8\r
+;@LD I,A\r
+opcode_ED_47:\r
+       str z80a,[cpucontext,#z80i]\r
+       fetch 9\r
+;@IN C,(C)\r
+opcode_ED_48:\r
+       opIN_C\r
+       and z80bc,z80bc,#0xFF<<24\r
+       orr z80bc,z80bc,r0, lsl #16\r
+       sub r1,opcodes,#0x100\r
+       ldrb r0,[r1,r0]\r
+       and z80f,z80f,#1<<CFlag\r
+       orr z80f,z80f,r0\r
+       fetch 12\r
+;@OUT (C),C\r
+opcode_ED_49:\r
+       mov r0,z80bc, lsr #16\r
+       and r1,r0,#0xFF\r
+       opOUT\r
+       fetch 12\r
+;@ADC HL,BC\r
+opcode_ED_4A:\r
+       opADC16 z80bc\r
+;@LD BC,(NN)\r
+opcode_ED_4B:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+       orr r0,r0,r1, lsl #8\r
+       readmem16\r
+       mov z80bc,r0, lsl #16\r
+       fetch 20\r
+\r
+;@RETN\r
+opcode_ED_45:\r
+;@RETI\r
+opcode_ED_4D:\r
+       ldrb r0,[cpucontext,#z80if]\r
+       tst r0,#Z80_IF2\r
+       orrne r0,r0,#Z80_IF1\r
+       biceq r0,r0,#Z80_IF1\r
+       strb r0,[cpucontext,#z80if]\r
+    opPOP\r
+       rebasepc\r
+       fetch 14\r
+\r
+;@LD R,A\r
+opcode_ED_4F:\r
+       mov r0,z80a,lsr#24\r
+       strb r0,[cpucontext,#z80r]\r
+       fetch 9\r
+\r
+;@IN D,(C)\r
+opcode_ED_50:\r
+       opIN_C\r
+       and z80de,z80de,#0xFF<<16\r
+       orr z80de,z80de,r0, lsl #24\r
+       sub r1,opcodes,#0x100\r
+       ldrb r0,[r1,r0]\r
+       and z80f,z80f,#1<<CFlag\r
+       orr z80f,z80f,r0\r
+       fetch 12\r
+;@OUT (C),D\r
+opcode_ED_51:\r
+       mov r1,z80de, lsr #24\r
+       opOUT_C\r
+       fetch 12\r
+;@SBC HL,DE\r
+opcode_ED_52:\r
+       opSBC16 z80de\r
+;@LD (NN),DE\r
+opcode_ED_53:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+       orr r1,r0,r1, lsl #8\r
+       mov r0,z80de, lsr #16\r
+       writemem16\r
+       fetch 20\r
+;@IM 1\r
+opcode_ED_56:\r
+       mov r0,#1\r
+       strb r0,[cpucontext,#z80im]\r
+       fetch 8\r
+;@LD A,I\r
+opcode_ED_57:\r
+       ldr z80a,[cpucontext,#z80i]\r
+       tst z80a,#0xFF000000\r
+       and z80f,z80f,#(1<<CFlag)\r
+       orreq z80f,z80f,#(1<<ZFlag)\r
+       orrmi z80f,z80f,#(1<<SFlag)\r
+       ldrb r0,[cpucontext,#z80if]\r
+       tst r0,#Z80_IF2\r
+       orrne z80f,z80f,#(1<<VFlag)\r
+       fetch 9\r
+;@IN E,(C)\r
+opcode_ED_58:\r
+       opIN_C\r
+       and z80de,z80de,#0xFF<<24\r
+       orr z80de,z80de,r0, lsl #16\r
+       sub r1,opcodes,#0x100\r
+       ldrb r0,[r1,r0]\r
+       and z80f,z80f,#1<<CFlag\r
+       orr z80f,z80f,r0\r
+       fetch 12\r
+;@OUT (C),E\r
+opcode_ED_59:\r
+       mov r1,z80de, lsr #16\r
+       and r1,r1,#0xFF\r
+       opOUT_C\r
+       fetch 12\r
+;@ADC HL,DE\r
+opcode_ED_5A:\r
+       opADC16 z80de\r
+;@LD DE,(NN)\r
+opcode_ED_5B:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+       orr r0,r0,r1, lsl #8\r
+       readmem16\r
+       mov z80de,r0, lsl #16\r
+       fetch 20\r
+;@IM 2\r
+opcode_ED_5E:\r
+       mov r0,#2\r
+       strb r0,[cpucontext,#z80im]\r
+       fetch 8\r
+;@LD A,R\r
+opcode_ED_5F:\r
+       ldrb r0,[cpucontext,#z80r]\r
+       and r0,r0,#0x80\r
+       rsb r1,z80_icount,#0\r
+       and r1,r1,#0x7F\r
+       orr r0,r0,r1\r
+       movs z80a,r0, lsl #24\r
+       and z80f,z80f,#1<<CFlag\r
+       orrmi z80f,z80f,#(1<<SFlag)\r
+       orreq z80f,z80f,#(1<<ZFlag)\r
+       ldrb r0,[cpucontext,#z80if]\r
+       tst r0,#Z80_IF2\r
+       orrne z80f,z80f,#(1<<VFlag)\r
+       fetch 9\r
+;@IN H,(C)\r
+opcode_ED_60:\r
+       opIN_C\r
+       and z80hl,z80hl,#0xFF<<16\r
+       orr z80hl,z80hl,r0, lsl #24\r
+       sub r1,opcodes,#0x100\r
+       ldrb r0,[r1,r0]\r
+       and z80f,z80f,#1<<CFlag\r
+       orr z80f,z80f,r0\r
+       fetch 12\r
+;@OUT (C),H\r
+opcode_ED_61:\r
+       mov r1,z80hl, lsr #24\r
+       opOUT_C\r
+       fetch 12\r
+;@SBC HL,HL\r
+opcode_ED_62:\r
+       opSBC16HL\r
+;@RRD\r
+opcode_ED_67:\r
+       readmem8HL\r
+       mov r1,r0,ror#4\r
+       orr r0,r1,z80a,lsr#20\r
+       bic z80a,z80a,#0x0F000000\r
+       orr z80a,z80a,r1,lsr#4\r
+       writemem8HL\r
+       sub r1,opcodes,#0x100\r
+       ldrb r0,[r1,z80a, lsr #24]\r
+       and z80f,z80f,#1<<CFlag\r
+       orr z80f,z80f,r0\r
+       fetch 18\r
+;@IN L,(C)\r
+opcode_ED_68:\r
+       opIN_C\r
+       and z80hl,z80hl,#0xFF<<24\r
+       orr z80hl,z80hl,r0, lsl #16\r
+       and z80f,z80f,#1<<CFlag\r
+       sub r1,opcodes,#0x100\r
+       ldrb r0,[r1,r0]\r
+       orr z80f,z80f,r0\r
+       fetch 12\r
+;@OUT (C),L\r
+opcode_ED_69:\r
+       mov r1,z80hl, lsr #16\r
+       and r1,r1,#0xFF\r
+       opOUT_C\r
+       fetch 12\r
+;@ADC HL,HL\r
+opcode_ED_6A:\r
+       opADC16HL\r
+;@RLD\r
+opcode_ED_6F:\r
+       readmem8HL\r
+       orr r0,r0,z80a,lsl#4\r
+       mov r0,r0,ror#28\r
+       and z80a,z80a,#0xF0000000\r
+       orr z80a,z80a,r0,lsl#16\r
+       and z80a,z80a,#0xFF000000\r
+       writemem8HL\r
+       sub r1,opcodes,#0x100\r
+       ldrb r0,[r1,z80a, lsr #24]\r
+       and z80f,z80f,#1<<CFlag\r
+       orr z80f,z80f,r0\r
+       fetch 18\r
+;@IN F,(C)\r
+opcode_ED_70:\r
+       opIN_C\r
+       and z80f,z80f,#1<<CFlag\r
+       sub r1,opcodes,#0x100\r
+       ldrb r0,[r1,r0]\r
+       orr z80f,z80f,r0\r
+       fetch 12\r
+;@OUT (C),0\r
+opcode_ED_71:\r
+       mov r1,#0\r
+       opOUT_C\r
+       fetch 12\r
+\r
+;@SBC HL,SP\r
+opcode_ED_72:\r
+.if FAST_Z80SP\r
+       ldr r0,[cpucontext,#z80sp_base]\r
+       sub r0,z80sp,r0\r
+       mov r0, r0, lsl #16\r
+.else\r
+       mov r0,z80sp,lsl#16\r
+.endif\r
+       opSBC16 r0\r
+;@LD (NN),SP\r
+opcode_ED_73:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+       orr r1,r0,r1, lsl #8\r
+.if FAST_Z80SP\r
+       ldr r0,[cpucontext,#z80sp_base]\r
+       sub r0,z80sp,r0\r
+.else\r
+       mov r0,z80sp\r
+.endif\r
+       writemem16\r
+       fetch 16\r
+;@IN A,(C)\r
+opcode_ED_78:\r
+       opIN_C\r
+       mov z80a,r0, lsl #24\r
+       and z80f,z80f,#1<<CFlag\r
+       sub r1,opcodes,#0x100\r
+       ldrb r0,[r1,r0]\r
+       orr z80f,z80f,r0\r
+       fetch 12\r
+;@OUT (C),A\r
+opcode_ED_79:\r
+       mov r1,z80a, lsr #24\r
+       opOUT_C\r
+       fetch 12\r
+;@ADC HL,SP\r
+opcode_ED_7A:\r
+.if FAST_Z80SP\r
+       ldr r0,[cpucontext,#z80sp_base]\r
+       sub r0,z80sp,r0\r
+       mov r0, r0, lsl #16\r
+.else\r
+       mov r0,z80sp,lsl#16\r
+.endif\r
+       opADC16 r0\r
+;@LD SP,(NN)\r
+opcode_ED_7B:\r
+       ldrb r0,[z80pc],#1\r
+       ldrb r1,[z80pc],#1\r
+       orr r0,r0,r1, lsl #8\r
+       readmem16\r
+.if FAST_Z80SP\r
+       rebasesp\r
+.endif\r
+       mov z80sp,r0\r
+       fetch 20\r
+;@LDI\r
+opcode_ED_A0:\r
+       copymem8HL_DE\r
+       add z80hl,z80hl,#1<<16\r
+       add z80de,z80de,#1<<16\r
+       subs z80bc,z80bc,#1<<16\r
+       bic z80f,z80f,#(1<<VFlag)|(1<<NFlag)|(1<<HFlag)\r
+       orrne z80f,z80f,#1<<VFlag\r
+       fetch 16\r
+;@CPI\r
+opcode_ED_A1:\r
+       readmem8HL\r
+       add z80hl,z80hl,#0x00010000\r
+       mov r1,z80a,lsl#4\r
+       cmp z80a,r0,lsl#24\r
+       and z80f,z80f,#1<<CFlag\r
+       orr z80f,z80f,#1<<NFlag\r
+       orrmi z80f,z80f,#1<<SFlag\r
+       orreq z80f,z80f,#1<<ZFlag\r
+       cmp r1,r0,lsl#28\r
+       orrcc z80f,z80f,#1<<HFlag\r
+       subs z80bc,z80bc,#0x00010000\r
+       orrne z80f,z80f,#1<<VFlag\r
+       fetch 16\r
+;@INI\r
+opcode_ED_A2:\r
+       opIN_C\r
+       and z80f,r0,#0x80\r
+       mov z80f,z80f,lsr#2                                             ;@NFlag set by bit 7\r
+;@     mov r1,z80bc,lsl#8\r
+;@     add r1,r1,#0x01000000\r
+;@     adds r1,r1,r0,lsl#24\r
+;@     orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag)  ;@ CF & HF set if (HL) + ((C+1) & 0xFF) > 0xFF\r
+       writemem8HL\r
+       add z80hl,z80hl,#1<<16\r
+       sub z80bc,z80bc,#1<<24\r
+       tst z80bc,#0xFF<<24\r
+       orrmi z80f,z80f,#1<<SFlag\r
+       orreq z80f,z80f,#1<<ZFlag\r
+       fetch 16\r
+\r
+;@OUTI\r
+opcode_ED_A3:\r
+       readmem8HL\r
+       add z80hl,z80hl,#1<<16\r
+       and z80f,r0,#0x80\r
+       mov z80f,z80f,lsr#2                                             ;@NFlag set by bit 7\r
+       mov r1,z80hl,lsl#8\r
+       adds r1,r1,r0,lsl#24\r
+       orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag)  ;@ CF & HF set if (HL)+L > 0xFF\r
+       sub z80bc,z80bc,#1<<24\r
+       tst z80bc,#0xFF<<24\r
+       orrmi z80f,z80f,#1<<SFlag\r
+       orreq z80f,z80f,#1<<ZFlag\r
+       mov r1,r0\r
+       opOUT_C\r
+       fetch 16\r
+\r
+;@LDD\r
+opcode_ED_A8:\r
+       copymem8HL_DE\r
+       sub z80hl,z80hl,#1<<16\r
+       sub z80de,z80de,#1<<16\r
+       subs z80bc,z80bc,#1<<16\r
+       bic z80f,z80f,#(1<<VFlag)|(1<<NFlag)|(1<<HFlag)\r
+       orrne z80f,z80f,#1<<VFlag\r
+       fetch 16\r
+\r
+;@CPD\r
+opcode_ED_A9:\r
+       readmem8HL\r
+       sub z80hl,z80hl,#1<<16\r
+       mov r1,z80a,lsl#4\r
+       cmp z80a,r0,lsl#24\r
+       and z80f,z80f,#1<<CFlag\r
+       orr z80f,z80f,#1<<NFlag\r
+       orrmi z80f,z80f,#1<<SFlag\r
+       orreq z80f,z80f,#1<<ZFlag\r
+       cmp r1,r0,lsl#28\r
+       orrcc z80f,z80f,#1<<HFlag\r
+       subs z80bc,z80bc,#0x00010000\r
+       orrne z80f,z80f,#1<<VFlag\r
+       fetch 16\r
+\r
+;@IND\r
+opcode_ED_AA:\r
+       opIN_C\r
+       and z80f,r0,#0x80\r
+       mov z80f,z80f,lsr#2                                             ;@NFlag set by bit 7\r
+;@     mov r1,z80bc,lsl#8\r
+;@     sub r1,r1,#0x01000000\r
+;@     adds r1,r1,r0,lsl#24\r
+;@     orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag)  ;@ CF & HF set if (HL) + ((C-1) & 0xFF) > 0xFF\r
+       writemem8HL\r
+       sub z80hl,z80hl,#1<<16\r
+       sub z80bc,z80bc,#1<<24\r
+       tst z80bc,#0xFF<<24\r
+       orrmi z80f,z80f,#1<<SFlag\r
+       orreq z80f,z80f,#1<<ZFlag\r
+       fetch 16\r
+\r
+;@OUTD\r
+opcode_ED_AB:\r
+       readmem8HL\r
+       sub z80hl,z80hl,#1<<16\r
+       and z80f,r0,#0x80\r
+       mov z80f,z80f,lsr#2                                             ;@NFlag set by bit 7\r
+       mov r1,z80hl,lsl#8\r
+       adds r1,r1,r0,lsl#24\r
+       orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag)  ;@ CF & HF set if r0+HL > 0xFF\r
+       sub z80bc,z80bc,#1<<24\r
+       tst z80bc,#0xFF<<24\r
+       orrmi z80f,z80f,#1<<SFlag\r
+       orreq z80f,z80f,#1<<ZFlag\r
+       mov r1,r0\r
+       opOUT_C\r
+       fetch 16\r
+;@LDIR\r
+opcode_ED_B0:\r
+       copymem8HL_DE\r
+       add z80hl,z80hl,#1<<16\r
+       add z80de,z80de,#1<<16\r
+       subs z80bc,z80bc,#1<<16\r
+       bic z80f,z80f,#(1<<VFlag)|(1<<NFlag)|(1<<HFlag)\r
+       orrne z80f,z80f,#1<<VFlag\r
+       subne z80pc,z80pc,#2\r
+       subne z80_icount,z80_icount,#5\r
+       fetch 16\r
+\r
+;@CPIR\r
+opcode_ED_B1:\r
+       readmem8HL\r
+       add z80hl,z80hl,#1<<16    \r
+       mov r1,z80a,lsl#4\r
+       cmp z80a,r0,lsl#24\r
+       and z80f,z80f,#1<<CFlag\r
+       orr z80f,z80f,#1<<NFlag\r
+       orrmi z80f,z80f,#1<<SFlag\r
+       orreq z80f,z80f,#1<<ZFlag\r
+       cmp r1,r0,lsl#28\r
+       orrcc z80f,z80f,#1<<HFlag\r
+       subs z80bc,z80bc,#1<<16\r
+       bne opcode_ED_B1_decpc\r
+       fetch 16\r
+opcode_ED_B1_decpc:\r
+       orr z80f,z80f,#1<<VFlag\r
+       tst z80f,#1<<ZFlag\r
+       subeq z80pc,z80pc,#2\r
+       subeq z80_icount,z80_icount,#5\r
+       fetch 16\r
+;@INIR\r
+opcode_ED_B2:\r
+       opIN_C\r
+       and z80f,r0,#0x80\r
+       mov z80f,z80f,lsr#2                                             ;@NFlag set by bit 7\r
+;@     mov r1,z80bc,lsl#8\r
+;@     add r1,r1,#0x01000000\r
+;@     adds r1,r1,r0,lsl#24\r
+;@     orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag)  ;@ CF & HF set if (HL) + ((C+1) & 0xFF) > 0xFF\r
+       writemem8HL\r
+       add z80hl,z80hl,#1<<16\r
+       sub z80bc,z80bc,#1<<24\r
+       tst z80bc,#0xFF<<24\r
+       orrmi z80f,z80f,#1<<SFlag\r
+       orreq z80f,z80f,#1<<ZFlag\r
+       subne z80pc,z80pc,#2\r
+       subne z80_icount,z80_icount,#5\r
+       fetch 16\r
+;@OTIR\r
+opcode_ED_B3:\r
+       readmem8HL\r
+       add z80hl,z80hl,#1<<16\r
+       and z80f,r0,#0x80\r
+       mov z80f,z80f,lsr#2                                             ;@NFlag set by bit 7\r
+       mov r1,z80hl,lsl#8\r
+       adds r1,r1,r0,lsl#24\r
+       orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag)  ;@ CF & HF set if r0+HL > 0xFF\r
+       sub z80bc,z80bc,#1<<24\r
+       tst z80bc,#0xFF<<24\r
+       orrmi z80f,z80f,#1<<SFlag\r
+       orreq z80f,z80f,#1<<ZFlag\r
+       subne z80pc,z80pc,#2\r
+       subne z80_icount,z80_icount,#5\r
+       mov r1,r0\r
+       opOUT_C\r
+       fetch 16\r
+;@LDDR\r
+opcode_ED_B8:\r
+       copymem8HL_DE\r
+       sub z80hl,z80hl,#1<<16\r
+       sub z80de,z80de,#1<<16\r
+       subs z80bc,z80bc,#1<<16\r
+       bic z80f,z80f,#(1<<VFlag)|(1<<NFlag)|(1<<HFlag)\r
+       orrne z80f,z80f,#1<<VFlag\r
+       subne z80pc,z80pc,#2\r
+       subne z80_icount,z80_icount,#5\r
+       fetch 16\r
+\r
+;@CPDR\r
+opcode_ED_B9:\r
+       readmem8HL\r
+       sub z80hl,z80hl,#1<<16\r
+       mov r1,z80a,lsl#4\r
+       cmp z80a,r0,lsl#24\r
+       and z80f,z80f,#1<<CFlag\r
+       orr z80f,z80f,#1<<NFlag\r
+       orrmi z80f,z80f,#1<<SFlag\r
+       orreq z80f,z80f,#1<<ZFlag\r
+       cmp r1,r0,lsl#28\r
+       orrcc z80f,z80f,#1<<HFlag\r
+       subs z80bc,z80bc,#1<<16\r
+       bne opcode_ED_B9_decpc\r
+       fetch 16\r
+opcode_ED_B9_decpc:\r
+       orr z80f,z80f,#1<<VFlag\r
+       tst z80f,#1<<ZFlag\r
+       subeq z80pc,z80pc,#2\r
+       subeq z80_icount,z80_icount,#5\r
+       fetch 16\r
+;@INDR\r
+opcode_ED_BA:\r
+       opIN_C\r
+       and z80f,r0,#0x80\r
+       mov z80f,z80f,lsr#2                                             ;@NFlag set by bit 7\r
+;@     mov r1,z80bc,lsl#8\r
+;@     sub r1,r1,#0x01000000\r
+;@     adds r1,r1,r0,lsl#24\r
+;@     orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag)  ;@ CF & HF set if (HL) + ((C-1) & 0xFF) > 0xFF\r
+       writemem8HL\r
+       sub z80hl,z80hl,#1<<16\r
+       sub z80bc,z80bc,#1<<24\r
+       tst z80bc,#0xFF<<24\r
+       orrmi z80f,z80f,#1<<SFlag\r
+       orreq z80f,z80f,#1<<ZFlag\r
+       subne z80pc,z80pc,#2\r
+       subne z80_icount,z80_icount,#5\r
+       fetch 16\r
+;@OTDR\r
+opcode_ED_BB:\r
+       readmem8HL\r
+       sub z80hl,z80hl,#1<<16\r
+       and z80f,r0,#0x80\r
+       mov z80f,z80f,lsr#2                                             ;@NFlag set by bit 7\r
+       mov r1,z80hl,lsl#8\r
+       adds r1,r1,r0,lsl#24\r
+       orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag)  ;@ CF & HF set if r0+HL > 0xFF\r
+       sub z80bc,z80bc,#1<<24\r
+       tst z80bc,#0xFF<<24\r
+       orrmi z80f,z80f,#1<<SFlag\r
+       orreq z80f,z80f,#1<<ZFlag\r
+       subne z80pc,z80pc,#2\r
+       subne z80_icount,z80_icount,#5\r
+       mov r1,r0\r
+       opOUT_C\r
+       fetch 16\r
+;@##################################\r
+;@##################################\r
+;@###  opcodes FD  #########################\r
+;@##################################\r
+;@##################################\r
+;@Since DD and FD opcodes are all the same apart from the address\r
+;@register they use.  When a FD intruction the program runs the code\r
+;@from the DD location but the address of the IY reg is passed instead\r
+;@of IX\r
+\r
+end_loop:\r
+     b end_loop\r
+\r
+\r
+\r
fast MegaDrive/MegaCD/32X emulator