--- /dev/null
+/*---------------------------------------------------------------\r
+ * Motorola 68000 32 Bit emulator\r
+ *\r
+ * Copyright 1998-2001 Mike Coates, All rights reserved\r
+ * Darren Olafson\r
+ *---------------------------------------------------------------\r
+ *\r
+ * Thanks to ...\r
+ *\r
+ * Neil Bradley (lots of optimisation help & ideas)\r
+ *\r
+ *---------------------------------------------------------------\r
+ * History (so we know what bugs have been fixed)\r
+ *\r
+ * 02.11.98 MJC - CMPM bug, overwriting first value\r
+ * 04.11.98 MJC - Debug timing - same as C core\r
+ * save PC on calls to C memory routines\r
+ * 05.11.98 NS - Re-insert changes to make work on OS/2\r
+ * 06.11.98 MJC - Flags saved on ADDA commands\r
+ * X set on ADD commands\r
+ * 23.11.98 MJC - Alternate Memory Read/Write for non DOS ports\r
+ * 24.11.98 CK - Add WIN32 specific stuff\r
+ * 25.11.98 DEO - ABCD Size not initialised\r
+ * 21.12.98 MJC - Change register saving on Memory Banking\r
+ * 13.01.99 M/D - Change to new C core disassembler\r
+ * 19.01.99 MJC - Proper? support for new Interrupt System\r
+ * 17.02.99 MJC - TRACE68K define added\r
+ * ABCD,SBCD not keeping Z flag\r
+ * JMP, JSR for some EA combo's damaging flags\r
+ * DIVU - Overflow not being set correctly\r
+ * ASL/ASR - Flag Handling now correct\r
+ * some minor optimisations\r
+ * 13.03.99 DEO - Added new cycle timing\r
+ * 24.03.99 MJC - TRACE68K define removed\r
+ * NEW INTERRUPT SYSTEM only\r
+ * interrupt check sped up (when not taken)\r
+ * STOP checks for interrupt\r
+ * 01.04.99 MJC - OS2 specifics added\r
+ * MOVEM reference point moved\r
+ * Data and Address register mode combined for :-\r
+ * movecodes\r
+ * dumpx\r
+ * 04.05.99 MJC - Add Previous PC support to MOVE.B #X,XXXXXX.L (F1 Dream)\r
+ * ABCD/SBCD could corrupt zero flag\r
+ * DIVS/DIVU overflow should not update register\r
+ * 22.05.99 MJC - Complete support of Previous PC on C calls\r
+ * Some optional bits now selected by DEFINES\r
+ * 27.05.99 MJC - Interrupt system changed\r
+ * 28.05.99 MJC - Use DEFINES in more places\r
+ * Interrupt check running one opcode when taken\r
+ * 16.07.99 MJC - Reset - Preload next opcode / external call\r
+ * 68010 commands almost complete\r
+ * more compression on jump table (16k smaller)\r
+ * Some optimising\r
+ * shl reg,1 -> add reg,reg\r
+ * or ecx,ecx:jz -> jecxz\r
+ * 22.08.99 DEO - SBCD/ABCD sets N flag same as carry\r
+ * 19.10.99 MJC - Change DOS memory routines\r
+ * Change DOS Clobber flags (ESI no longer safe)\r
+ * Save EAX around memory write where needed\r
+ * bit commands optimised\r
+ * 25.10.99 MJC - Was keeping masked register on read/write\r
+ * if register was preserved over call\r
+ * ESI assumed 'safe' again\r
+ * 25.10.99 MJC - Bank ID moved to CPU context\r
+ * 03.11.99 KENJO - VC++6.0 seems not to preserve EDI. Fixed "ABCD -(A0), -(A0)" crash / "roxr (A0)"-type shift crash\r
+ * 13.11.99 KENJO - Fixed "NABC"\r
+ * Now Win32 uses FASTCALL type call for interrupt callback\r
+ * 09.02.00 MJC - Check CPU type before allowing 68010/68020 instructions\r
+ * remove routines for 5 non existant opcodes\r
+ * 05.03.00 MJC - not command decrement A7 by 1 for bytes\r
+ * 10.03.00 MJC - as did btst,cmpm and nbcd\r
+ * 22.03.00 MJC - Divide by zero should not decrement PC by 2 before push\r
+ * Move memory banking into exception routine\r
+ * 14.04.00 Dave - BTST missing Opcode\r
+ * ASL.L > 31 shift\r
+ * 20.04.00 MJC - TST.B Also missing A7 specific routine\r
+ * - Extra Define A7ROUTINE to switch between having seperate\r
+ * routines for +-(A7) address modes.\r
+ * 24.06.00 MJC - ADDX/SUBX +-(A7) routines added.\r
+ * TAS should not touch X flag\r
+ * LSL/LSR EA not clearing V flag\r
+ * CHK not all opcodes in jump table\r
+ * Add define to mask status register\r
+ * 04.07.00 MJC - Keep high byte of Program Counter on Bxx and Jxx\r
+ * Fix flag handling on NEGX\r
+ * Really fix ADDX/SUBX +-(A7)\r
+ * PC could be set wrong after CHK.W instruction\r
+ * DIVS/DIVU always clear C flag\r
+ * ABCD/SBCD missing +-(A7) Routine\r
+ * TAS missing +-(A7) Routine\r
+ * Bitwise Static missing +-(A7) Routine\r
+ * CMPM missing +-(A7) Routine\r
+ * 30.09.00 DEO - added mull, divl, bfextu\r
+ * added '020 addressing modes\r
+ * fixed $6xff branching\r
+ * 23.01.01 MJC - Spits out seperate code for 68000 & 68020\r
+ * allows seperate optimising!\r
+ * 17.02.01 MJC - Support for encrypted PC relative fetch calls\r
+ * 11.03.01 GUTI - change some cmp reg,0 and or reg,reg with test\r
+ * 13.03.01 MJC - Single Icount for Asm & C cores\r
+ * 16.05.01 ASG - use push/pop around mem calls instead of store to safe_REG\r
+ * optimized a bit the 020 extension word decoder\r
+ * removed lots of unnecessary code in branches\r
+ *---------------------------------------------------------------\r
+ * Known Problems / Bugs\r
+ *\r
+ * 68000\r
+ * None - Let us know if you find any!\r
+ *\r
+ * 68010\r
+ * Instructions that are supervisor only as per 68000 spec.\r
+ * move address space not implemented.\r
+ *\r
+ * 68020\r
+ * only long Bcc instruction implemented.\r
+ *---------------------------------------------------------------\r
+ * Notes\r
+ *\r
+ * STALLCHECK should be defined for Pentium Class\r
+ * undefined for P2/Celerons\r
+ *\r
+ * ALIGNMENT is normally 4, but seems faster on my P2 as 0 !\r
+ *\r
+ *---------------------------------------------------------------\r
+ *\r
+ * Future Changes\r
+ *\r
+ * 68020 instructions to be completed\r
+ * assembler memory routines +\r
+ *\r
+ * and anything else that takes our fancy!\r
+ *---------------------------------------------------------------*/\r
+\r
+/* Specials - Switch what program allows/disallows */\r
+\r
+#undef STALLCHECK /* Affects fetching of Opcode */\r
+#undef SAVEPPC /* Save Previous PC */ // dave \r
+#define ENCRYPTED /* PC relative = decrypted */\r
+#define ASMBANK /* Memory banking algorithm to use */ // dave\r
+#define A7ROUTINE /* Define to use separate routines for -(a7)/(a7)+ */\r
+#define ALIGNMENT 4 /* Alignment to use for branches */\r
+#undef MASKCCR /* Mask the status register to filter out unused bits */\r
+#define KEEPHIGHPC /* Keep or Ignore bits 24-31 */\r
+#define QUICKZERO /* selects XOR r,r or MOV r,0 */\r
+\r
+#include <stdio.h>\r
+#include <stdlib.h>\r
+#include <string.h>\r
+#include <assert.h>\r
+\r
+/* New Disassembler */\r
+\r
+char * codebuf;\r
+int DisOp;\r
+\r
+#define cpu_readmem24bew(addr) (0)\r
+#define cpu_readmem24bew_word(addr) (DisOp)\r
+\r
+#define MEMORY_H /* so memory.h will not be included... */\r
+/*\r
+#include "d68k.c"\r
+*/\r
+#undef MEMORY_H\r
+\r
+#undef cpu_readmem24bew\r
+#undef cpu_readmem24bew_word\r
+\r
+#include "cpuintrf.h"\r
+\r
+/*\r
+ * Defines used by Program\r
+ *\r
+ */\r
+\r
+#define VERSION "0.30"\r
+\r
+#define TRUE -1\r
+#define FALSE 0\r
+\r
+#define EAX 0\r
+#define EBX 1\r
+#define ECX 2\r
+#define EDX 3\r
+#define ESI 4\r
+#define PC ESI\r
+#define EDI 5\r
+#define EBP 6\r
+\r
+\r
+#define NORMAL 0\r
+#define PCREL 1\r
+\r
+/* Register Location Offsets */\r
+\r
+#define ICOUNT "_m68k_ICount"\r
+\r
+#define REG_DAT "R_D0"\r
+#define REG_DAT_EBX "[R_D0+ebx*4]"\r
+#define REG_ADD "R_A0"\r
+#define REG_A7 "R_A7"\r
+#define REG_USP "R_USP"\r
+#define REG_ISP "R_ISP"\r
+#define REG_SRH "R_SR_H"\r
+#define REG_CCR "R_CCR"\r
+#define REG_X "R_XC"\r
+#define REG_PC "R_PC"\r
+#define REG_IRQ "R_IRQ"\r
+#define REG_S "R_SR"\r
+#define REG_IRQ_CALLBACK "R_IRQ_CALLBACK"\r
+#define REG_RESET_CALLBACK "R_RESET_CALLBACK"\r
+\r
+\r
+/* 68010 Regs */\r
+\r
+#define REG_VBR "R_VBR"\r
+#define REG_SFC "R_SFC"\r
+#define REG_DFC "R_DFC"\r
+\r
+#define FASTCALL_FIRST_REG "ecx"\r
+#define FASTCALL_SECOND_REG "edx"\r
+\r
+\r
+\r
+/*\r
+ * Global Variables\r
+ *\r
+ */\r
+\r
+FILE *fp = NULL;\r
+\r
+char *comptab = NULL;\r
+char *CPUtype = NULL;\r
+\r
+int CPU = 0;\r
+int FlagProcess = 0;\r
+int CheckInterrupt = 0;\r
+int ExternalIO = 0;\r
+int Opcount = 0;\r
+int TimingCycles = 0;\r
+int AddEACycles = 0;\r
+int AccessType = NORMAL;\r
+int ppro = 0;\r
+\r
+\r
+\r
+/* External register preservation */\r
+\r
+#ifdef DOS\r
+\r
+/* Registers normally saved around C routines anyway */\r
+/* GCC 2.9.1 (dos) seems to preserve EBX,EDI and EBP */\r
+static char SavedRegs[] = "-B--SDB";\r
+\r
+#elif defined(WIN32)\r
+\r
+/* visual C++, win32, says it preserves ebx, edi, esi, and ebp */\r
+/* ---------- VC++ deosn't preserve EDI? (Kenjo, 110399) ---------- */\r
+static char SavedRegs[] = "-B--S-B";\r
+\r
+#else\r
+\r
+/* Assume nothing preserved */\r
+static char SavedRegs[] = "-------";\r
+\r
+#endif\r
+\r
+\r
+\r
+/* Jump Table */\r
+\r
+int OpcodeArray[65536];\r
+\r
+/* Lookup Arrays */\r
+\r
+static char* regnameslong[] =\r
+{ "EAX","EBX","ECX","EDX","ESI","EDI","EBP"};\r
+\r
+static char* regnamesword[] =\r
+{ "AX","BX","CX","DX", "SI", "DI", "BP"};\r
+\r
+static char* regnamesshort[] =\r
+{ "AL","BL","CL","DL"};\r
+\r
+\r
+\r
+/*********************************/\r
+/* Conversion / Utility Routines */\r
+/*********************************/\r
+\r
+/* Convert EA to Address Mode Number\r
+ *\r
+ * 0 Dn\r
+ * 1 An\r
+ * 2 (An)\r
+ * 3 (An)+\r
+ * 4 -(An)\r
+ * 5 x(An)\r
+ * 6 x(An,xr.s)\r
+ * 7 x.w\r
+ * 8 x.l\r
+ * 9 x(PC)\r
+ * 10 x(PC,xr.s)\r
+ * 11 #x,SR,CCR Read = Immediate, Write = SR or CCR\r
+ * in order to read SR to AX, use READCCR\r
+ * 12-15 INVALID\r
+ *\r
+ * 19 (A7)+\r
+ * 20 -(A7)\r
+ *\r
+ */\r
+\r
+int EAtoAMN(int EA, int Way)\r
+{\r
+ int Work;\r
+\r
+ if (Way)\r
+ {\r
+ Work = (EA & 0x7);\r
+\r
+ if (Work == 7) Work += ((EA & 0x38) >> 3);\r
+\r
+ if (((Work == 3) || (Work == 4)) && (((EA & 0x38) >> 3) == 7))\r
+ {\r
+ Work += 16;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ Work = (EA & 0x38) >> 3;\r
+\r
+ if (Work == 7) Work += (EA & 7);\r
+\r
+ if (((Work == 3) || (Work == 4)) && ((EA & 7) == 7))\r
+ {\r
+ Work += 16;\r
+ }\r
+ }\r
+\r
+ return Work;\r
+}\r
+\r
+/*\r
+ * Generate Main or Sub label\r
+ */\r
+\r
+char *GenerateLabel(int ID,int Type)\r
+{\r
+ static int LabID,LabNum;\r
+/*\r
+ static char disasm[80];\r
+ char *dis = disasm;\r
+*/\r
+ if (Type == 0)\r
+ {\r
+ CheckInterrupt=0; /* No need to check for Interrupts */\r
+ ExternalIO=0; /* Not left Assembler Yet */\r
+ TimingCycles=0; /* No timing info for this command */\r
+ AddEACycles=1; /* default to add in EA timing */\r
+ Opcount++; /* for screen display */\r
+\r
+ DisOp = ID;\r
+/*\r
+ m68k_disassemble(dis,0);\r
+ sprintf(codebuf, "OP%d_%4.4x:\t\t\t\t; %s", CPU,ID, dis);\r
+*/\r
+ sprintf(codebuf, "OP%d_%4.4x:\t\t\t\t;", CPU,ID);\r
+\r
+ LabID = ID;\r
+ LabNum = 0;\r
+ }\r
+ else\r
+ {\r
+ LabNum++;\r
+ sprintf(codebuf, "OP%d_%4.4x_%1x", CPU,LabID, LabNum);\r
+ }\r
+\r
+ return codebuf;\r
+}\r
+\r
+/*\r
+ * Generate Alignment Line\r
+ */\r
+\r
+void Align(void)\r
+{\r
+ fprintf(fp, "\t\t ALIGN %d\n\n",ALIGNMENT);\r
+}\r
+\r
+/*\r
+ * Copy X into Carry\r
+ *\r
+ * There are several ways this could be done, this allows\r
+ * us to easily change the way we are doing it!\r
+ */\r
+\r
+void CopyX(void)\r
+{\r
+ /* Copy bit 0 from X flag store into Carry */\r
+\r
+ fprintf(fp, "\t\t bt dword [%s],0\n",REG_X);\r
+}\r
+\r
+/*\r
+ * Immediate 3 bit data\r
+ *\r
+ * 0=8, anything else is itself\r
+ *\r
+ * Again, several ways to achieve this\r
+ *\r
+ * ECX contains data as 3 lowest bits\r
+ *\r
+ */\r
+\r
+void ClearRegister(int regno)\r
+{\r
+#ifdef QUICKZERO\r
+ fprintf(fp, "\t\t mov %s,0\n",regnameslong[regno]);\r
+#else\r
+ fprintf(fp, "\t\t xor %s,%s\n",regnameslong[regno],regnameslong[regno]);\r
+#endif\r
+}\r
+\r
+void Immediate8(void)\r
+{\r
+ /* This takes 3 cycles, 5 bytes, no memory reads */\r
+\r
+ fprintf(fp, "\t\t dec ecx ; Move range down\n");\r
+ fprintf(fp, "\t\t and ecx,byte 7 ; Mask out lower bits\n");\r
+ fprintf(fp, "\t\t inc ecx ; correct range\n");\r
+\r
+\r
+ /* This takes 2 cycles, 10 bytes but has a memory read */\r
+ /* I don't know timing for the mov command - assumed 1 */\r
+\r
+#if 0\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ fprintf(fp, "\t\t mov ecx,[ImmTable+ECX*4]\n");\r
+#endif\r
+}\r
+\r
+/*\r
+ * This will check for bank changes before\r
+ * resorting to calling the C bank select code\r
+ *\r
+ * Most of the time it does not change!\r
+ *\r
+ */\r
+\r
+/* forward used by MemoryBanking */\r
+void Exception(int Number, int BaseCode) ;\r
+\r
+void MemoryBanking(int BaseCode)\r
+{\r
+ /* check for odd address */\r
+ fprintf(fp, "\t\t test esi, dword 1\n");\r
+ fprintf(fp, "\t\t jz near OP%d_%5.5x\n",CPU,BaseCode);\r
+\r
+ /* trying to run at an odd address */\r
+ Exception(3,BaseCode);\r
+\r
+ /* Keep Whole PC */\r
+\r
+ fprintf(fp, "OP%d_%5.5x:\n",CPU,BaseCode);\r
+\r
+/* ASG - always call to the changepc subroutine now, since the number of */\r
+/* bits varies based on the memory model */\r
+#ifdef KEEPHIGHPC\r
+ fprintf(fp, "\t\t mov [FullPC],ESI\n");\r
+#endif\r
+\r
+ /* Mask to n bits */\r
+ fprintf(fp, "\t\t and esi,[_mem_amask]\n");\r
+\r
+#if 0\r
+#ifdef KEEPHIGHPC\r
+ fprintf(fp, "\t\t mov [FullPC],ESI\n");\r
+#endif\r
+\r
+ /* Mask to 24 bits */\r
+// fprintf(fp, "\t\t and esi,0ffffffh\n");\r
+\r
+#ifdef ASMBANK\r
+ /* Assembler bank switch - 64k granularity */\r
+\r
+ fprintf(fp, "\t\t mov eax,esi\n");\r
+ fprintf(fp, "\t\t shr eax,16\n");\r
+ fprintf(fp, "\t\t cmp [asmbank],eax\n");\r
+ fprintf(fp, "\t\t je OP%d_%5.5x_Bank\n",CPU,BaseCode);\r
+\r
+ fprintf(fp, "\t\t mov [asmbank],eax\n");\r
+#else\r
+ /* This code is same as macro used by C core */\r
+\r
+ fprintf(fp, "\t\t mov ecx,esi\n");\r
+ fprintf(fp, "\t\t mov ebx,[_cur_mrhard]\n");\r
+ fprintf(fp, "\t\t shr ecx,9\n");\r
+ fprintf(fp, "\t\t mov al,byte [_opcode_entry]\n");\r
+ fprintf(fp, "\t\t cmp al,[ecx+ebx]\n");\r
+ fprintf(fp, "\t\t je OP%d_%5.5x_Bank\n",CPU,BaseCode);\r
+#endif\r
+#endif\r
+\r
+ /* Call Banking Routine */\r
+\r
+ if (SavedRegs[ESI] == '-')\r
+ {\r
+ fprintf(fp, "\t\t mov [%s],ESI\n",REG_PC);\r
+ }\r
+\r
+ if (SavedRegs[EDX] == '-')\r
+ {\r
+ fprintf(fp, "\t\t mov [%s],edx\n",REG_CCR);\r
+ }\r
+\r
+#ifdef FASTCALL\r
+ fprintf(fp, "\t\t mov %s,esi\n",FASTCALL_FIRST_REG);\r
+#else\r
+ fprintf(fp, "\t\t push esi\n");\r
+#endif\r
+\r
+ fprintf(fp, "\t\t call [_a68k_memory_intf+28]\n");\r
+\r
+#ifndef FASTCALL\r
+ fprintf(fp, "\t\t lea esp,[esp+4]\n");\r
+#endif\r
+\r
+ if (SavedRegs[EDX] == '-')\r
+ {\r
+ fprintf(fp, "\t\t mov edx,[%s]\n",REG_CCR);\r
+ }\r
+\r
+ if (SavedRegs[ESI] == '-')\r
+ {\r
+ fprintf(fp, "\t\t mov esi,[%s]\n",REG_PC);\r
+ }\r
+\r
+ /* Update our copy */\r
+\r
+ fprintf(fp, "\t\t mov ebp,dword [_OP_ROM]\n");\r
+\r
+ fprintf(fp, "OP%d_%5.5x_Bank:\n",CPU,BaseCode);\r
+}\r
+\r
+/*\r
+ * Update Previous PC value\r
+ *\r
+ */\r
+\r
+void SavePreviousPC(void)\r
+{\r
+#ifdef SAVEPPC\r
+ fprintf(fp, "\t\t mov [R_PPC],esi\t\t\t ; Keep Previous PC\n");\r
+#endif\r
+}\r
+\r
+/*\r
+ * Complete Opcode handling\r
+ *\r
+ * Any tidying up, end code\r
+ *\r
+ */\r
+\r
+void Completed(void)\r
+{\r
+\r
+ /* Flag Processing to be finished off ? */\r
+\r
+ AccessType = NORMAL;\r
+\r
+ /* Use assembler timing routines */\r
+\r
+ if (TimingCycles != 0)\r
+ {\r
+ if (TimingCycles > 127)\r
+ fprintf(fp, "\t\t sub dword [%s],%d\n",ICOUNT,TimingCycles);\r
+ else\r
+ {\r
+ if (TimingCycles != -1)\r
+ fprintf(fp, "\t\t sub dword [%s],byte %d\n",ICOUNT,TimingCycles);\r
+ }\r
+ \r
+ if (FlagProcess > 0)\r
+ fprintf(fp, "\t\t pop EDX\n");\r
+ if (FlagProcess == 2)\r
+ fprintf(fp, "\t\t mov [%s],edx\n",REG_X);\r
+\r
+ fprintf(fp, "\t\t js near MainExit\n\n");\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t test dword [%s],0xffffffff\n",ICOUNT);\r
+ \r
+ if (FlagProcess > 0)\r
+ fprintf(fp, "\t\t pop EDX\n");\r
+ if (FlagProcess == 2)\r
+ fprintf(fp, "\t\t mov [%s],edx\n",REG_X);\r
+\r
+ fprintf(fp, "\t\t jle near MainExit\n\n");\r
+ }\r
+ FlagProcess = 0;\r
+\r
+#ifdef MAME_DEBUG\r
+\r
+ /* Check for Debug Active */\r
+\r
+ fprintf(fp, "\n\t\t test byte [_mame_debug],byte 0xff\n");\r
+ fprintf(fp, "\t\t jnz near MainExit\n\n");\r
+\r
+#endif\r
+\r
+ if (CheckInterrupt)\r
+ {\r
+ fprintf(fp,"; Check for Interrupt waiting\n\n");\r
+ fprintf(fp,"\t\t test byte [%s],07H\n",REG_IRQ);\r
+ fprintf(fp,"\t\t jne near interrupt\n\n");\r
+ }\r
+\r
+ if(CPU==2)\r
+ {\r
+ /* 32 bit memory version */\r
+ fprintf(fp, "\t\t mov eax,2\n"); /* ASG */\r
+ fprintf(fp, "\t\t xor eax,esi\n"); /* ASG */\r
+\r
+#ifdef STALLCHECK\r
+ ClearRegister(ECX);\r
+ fprintf(fp, "\t\t mov cx,[eax+ebp]\n");\r
+#else\r
+ fprintf(fp, "\t\t movzx ecx,word [eax+ebp]\n");\r
+#endif\r
+ }\r
+ else\r
+ {\r
+ /* 16 bit memory */\r
+#ifdef STALLCHECK\r
+ ClearRegister(ECX);\r
+ fprintf(fp, "\t\t mov cx,[esi+ebp]\n");\r
+#else\r
+ fprintf(fp, "\t\t movzx ecx,word [esi+ebp]\n");\r
+#endif\r
+ }\r
+\r
+ fprintf(fp, "\t\t jmp [%s_OPCODETABLE+ecx*4]\n\n", CPUtype);\r
+}\r
+\r
+/*\r
+ * Flag Routines\r
+ *\r
+ * Size = B,W or L\r
+ * Sreg = Register to Test\r
+ * TestReg = Need to test register (false if flags already set up)\r
+ * SetX = if C needs to be copied across to X register\r
+ * Delayed = Delays final processing to end of routine (Completed())\r
+ *\r
+ */\r
+\r
+void TestFlags(char Size,int Sreg)\r
+{\r
+ char* Regname="";\r
+\r
+ switch (Size)\r
+ {\r
+ case 66:\r
+ Regname = regnamesshort[Sreg];\r
+ break;\r
+\r
+ case 87:\r
+ Regname = regnamesword[Sreg];\r
+ break;\r
+\r
+ case 76:\r
+ Regname = regnameslong[Sreg];\r
+ break;\r
+ }\r
+\r
+ /* Test does not update register */\r
+ /* so cannot generate partial stall */\r
+\r
+ fprintf(fp, "\t\t test %s,%s\n",Regname,Regname);\r
+}\r
+\r
+void SetFlags(char Size,int Sreg,int Testreg,int SetX,int Delayed)\r
+{\r
+ if (Testreg) TestFlags(Size,Sreg);\r
+\r
+ fprintf(fp, "\t\t pushfd\n");\r
+\r
+ if (Delayed)\r
+ {\r
+ /* Rest of code done by Completed routine */\r
+\r
+ if (SetX) FlagProcess = 2;\r
+ else FlagProcess = 1;\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t pop EDX\n");\r
+\r
+ if (SetX) fprintf(fp, "\t\t mov [%s],edx\n",REG_X);\r
+ }\r
+}\r
+\r
+/******************/\r
+/* Check CPU Type */\r
+/******************/\r
+\r
+void CheckCPUtype(int Minimum)\r
+{\r
+ if(CPU==2)\r
+ {\r
+ /* Only check for > 020 */\r
+\r
+ if(Minimum>2)\r
+ {\r
+ fprintf(fp, "\t\t mov eax,[CPUversion]\n");\r
+\r
+ fprintf(fp, "\t\t cmp al,%d\n",Minimum);\r
+ fprintf(fp, "\t\t jb near ILLEGAL\n\n");\r
+ }\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t mov eax,[CPUversion]\n");\r
+\r
+ if (Minimum == 1)\r
+ {\r
+ fprintf(fp, "\t\t test eax,eax\n");\r
+ fprintf(fp, "\t\t jz near ILLEGAL\n\n");\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t cmp al,%d\n",Minimum);\r
+ fprintf(fp, "\t\t jb near ILLEGAL\n\n");\r
+ }\r
+ }\r
+}\r
+\r
+/************************************/\r
+/* Pre-increment and Post-Decrement */\r
+/************************************/\r
+\r
+void IncrementEDI(int Size,int Rreg)\r
+{\r
+ switch (Size)\r
+ {\r
+ case 66:\r
+\r
+#ifdef A7ROUTINE\r
+\r
+ /* Always does Byte Increment - A7 uses special routine */\r
+\r
+ fprintf(fp, "\t\t inc dword [%s+%s*4]\n",REG_ADD,regnameslong[Rreg]);\r
+\r
+#else\r
+\r
+ /* A7 uses same routines, so inc by 2 if A7 */\r
+\r
+ fprintf(fp, "\t\t cmp %s,7\n",regnamesshort[Rreg]);\r
+ fprintf(fp, "\t\t cmc\n");\r
+ fprintf(fp, "\t\t adc dword [%s+%s*4],byte 1\n",REG_ADD,regnameslong[Rreg]);\r
+\r
+#endif\r
+ break;\r
+\r
+ case 87:\r
+\r
+ fprintf(fp, "\t\t add dword [%s+%s*4],byte 2\n",REG_ADD,regnameslong[Rreg]);\r
+ break;\r
+\r
+ case 76:\r
+\r
+ fprintf(fp, "\t\t add dword [%s+%s*4],byte 4\n",REG_ADD,regnameslong[Rreg]);\r
+ break;\r
+ }\r
+}\r
+\r
+void DecrementEDI(int Size,int Rreg)\r
+{\r
+ switch (Size)\r
+ {\r
+ case 66:\r
+\r
+#ifdef A7ROUTINE\r
+\r
+ /* Always does Byte Increment - A7 uses special routine */\r
+\r
+ fprintf(fp, "\t\t dec EDI\n");\r
+\r
+#else\r
+\r
+ /* A7 uses same routines, so dec by 2 if A7 */\r
+\r
+ fprintf(fp, "\t\t cmp %s,7\n",regnamesshort[Rreg]);\r
+ fprintf(fp, "\t\t cmc\n");\r
+ fprintf(fp, "\t\t sbb dword edi,byte 1\n");\r
+\r
+#endif\r
+ break;\r
+\r
+ case 87:\r
+\r
+ fprintf(fp, "\t\t sub EDI,byte 2\n");\r
+ break;\r
+\r
+ case 76:\r
+ fprintf(fp, "\t\t sub EDI,byte 4\n");\r
+ break;\r
+ }\r
+}\r
+\r
+/*\r
+ * Generate an exception\r
+ *\r
+ * if Number = -1 then assume value in AL already\r
+ * code must continue running afterwards\r
+ *\r
+ */\r
+\r
+void Exception(int Number, int BaseCode)\r
+{\r
+ if (Number > -1)\r
+ {\r
+ fprintf(fp, "\t\t sub esi,byte 2\n");\r
+ fprintf(fp, "\t\t mov al,%d\n",Number);\r
+ }\r
+\r
+ fprintf(fp, "\t\t call Exception\n\n");\r
+\r
+ if (Number > -1)\r
+ Completed();\r
+}\r
+\r
+\r
+/********************/\r
+/* Address Routines */\r
+/********************/\r
+\r
+/*\r
+ * Decode Intel flags into AX as SR register\r
+ *\r
+ * Wreg = spare register to use (must not be EAX or EDX)\r
+ */\r
+\r
+void ReadCCR(char Size, int Wreg)\r
+{\r
+ fprintf(fp, "\t\t mov eax,edx\n");\r
+ fprintf(fp, "\t\t mov ah,byte [%s]\n",REG_X);\r
+\r
+ /* Partial stall so .. switch to new bit of processing */\r
+\r
+ fprintf(fp, "\t\t mov %s,edx\n",regnameslong[Wreg]);\r
+ fprintf(fp, "\t\t and %s,byte 1\n",regnameslong[Wreg]);\r
+\r
+ /* Finish what we started */\r
+\r
+ fprintf(fp, "\t\t shr eax,4\n");\r
+ fprintf(fp, "\t\t and eax,byte 01Ch \t\t; X, N & Z\n\n");\r
+\r
+ /* and complete second task */\r
+\r
+ fprintf(fp, "\t\t or eax,%s \t\t\t\t; C\n\n",regnameslong[Wreg]);\r
+\r
+ /* and Finally */\r
+\r
+ fprintf(fp, "\t\t mov %s,edx\n",regnameslong[Wreg]);\r
+ fprintf(fp, "\t\t shr %s,10\n",regnameslong[Wreg]);\r
+ fprintf(fp, "\t\t and %s,byte 2\n",regnameslong[Wreg]);\r
+ fprintf(fp, "\t\t or eax,%s\t\t\t\t; O\n\n",regnameslong[Wreg]);\r
+\r
+ if (Size == 'W')\r
+ {\r
+ fprintf(fp, "\t\t mov ah,byte [%s] \t; T, S & I\n\n",REG_SRH);\r
+\r
+#ifdef MASKCCR\r
+ fprintf(fp, "\t\t and ax,0A71Fh\t; Mask unused bits\n");\r
+#endif\r
+ }\r
+}\r
+\r
+/*\r
+ * Convert SR into Intel flags\r
+ *\r
+ * Also handles change of mode from Supervisor to User\r
+ *\r
+ * n.b. This is also called by EffectiveAddressWrite\r
+ */\r
+\r
+void WriteCCR(char Size)\r
+{\r
+ if (Size == 'W')\r
+ {\r
+ /* Did we change from Supervisor to User mode ? */\r
+\r
+ char *Label = GenerateLabel(0,1);\r
+\r
+ fprintf(fp, "\t\t test ah,20h \t\t\t; User Mode ?\n");\r
+ fprintf(fp, "\t\t jne short %s\n\n",Label);\r
+\r
+ /* Mode Switch - Update A7 */\r
+\r
+ fprintf(fp, "\t\t mov edx,[%s]\n",REG_A7);\r
+ fprintf(fp, "\t\t mov [%s],edx\n",REG_ISP);\r
+ fprintf(fp, "\t\t mov edx,[%s]\n",REG_USP);\r
+ fprintf(fp, "\t\t mov [%s],edx\n",REG_A7);\r
+\r
+ fprintf(fp, "%s:\n",Label);\r
+ fprintf(fp, "\t\t mov byte [%s],ah \t;T, S & I\n",REG_SRH);\r
+\r
+ /* Mask may now allow Interrupt */\r
+\r
+ CheckInterrupt += 1;\r
+ }\r
+\r
+ /* Flags */\r
+\r
+ fprintf(fp, "\t\t and eax,byte 1Fh\n");\r
+ fprintf(fp, "\t\t mov edx,[IntelFlag+eax*4]\n");\r
+ fprintf(fp, "\t\t mov [%s],dh\n",REG_X);\r
+ fprintf(fp, "\t\t and edx,0EFFh\n");\r
+}\r
+\r
+\r
+/*\r
+ * Interface to Mame memory commands\r
+ *\r
+ * Flags = "ABCDSDB" - set to '-' if not required to preserve\r
+ * (order EAX,EBX,ECX,EDX,ESI,EDI,EBP)\r
+ *\r
+ * AReg = Register containing Address\r
+ *\r
+ * Mask 0 : No Masking\r
+ * 1 : Mask top byte, but preserve register\r
+ * 2 : Mask top byte, preserve masked register\r
+ */\r
+\r
+void Memory_Read(char Size,int AReg,char *Flags,int Mask)\r
+{\r
+ ExternalIO = 1;\r
+\r
+ /* Save PC */\r
+\r
+ fprintf(fp, "\t\t mov [%s],ESI\n",REG_PC);\r
+\r
+ /* Check for special mask condition */\r
+\r
+ /* ASG - no longer need to mask addresses here */\r
+/* if (Mask == 2)\r
+ fprintf(fp, "\t\t and %s,0FFFFFFh\n",regnameslong[AReg]);*/\r
+\r
+ /* Check to see if registers need saving */\r
+\r
+ if ((Flags[EDX] != '-') && (SavedRegs[EDX] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t mov [%s],edx\n",REG_CCR);\r
+ }\r
+\r
+ if ((Flags[EBX] != '-') && (SavedRegs[EBX] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t push EBX\n");\r
+ }\r
+\r
+ if ((Flags[ECX] != '-') && (SavedRegs[ECX] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t push ECX\n");\r
+ }\r
+\r
+ if ((Flags[EDI] != '-') && (SavedRegs[EDI] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t push EDI\n");\r
+ }\r
+\r
+ /* Sort Address out */\r
+\r
+#ifdef FASTCALL\r
+\r
+ fprintf(fp, "\t\t mov %s,%s\n",FASTCALL_FIRST_REG,regnameslong[AReg]);\r
+\r
+ /* ASG - no longer need to mask addresses here */\r
+/* if (Mask == 1)\r
+ fprintf(fp, "\t\t and %s,0FFFFFFh\n",FASTCALL_FIRST_REG);*/\r
+\r
+#else\r
+\r
+ if (Mask == 1)\r
+ {\r
+ if ((Flags[AReg] != '-') && (SavedRegs[AReg] != '-'))\r
+ {\r
+ /* Don't trash a wanted safe register */\r
+\r
+ fprintf(fp, "\t\t mov EAX,%s\n",regnameslong[AReg]);\r
+ /* ASG - no longer need to mask addresses here */\r
+/* fprintf(fp, "\t\t and EAX,0FFFFFFh\n");*/\r
+ fprintf(fp, "\t\t push EAX\n");\r
+ }\r
+ else\r
+ {\r
+ /* ASG - no longer need to mask addresses here */\r
+/* fprintf(fp, "\t\t and %s,0FFFFFFh\n",regnameslong[AReg]);*/\r
+ fprintf(fp, "\t\t push %s\n",regnameslong[AReg]);\r
+ }\r
+ }\r
+ else\r
+ fprintf(fp, "\t\t push %s\n",regnameslong[AReg]);\r
+\r
+#endif\r
+\r
+\r
+\r
+ /* Call Mame memory routine */\r
+\r
+ /* ASG - changed these to call through the function pointers */\r
+\r
+#ifdef ENCRYPTED\r
+ switch (AccessType)\r
+ {\r
+ case NORMAL :\r
+ switch (Size)\r
+ {\r
+ case 66 :\r
+ fprintf(fp, "\t\t call [_a68k_memory_intf+4]\n");\r
+ break;\r
+\r
+ case 87 :\r
+ fprintf(fp, "\t\t call [_a68k_memory_intf+8]\n");\r
+ break;\r
+\r
+ case 76 :\r
+ fprintf(fp, "\t\t call [_a68k_memory_intf+12]\n");\r
+ break;\r
+ }\r
+ break;\r
+\r
+ case PCREL :\r
+\r
+ switch (Size)\r
+ {\r
+ case 66 :\r
+ fprintf(fp, "\t\t call [_a68k_memory_intf+32]\n");\r
+ break;\r
+\r
+ case 87 :\r
+ fprintf(fp, "\t\t call [_a68k_memory_intf+36]\n");\r
+ break;\r
+\r
+ case 76 :\r
+ fprintf(fp, "\t\t call [_a68k_memory_intf+40]\n");\r
+ break;\r
+ }\r
+ break;\r
+ }\r
+\r
+// AccessType = NORMAL;\r
+\r
+#else\r
+\r
+ switch (Size)\r
+ {\r
+ case 66 :\r
+ fprintf(fp, "\t\t call [_a68k_memory_intf+4]\n");\r
+ break;\r
+\r
+ case 87 :\r
+ fprintf(fp, "\t\t call [_a68k_memory_intf+8]\n");\r
+ break;\r
+\r
+ case 76 :\r
+ fprintf(fp, "\t\t call [_a68k_memory_intf+12]\n");\r
+ break;\r
+ }\r
+#endif\r
+\r
+ /* Correct Stack */\r
+\r
+#ifndef FASTCALL\r
+ fprintf(fp, "\t\t lea esp,[esp+4]\n");\r
+#endif\r
+\r
+\r
+\r
+ /* Restore registers */\r
+\r
+ /* Check to see if registers need restoring */\r
+\r
+ if ((Flags[EDI] != '-') && (SavedRegs[EDI] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t pop EDI\n");\r
+ }\r
+\r
+ if ((Flags[ECX] != '-') && (SavedRegs[ECX] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t pop ECX\n");\r
+ }\r
+\r
+ if ((Flags[EBX] != '-') && (SavedRegs[EBX] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t pop EBX\n");\r
+ }\r
+\r
+ if ((Flags[ESI] != '-') && (SavedRegs[ESI] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t mov ESI,[%s]\n",REG_PC);\r
+ }\r
+\r
+ if ((Flags[EDX] != '-') && (SavedRegs[EDX] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t mov EDX,[%s]\n",REG_CCR);\r
+ }\r
+\r
+ if ((Flags[EBP] != '-') && (SavedRegs[EBP] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t mov ebp,dword [_OP_ROM]\n");\r
+ }\r
+}\r
+\r
+void Memory_Write(char Size,int AReg,int DReg,char *Flags,int Mask)\r
+{\r
+ ExternalIO = 1;\r
+\r
+ /* Save PC */\r
+\r
+ fprintf(fp, "\t\t mov [%s],ESI\n",REG_PC);\r
+\r
+ /* Check for special mask condition */\r
+\r
+ /* ASG - no longer need to mask addresses here */\r
+/* if (Mask == 2)\r
+ fprintf(fp, "\t\t and %s,0FFFFFFh\n",regnameslong[AReg]);*/\r
+\r
+ /* Check to see if registers need saving */\r
+\r
+ if ((Flags[EDX] != '-') && (SavedRegs[EDX] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t mov [%s],edx\n",REG_CCR);\r
+ }\r
+\r
+ if ((Flags[EAX] != '-') && (SavedRegs[EAX] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t push EAX\n");\r
+ }\r
+\r
+ if ((Flags[EBX] != '-') && (SavedRegs[EBX] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t push EBX\n");\r
+ }\r
+\r
+ if ((Flags[ECX] != '-') && (SavedRegs[ECX] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t push ECX\n");\r
+ }\r
+\r
+ if ((Flags[EDI] != '-') && (SavedRegs[EDI] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t push EDI\n");\r
+ }\r
+\r
+#ifdef FASTCALL\r
+\r
+ fprintf(fp, "\t\t mov %s,%s\n",FASTCALL_SECOND_REG,regnameslong[DReg]);\r
+ fprintf(fp, "\t\t mov %s,%s\n",FASTCALL_FIRST_REG,regnameslong[AReg]);\r
+\r
+ /* ASG - no longer need to mask addresses here */\r
+/* if (Mask == 1)\r
+ fprintf(fp, "\t\t and %s,0FFFFFFh\n",FASTCALL_FIRST_REG);*/\r
+\r
+#else\r
+\r
+ fprintf(fp, "\t\t push %s\n",regnameslong[DReg]);\r
+\r
+ if (Mask == 1)\r
+ {\r
+ if ((Flags[AReg] != '-') && (SavedRegs[AReg] != '-'))\r
+ {\r
+ /* Don't trash a wanted safe register */\r
+\r
+ fprintf(fp, "\t\t mov EAX,%s\n",regnameslong[AReg]);\r
+ /* ASG - no longer need to mask addresses here */\r
+/* fprintf(fp, "\t\t and EAX,0FFFFFFh\n");*/\r
+ fprintf(fp, "\t\t push EAX\n");\r
+ }\r
+ else\r
+ {\r
+ /* ASG - no longer need to mask addresses here */\r
+/* fprintf(fp, "\t\t and %s,0FFFFFFh\n",regnameslong[AReg]);*/\r
+ fprintf(fp, "\t\t push %s\n",regnameslong[AReg]);\r
+ }\r
+ }\r
+ else\r
+ fprintf(fp, "\t\t push %s\n",regnameslong[AReg]);\r
+\r
+#endif\r
+\r
+\r
+\r
+ /* Call Mame Routine */\r
+\r
+ /* ASG - changed these to call through the function pointers */\r
+ switch (Size)\r
+ {\r
+ case 66 :\r
+ fprintf(fp, "\t\t call [_a68k_memory_intf+16]\n");\r
+ break;\r
+\r
+ case 87 :\r
+ fprintf(fp, "\t\t call [_a68k_memory_intf+20]\n");\r
+ break;\r
+\r
+ case 76 :\r
+ fprintf(fp, "\t\t call [_a68k_memory_intf+24]\n");\r
+ break;\r
+ }\r
+\r
+ /* Correct Stack */\r
+\r
+#ifndef FASTCALL\r
+ fprintf(fp, "\t\t lea esp,[esp+8]\n");\r
+#endif\r
+\r
+\r
+\r
+ /* Restore registers */\r
+\r
+ /* Check to see if registers need restoring */\r
+\r
+ if ((Flags[EDI] != '-') && (SavedRegs[EDI] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t pop EDI\n");\r
+ }\r
+\r
+ if ((Flags[ECX] != '-') && (SavedRegs[ECX] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t pop ECX\n");\r
+ }\r
+\r
+ if ((Flags[EBX] != '-') && (SavedRegs[EBX] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t pop EBX\n");\r
+ }\r
+\r
+ if ((Flags[EAX] != '-') && (SavedRegs[EAX] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t pop EAX\n");\r
+ }\r
+\r
+ if ((Flags[EDX] != '-') && (SavedRegs[EDX] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t mov EDX,[%s]\n",REG_CCR);\r
+ }\r
+\r
+ if ((Flags[ESI] != '-') && (SavedRegs[ESI] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t mov ESI,[%s]\n",REG_PC);\r
+ }\r
+\r
+ if ((Flags[EBP] != '-') && (SavedRegs[EBP] == '-'))\r
+ {\r
+ fprintf(fp, "\t\t mov ebp,dword [_OP_ROM]\n");\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Fetch data from Code area\r
+ *\r
+ * Dreg = Destination Register\r
+ * Extend = Sign Extend Word to Long\r
+ *\r
+ */\r
+\r
+void Memory_Fetch(char Size,int Dreg,int Extend)\r
+{\r
+ static int loopcount=0;\r
+\r
+ /* Always goes via OP_ROM */\r
+\r
+ if(CPU!=2)\r
+ {\r
+ /* 16 Bit version */\r
+\r
+ if ((Extend == TRUE) & (Size == 'W'))\r
+ fprintf(fp, "\t\t movsx %s,word [esi+ebp]\n",regnameslong[Dreg]);\r
+ else if (Size == 'W')\r
+ fprintf(fp, "\t\t movzx %s,word [esi+ebp]\n",regnameslong[Dreg]);\r
+ else\r
+ fprintf(fp, "\t\t mov %s,dword [esi+ebp]\n",regnameslong[Dreg]);\r
+\r
+ if (Size == 'L')\r
+ fprintf(fp, "\t\t rol %s,16\n",regnameslong[Dreg]);\r
+ }\r
+ else\r
+ {\r
+ /* 32 Bit version */\r
+\r
+ if (Size == 'W')\r
+ {\r
+ fprintf(fp, "\t\t mov %s,esi\n",regnameslong[Dreg]);\r
+ fprintf(fp, "\t\t xor %s,byte 2\n",regnameslong[Dreg]);\r
+\r
+ if (Extend == TRUE)\r
+ fprintf(fp, "\t\t movsx %s,word [%s+ebp]\n",regnameslong[Dreg],regnameslong[Dreg]);\r
+ else\r
+ fprintf(fp, "\t\t movzx %s,word [%s+ebp]\n",regnameslong[Dreg],regnameslong[Dreg]);\r
+ }\r
+ else\r
+ {\r
+ // if address is exact multiple of 4, long read will work\r
+ // otherwise we need to get words address-2 and address+4\r
+\r
+ // Always read long\r
+ fprintf(fp, "\t\t test esi,2\n");\r
+#if (!ppro)\r
+ fprintf(fp, "\t\t mov %s,dword [esi+ebp]\n",regnameslong[Dreg]);\r
+\r
+ // OK ?\r
+ fprintf(fp, "\t\t jz short FL%3.3d\n",loopcount+1);\r
+\r
+ // no, so get high word\r
+ fprintf(fp, "\t\t mov %s,dword [esi+ebp-4]\n",regnameslong[Dreg]);\r
+ // and get low word\r
+ fprintf(fp, "\t\t mov %s,word [esi+ebp+4]\n",regnamesword[Dreg]);\r
+\r
+ fprintf(fp, "FL%3.3d:\n",++loopcount);\r
+#else\r
+ fprintf(fp, "\t\t cmovnz %s,dword [esi+ebp-4]\n",regnameslong[Dreg]);\r
+ fprintf(fp, "\t\t cmovz %s,dword [esi+ebp]\n",regnameslong[Dreg]);\r
+ fprintf(fp, "\t\t cmovnz %s,word [esi+ebp+4]\n",regnamesword[Dreg]);\r
+#endif\r
+ }\r
+ }\r
+}\r
+\r
+/**********************/\r
+/* Push PC onto Stack */\r
+/**********************/\r
+\r
+void PushPC(int Wreg,int Wreg2,char *Flags, int Mask)\r
+{\r
+\r
+ /* Wreg2 is only used when high byte is kept */\r
+ /* If it is EBP then the register is restored */\r
+\r
+ fprintf(fp, "\t\t mov %s,[%s]\t ; Push onto Stack\n",regnameslong[Wreg],REG_A7);\r
+ fprintf(fp, "\t\t sub %s,byte 4\n",regnameslong[Wreg]);\r
+ fprintf(fp, "\t\t mov [%s],%s\n",REG_A7,regnameslong[Wreg]);\r
+\r
+#ifndef KEEPHIGHPC\r
+\r
+ Memory_Write('L',Wreg,ESI,Flags,Mask);\r
+\r
+#else\r
+\r
+ fprintf(fp, "\t\t mov %s,[FullPC]\n",regnameslong[Wreg2]);\r
+ fprintf(fp, "\t\t and %s,0xff000000\n",regnameslong[Wreg2]);\r
+ fprintf(fp, "\t\t or %s,ESI\n",regnameslong[Wreg2]);\r
+\r
+ Memory_Write('L',Wreg,Wreg2,Flags,Mask);\r
+\r
+ if (Wreg2 == EBP)\r
+ {\r
+ fprintf(fp, "\t\t mov ebp,dword [_OP_ROM]\n");\r
+ }\r
+\r
+#endif\r
+}\r
+\r
+void ExtensionDecode(int SaveEDX)\r
+{\r
+ char *Label = GenerateLabel(0,1);\r
+\r
+ if (SaveEDX)\r
+ fprintf(fp, "\t\t push edx\n");\r
+\r
+ Memory_Fetch('W',EAX,FALSE);\r
+ fprintf(fp, "\t\t add esi,byte 2\n");\r
+\r
+ if(CPU!=2)\r
+ {\r
+ /* 68000 Extension */\r
+\r
+ fprintf(fp, "\t\t mov edx,eax\n");\r
+ fprintf(fp, "\t\t shr eax,12\n");\r
+ fprintf(fp, "\t\t test edx,0x0800\n");\r
+ fprintf(fp, "\t\t mov eax,[%s+eax*4]\n",REG_DAT);\r
+ fprintf(fp, "\t\t jnz short %s\n",Label);\r
+ fprintf(fp, "\t\t cwde\n");\r
+ fprintf(fp, "%s:\n",Label);\r
+ fprintf(fp, "\t\t lea edi,[edi+eax]\n");\r
+ fprintf(fp, "\t\t movsx edx,dl\n");\r
+ fprintf(fp, "\t\t lea edi,[edi+edx]\n");\r
+ }\r
+ else\r
+ {\r
+ /* 68020 Extension */\r
+\r
+ // eax holds scaled index\r
+\r
+ // might be faster just to push all regs\r
+ fprintf(fp, "\t\t push ebx\n");\r
+ fprintf(fp, "\t\t push ecx\n");\r
+\r
+ // copies for later use\r
+ fprintf(fp, "\t\t mov ecx,eax\n");\r
+ fprintf(fp, "\t\t mov edx,eax\n");\r
+\r
+ // check E bit to see if displacement or full format\r
+ fprintf(fp, "\t\t test edx,0x0100\n");\r
+ fprintf(fp, "\t\t jz short %s_a\n",Label);\r
+ // full mode so check IS (index supress)\r
+ fprintf(fp, "\t\t test edx,0x0040\n");\r
+ fprintf(fp, "\t\t jz short %s_b\n",Label);\r
+ // set index to 0, it's not added\r
+ ClearRegister(EAX);\r
+ fprintf(fp, "\t\t jmp short %s_d\n",Label); // near\r
+\r
+ // add displacement\r
+ fprintf(fp, "%s_a:\n",Label);\r
+ fprintf(fp, "\t\t movsx eax,al\n");\r
+ fprintf(fp, "\t\t lea edi,[edi+eax]\n");\r
+\r
+ fprintf(fp, "%s_b:\n",Label);\r
+ // calc index always scale (68k will scale by 1)\r
+ fprintf(fp, "\t\t mov eax,edx\n");\r
+ fprintf(fp, "\t\t shr eax,12\n");\r
+ fprintf(fp, "\t\t test edx,0x0800\n");\r
+ fprintf(fp, "\t\t mov eax,[%s+eax*4]\n",REG_DAT);\r
+ fprintf(fp, "\t\t jnz short %s_c\n",Label);\r
+ fprintf(fp, "\t\t cwde\n");\r
+\r
+ fprintf(fp, "%s_c:\n",Label);\r
+ fprintf(fp, "\t\t shr ecx,byte 9\n");\r
+ fprintf(fp, "\t\t and ecx,byte 3\n");\r
+ fprintf(fp, "\t\t shl eax,cl\n");\r
+\r
+ // if brief mode we can add index and exit\r
+ fprintf(fp, "\t\t test edx,0x0100\n");\r
+ fprintf(fp, "\t\t jz near %s_i2\n",Label);\r
+\r
+ fprintf(fp, "%s_d:\n",Label);\r
+ // check BS (base supress)\r
+ // if BS is 1 then set edi to 0\r
+ fprintf(fp, "\t\t test edx,0x0080\n");\r
+ fprintf(fp, "\t\t jz short %s_4a\n",Label);\r
+ ClearRegister(EDI);\r
+ // if null displacement skip over\r
+ fprintf(fp, "%s_4a:\n",Label);\r
+ fprintf(fp, "\t\t test edx,0x0020\n");\r
+ fprintf(fp, "\t\t jz short %s_f\n",Label);\r
+\r
+ // **** calc base displacement ****\r
+ // is it long\r
+ fprintf(fp, "\t\t test edx,0x0010\n");\r
+ fprintf(fp, "\t\t jz short %s_e\n",Label);\r
+ // fetch long base\r
+ Memory_Fetch('L',EBX,FALSE);\r
+ fprintf(fp, "\t\t lea edi,[edi+ebx]\n");\r
+ fprintf(fp, "\t\t add esi,byte 4\n");\r
+ fprintf(fp, "\t\t jmp short %s_f\n",Label);\r
+\r
+ // fetch word base\r
+ fprintf(fp, "%s_e:\n",Label);\r
+ Memory_Fetch('W',EBX,TRUE);\r
+ fprintf(fp, "\t\t lea edi,[edi+ebx]\n");\r
+ fprintf(fp, "\t\t add esi,byte 2\n");\r
+\r
+ // **** indirect? ****\r
+ fprintf(fp, "%s_f:\n",Label);\r
+ fprintf(fp, "\t\t test edx,0x0003\n");\r
+ fprintf(fp, "\t\t jz near %s_7a\n",Label);\r
+ // pre or post indirect\r
+ fprintf(fp, "\t\t test edx,0x0004\n");\r
+ fprintf(fp, "\t\t jnz short %s_g\n",Label);\r
+ // do pre\r
+ fprintf(fp, "\t\t lea edi,[edi+eax]\n");\r
+ Memory_Read('L',EDI,"ABCDSDB",2);\r
+ fprintf(fp, "\t\t mov edi,eax\n");\r
+ fprintf(fp, "\t\t jmp short %s_h\n",Label);\r
+\r
+ // do post\r
+ fprintf(fp, "%s_g:\n",Label);\r
+ fprintf(fp, "\t\t push eax\n");\r
+ Memory_Read('L',EDI,"-B-DS-B",2);\r
+ fprintf(fp, "\t\t pop edi\n");\r
+\r
+ fprintf(fp, "%s_7a:\n",Label);\r
+ fprintf(fp, "\t\t lea edi,[edi+eax]\n");\r
+\r
+ // **** outer displacement ****\r
+ // if null displacement skip over\r
+ fprintf(fp, "%s_h:\n",Label);\r
+ fprintf(fp, "\t\t test edx,0x0002\n");\r
+ fprintf(fp, "\t\t jz short %s_j\n",Label);\r
+ // word or long?\r
+ fprintf(fp, "\t\t test edx,0x0001\n");\r
+ fprintf(fp, "\t\t jz short %s_i\n",Label);\r
+ // fetch long\r
+ Memory_Fetch('L',EAX,FALSE);\r
+ fprintf(fp, "\t\t add esi,byte 4\n");\r
+ fprintf(fp, "\t\t jmp short %s_i2\n",Label);\r
+ // fetch word\r
+ fprintf(fp, "%s_i:\n",Label);\r
+ Memory_Fetch('W',EAX,TRUE);\r
+ fprintf(fp, "\t\t add esi,byte 2\n");\r
+ fprintf(fp, "%s_i2:\n",Label);\r
+ fprintf(fp, "\t\t lea edi,[edi+eax]\n");\r
+\r
+ // **** exit ****\r
+ fprintf(fp, "%s_j:\n",Label);\r
+ fprintf(fp, "\t\t pop ecx\n");\r
+ fprintf(fp, "\t\t pop ebx\n");\r
+ }\r
+\r
+ if (SaveEDX)\r
+ fprintf(fp, "\t\t pop edx\n");\r
+}\r
+\r
+/* Calculate Effective Address - Return address in EDI\r
+ *\r
+ * mode = Effective Address from Instruction\r
+ * Size = Byte,Word or Long\r
+ * Rreg = Register with Register Number in\r
+ *\r
+ * Only for modes 2 - 10 (5-10 clobber EAX)\r
+ */\r
+\r
+void EffectiveAddressCalculate(int mode,char Size,int Rreg,int SaveEDX)\r
+{\r
+ /* timing */\r
+\r
+ if ((TimingCycles > 0) && (AddEACycles!=0))\r
+ {\r
+ switch (mode)\r
+ {\r
+ case 2: /* (An) */\r
+ case 3: /* (An)+ */\r
+ case 11: /* #x,SR,CCR */\r
+ case 19: /* (A7)+ */\r
+ TimingCycles += 4 ;\r
+ break ;\r
+\r
+ case 4: /* -(An) */\r
+ case 20: /* -(A7) */\r
+ TimingCycles += (CPU==2) ? 5 : 6 ;\r
+ break ;\r
+\r
+ case 5: /* x(An) */\r
+ case 9: /* x(PC) */\r
+ TimingCycles += (CPU==2) ? 5 : 8 ;\r
+ break ;\r
+\r
+ case 7: /* x.w */\r
+ TimingCycles += (CPU==2) ? 4 : 8 ;\r
+ break ;\r
+\r
+ case 6: /* x(An,xr.s) */\r
+ case 10: /* x(PC,xr.s) */\r
+ TimingCycles += (CPU==2) ? 7 : 10 ;\r
+ break ;\r
+\r
+ case 8: /* x.l */\r
+ TimingCycles += (CPU==2) ? 4 : 12 ;\r
+ break ;\r
+ }\r
+\r
+ /* long w/r adds 4 cycles */\r
+\r
+ if ((mode>1) && (Size == 'L') && (CPU != 2))\r
+ TimingCycles += 4 ;\r
+ }\r
+\r
+ AccessType = NORMAL;\r
+\r
+ switch (mode)\r
+ {\r
+\r
+ case 2:\r
+ fprintf(fp, "\t\t mov EDI,[%s+%s*4]\n",REG_ADD,regnameslong[Rreg]);\r
+ break;\r
+\r
+ case 3:\r
+ fprintf(fp, "\t\t mov EDI,[%s+%s*4]\n",REG_ADD,regnameslong[Rreg]);\r
+ IncrementEDI(Size,Rreg);\r
+ break;\r
+\r
+ case 4:\r
+ fprintf(fp, "\t\t mov EDI,[%s+%s*4]\n",REG_ADD,regnameslong[Rreg]);\r
+ DecrementEDI(Size,Rreg);\r
+ fprintf(fp, "\t\t mov [%s+%s*4],EDI\n",REG_ADD,regnameslong[Rreg]);\r
+ break;\r
+\r
+ case 5:\r
+ Memory_Fetch('W',EAX,TRUE);\r
+ fprintf(fp, "\t\t mov EDI,[%s+%s*4]\n",REG_ADD,regnameslong[Rreg]);\r
+ fprintf(fp, "\t\t add esi,byte 2\n");\r
+ fprintf(fp, "\t\t add edi,eax\n");\r
+ break;\r
+\r
+ case 6:\r
+\r
+ /* Get Address register Value */\r
+\r
+ fprintf(fp, "\t\t mov EDI,[%s+%s*4]\n",REG_ADD,regnameslong[Rreg]);\r
+\r
+ /* Add Extension Details */\r
+\r
+ ExtensionDecode(SaveEDX);\r
+ break;\r
+\r
+ case 7:\r
+\r
+ /* Get Word */\r
+\r
+ Memory_Fetch('W',EDI,TRUE);\r
+// fprintf(fp, "\t\t movsx edi,di\n");\r
+ fprintf(fp, "\t\t add esi,byte 2\n");\r
+ break;\r
+\r
+ case 8:\r
+\r
+ /* Get Long */\r
+\r
+ Memory_Fetch('L',EDI,FALSE);\r
+ fprintf(fp, "\t\t add esi,byte 4\n");\r
+ break;\r
+\r
+ case 9:\r
+\r
+ AccessType = PCREL;\r
+\r
+ Memory_Fetch('W',EAX,TRUE);\r
+// fprintf(fp, "\t\t movsx eax,ax\n");\r
+ fprintf(fp, "\t\t mov EDI,ESI ; Get PC\n");\r
+ fprintf(fp, "\t\t add esi,byte 2\n");\r
+ fprintf(fp, "\t\t add edi,eax ; Add Offset to PC\n");\r
+ break;\r
+\r
+ case 10:\r
+\r
+ AccessType = PCREL;\r
+\r
+ /* Get PC */\r
+\r
+ fprintf(fp, "\t\t mov edi,esi ; Get PC\n");\r
+\r
+ /* Add Extension Details */\r
+\r
+ ExtensionDecode(SaveEDX);\r
+\r
+ break;\r
+\r
+ case 19:\r
+\r
+ /* (A7)+ */\r
+\r
+ fprintf(fp, "\t\t mov edi,[%s] ; Get A7\n",REG_A7);\r
+ fprintf(fp, "\t\t add dword [%s],byte 2\n",REG_A7);\r
+ break;\r
+\r
+ case 20:\r
+\r
+ /* -(A7) */\r
+\r
+ fprintf(fp, "\t\t mov edi,[%s] ; Get A7\n",REG_A7);\r
+ fprintf(fp, "\t\t sub edi,byte 2\n");\r
+ fprintf(fp, "\t\t mov [%s],edi\n",REG_A7);\r
+ break;\r
+\r
+ }\r
+}\r
+\r
+/* Read from Effective Address\r
+ *\r
+ * mode = Effective Address from Instruction\r
+ * Size = Byte,Word or Long\r
+ * Rreg = Register with Register Number in\r
+ * Flag = Registers to preserve (EDX is handled by SaveEDX)\r
+ *\r
+ * Return\r
+ * Dreg = Register to return result in (EAX is usually most efficient)\r
+ * (modes 5 to 10) EDI = Address of data read (masked with FFFFFF)\r
+ */\r
+\r
+void EffectiveAddressRead(int mode,char Size,int Rreg,int Dreg,const char *flags,int SaveEDX)\r
+{\r
+ char* Regname="";\r
+ int MaskMode;\r
+ char Flags[8];\r
+\r
+ AccessType = NORMAL;\r
+\r
+ strcpy(Flags,flags);\r
+\r
+ /* Which Masking to Use */\r
+\r
+ if (Flags[5] != '-')\r
+ MaskMode = 2;\r
+ else\r
+ MaskMode = 1;\r
+\r
+ if (SaveEDX)\r
+ Flags[3] = 'D';\r
+ else\r
+ Flags[3] = '-';\r
+\r
+ switch (Size)\r
+ {\r
+ case 66:\r
+ Regname = regnamesshort[Dreg];\r
+ break;\r
+\r
+ case 87:\r
+ Regname = regnamesword[Dreg];\r
+ break;\r
+\r
+ case 76:\r
+ Regname = regnameslong[Dreg];\r
+ break;\r
+ }\r
+\r
+ switch (mode & 15)\r
+ {\r
+\r
+ case 0:\r
+\r
+ /* Read 32 bits - No prefix */\r
+\r
+ fprintf(fp, "\t\t mov %s,[%s+%s*4]\n",regnameslong[Dreg],REG_DAT,regnameslong[Rreg]);\r
+ break;\r
+\r
+ case 1:\r
+\r
+ /* Read 32 bits - No prefix */\r
+\r
+ fprintf(fp, "\t\t mov %s,[%s+%s*4]\n",regnameslong[Dreg],REG_ADD,regnameslong[Rreg]);\r
+ break;\r
+\r
+ case 2:\r
+ EffectiveAddressCalculate(mode,Size,Rreg,SaveEDX);\r
+\r
+ Memory_Read(Size,EDI,Flags,MaskMode);\r
+\r
+ if (Dreg != EAX)\r
+ {\r
+ fprintf(fp, "\t\t mov %s,EAX\n",regnameslong[Dreg]);\r
+ }\r
+ break;\r
+\r
+ case 3:\r
+ EffectiveAddressCalculate(mode,Size,Rreg,SaveEDX);\r
+\r
+ Memory_Read(Size,EDI,Flags,MaskMode);\r
+\r
+ if (Dreg != EAX)\r
+ {\r
+ fprintf(fp, "\t\t mov %s,EAX\n",regnameslong[Dreg]);\r
+ }\r
+ break;\r
+\r
+ case 4:\r
+ EffectiveAddressCalculate(mode,Size,Rreg,SaveEDX);\r
+\r
+ Memory_Read(Size,EDI,Flags,MaskMode);\r
+\r
+ if (Dreg != EAX)\r
+ {\r
+ fprintf(fp, "\t\t mov %s,EAX\n",regnameslong[Dreg]);\r
+ }\r
+ break;\r
+\r
+\r
+ case 5:\r
+ EffectiveAddressCalculate(mode,Size,Rreg,SaveEDX);\r
+\r
+ Memory_Read(Size,EDI,Flags,MaskMode);\r
+\r
+ if (Dreg != EAX)\r
+ {\r
+ fprintf(fp, "\t\t mov %s,EAX\n",regnameslong[Dreg]);\r
+ }\r
+ break;\r
+\r
+ case 6:\r
+ EffectiveAddressCalculate(mode,Size,Rreg,SaveEDX);\r
+\r
+ Memory_Read(Size,EDI,Flags,MaskMode);\r
+\r
+ if (Dreg != EAX)\r
+ {\r
+ fprintf(fp, "\t\t mov %s,EAX\n",regnameslong[Dreg]);\r
+ }\r
+ break;\r
+\r
+ case 7:\r
+ EffectiveAddressCalculate(mode,Size,Rreg,SaveEDX);\r
+\r
+ Memory_Read(Size,EDI,Flags,MaskMode);\r
+\r
+ if (Dreg != EAX)\r
+ {\r
+ fprintf(fp, "\t\t mov %s,EAX\n",regnameslong[Dreg]);\r
+ }\r
+ break;\r
+\r
+ case 8:\r
+ EffectiveAddressCalculate(mode,Size,Rreg,SaveEDX);\r
+\r
+ Memory_Read(Size,EDI,Flags,MaskMode);\r
+\r
+ if (Dreg != EAX)\r
+ {\r
+ fprintf(fp, "\t\t mov %s,EAX\n",regnameslong[Dreg]);\r
+ }\r
+ break;\r
+\r
+ case 9:\r
+ EffectiveAddressCalculate(mode,Size,Rreg,SaveEDX);\r
+\r
+ Memory_Read(Size,EDI,Flags,MaskMode);\r
+\r
+ if (Dreg != EAX)\r
+ {\r
+ fprintf(fp, "\t\t mov %s,EAX\n",regnameslong[Dreg]);\r
+ }\r
+ break;\r
+\r
+ case 10:\r
+ EffectiveAddressCalculate(mode,Size,Rreg,SaveEDX);\r
+\r
+ Memory_Read(Size,EDI,Flags,MaskMode);\r
+\r
+ if (Dreg != EAX)\r
+ {\r
+ fprintf(fp, "\t\t mov %s,EAX\n",regnameslong[Dreg]);\r
+ }\r
+ break;\r
+\r
+ case 11:\r
+\r
+ /* Immediate - for SR or CCR see ReadCCR() */\r
+\r
+ if (Size == 'L')\r
+ {\r
+ Memory_Fetch('L',Dreg,FALSE);\r
+ fprintf(fp, "\t\t add esi,byte 4\n");\r
+ }\r
+ else\r
+ {\r
+ Memory_Fetch('W',Dreg,FALSE);\r
+ fprintf(fp, "\t\t add esi,byte 2\n");\r
+ };\r
+ break;\r
+ }\r
+}\r
+\r
+/*\r
+ * EA = Effective Address from Instruction\r
+ * Size = Byte,Word or Long\r
+ * Rreg = Register with Register Number in\r
+ *\r
+ * Writes from EAX\r
+ */\r
+\r
+void EffectiveAddressWrite(int mode,char Size,int Rreg,int CalcAddress,const char *flags,int SaveEDX)\r
+{\r
+ int MaskMode;\r
+ char* Regname="";\r
+ char Flags[8];\r
+\r
+\r
+ strcpy(Flags,flags);\r
+\r
+ /* Which Masking to Use ? */\r
+\r
+ if (CalcAddress)\r
+ {\r
+ if (Flags[5] != '-')\r
+ MaskMode = 2;\r
+ else\r
+ MaskMode = 1;\r
+ }\r
+ else\r
+ MaskMode = 0;\r
+\r
+ if (SaveEDX)\r
+ Flags[3] = 'D';\r
+ else\r
+ Flags[3] = '-';\r
+\r
+ switch (Size)\r
+ {\r
+ case 66:\r
+ Regname = regnamesshort[0];\r
+ break;\r
+\r
+ case 87:\r
+ Regname = regnamesword[0];\r
+ break;\r
+\r
+ case 76:\r
+ Regname = regnameslong[0];\r
+ break;\r
+ }\r
+\r
+ switch (mode & 15)\r
+ {\r
+\r
+ case 0:\r
+ fprintf(fp, "\t\t mov [%s+%s*4],%s\n",REG_DAT,regnameslong[Rreg],Regname);\r
+ break;\r
+\r
+ case 1:\r
+ if (Size == 66)\r
+ {\r
+ /* Not Allowed */\r
+\r
+ fprintf(fp, "DUFF CODE!\n");\r
+ }\r
+ else\r
+ {\r
+ if (Size == 87)\r
+ {\r
+ fprintf(fp, "\t\t cwde\n");\r
+ }\r
+\r
+ fprintf(fp, "\t\t mov [%s+%s*4],%s\n",REG_ADD,regnameslong[Rreg],regnameslong[0]);\r
+ }\r
+ break;\r
+\r
+ case 2:\r
+ if (CalcAddress) EffectiveAddressCalculate(mode,Size,Rreg,SaveEDX);\r
+ Memory_Write(Size,EDI,EAX,Flags,MaskMode);\r
+ break;\r
+\r
+ case 3:\r
+ if (CalcAddress) EffectiveAddressCalculate(mode,Size,Rreg,SaveEDX);\r
+ Memory_Write(Size,EDI,EAX,Flags,MaskMode);\r
+ break;\r
+\r
+ case 4:\r
+ if (CalcAddress) EffectiveAddressCalculate(mode,Size,Rreg,SaveEDX);\r
+ Memory_Write(Size,EDI,EAX,Flags,MaskMode);\r
+ break;\r
+\r
+ case 5:\r
+ if (CalcAddress)\r
+ {\r
+ fprintf(fp, "\t\t push EAX\n");\r
+ EffectiveAddressCalculate(mode,Size,Rreg,SaveEDX);\r
+ fprintf(fp, "\t\t pop EAX\n");\r
+ }\r
+ Memory_Write(Size,EDI,EAX,Flags,MaskMode);\r
+ break;\r
+\r
+ case 6:\r
+ if (CalcAddress)\r
+ {\r
+ fprintf(fp, "\t\t push EAX\n");\r
+ EffectiveAddressCalculate(mode,Size,Rreg,SaveEDX);\r
+ fprintf(fp, "\t\t pop EAX\n");\r
+ }\r
+ Memory_Write(Size,EDI,EAX,Flags,MaskMode);\r
+ break;\r
+\r
+ case 7:\r
+ if (CalcAddress)\r
+ {\r
+ fprintf(fp, "\t\t push EAX\n");\r
+ EffectiveAddressCalculate(mode,Size,Rreg,SaveEDX);\r
+ fprintf(fp, "\t\t pop EAX\n");\r
+ }\r
+ Memory_Write(Size,EDI,EAX,Flags,MaskMode);\r
+ break;\r
+\r
+ case 8:\r
+ if (CalcAddress)\r
+ {\r
+ fprintf(fp, "\t\t push EAX\n");\r
+ EffectiveAddressCalculate(mode,Size,Rreg,SaveEDX);\r
+ fprintf(fp, "\t\t pop EAX\n");\r
+ }\r
+ Memory_Write(Size,EDI,EAX,Flags,MaskMode);\r
+ break;\r
+\r
+ case 9:\r
+ if (CalcAddress)\r
+ {\r
+ fprintf(fp, "\t\t push EAX\n");\r
+ EffectiveAddressCalculate(mode,Size,Rreg,SaveEDX);\r
+ fprintf(fp, "\t\t pop EAX\n");\r
+ }\r
+ Memory_Write(Size,EDI,EAX,Flags,MaskMode);\r
+ break;\r
+\r
+ case 10:\r
+ if (CalcAddress)\r
+ {\r
+ fprintf(fp, "\t\t push EAX\n");\r
+ EffectiveAddressCalculate(mode,Size,Rreg,SaveEDX);\r
+ fprintf(fp, "\t\t pop EAX\n");\r
+ }\r
+ Memory_Write(Size,EDI,EAX,Flags,MaskMode);\r
+ break;\r
+\r
+ case 11:\r
+\r
+ /* SR, CCR - Chain to correct routine */\r
+\r
+ WriteCCR(Size);\r
+ }\r
+}\r
+\r
+/* Condition Decode Routines */\r
+\r
+/*\r
+ * mode = condition to check for\r
+ *\r
+ * Returns LABEL that is jumped to if condition is Condition\r
+ *\r
+ * Some conditions clobber AH\r
+ */\r
+\r
+char *ConditionDecode(int mode, int Condition)\r
+{\r
+ char *Label = GenerateLabel(0,1);\r
+\r
+ switch (mode)\r
+ {\r
+\r
+ case 0: /* A - Always */\r
+ if (Condition)\r
+ {\r
+ fprintf(fp, "\t\t jmp %s ;dave removed near\n",Label);\r
+ }\r
+ break;\r
+\r
+ case 1: /* F - Never */\r
+ if (!Condition)\r
+ {\r
+ fprintf(fp, "\t\t jmp near %s\n",Label);\r
+ }\r
+ break;\r
+\r
+ case 2: /* Hi */\r
+ fprintf(fp, "\t\t mov ah,dl\n");\r
+ fprintf(fp, "\t\t sahf\n");\r
+\r
+ if (Condition)\r
+ {\r
+ fprintf(fp, "\t\t ja near %s\n",Label);\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t jbe near %s\n",Label);\r
+ }\r
+ break;\r
+\r
+ case 3: /* Ls */\r
+ fprintf(fp, "\t\t mov ah,dl\n");\r
+ fprintf(fp, "\t\t sahf\n");\r
+\r
+ if (Condition)\r
+ {\r
+ fprintf(fp, "\t\t jbe near %s\n",Label);\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t ja near %s\n",Label);\r
+ }\r
+ break;\r
+\r
+ case 4: /* CC */\r
+ fprintf(fp, "\t\t test dl,1H\t\t;check carry\n");\r
+\r
+ if (Condition)\r
+ {\r
+ fprintf(fp, "\t\t jz near %s\n",Label);\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t jnz near %s\n",Label);\r
+ }\r
+ break;\r
+\r
+ case 5: /* CS */\r
+ fprintf(fp, "\t\t test dl,1H\t\t;check carry\n");\r
+ if (Condition)\r
+ {\r
+ fprintf(fp, "\t\t jnz near %s\n",Label);\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t jz near %s\n",Label);\r
+ }\r
+ break;\r
+\r
+ case 6: /* NE */\r
+ fprintf(fp, "\t\t test dl,40H\t\t;Check zero\n");\r
+ if (Condition)\r
+ {\r
+ fprintf(fp, "\t\t jz near %s\n",Label);\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t jnz near %s\n",Label);\r
+ }\r
+ break;\r
+\r
+ case 7: /* EQ */\r
+ fprintf(fp, "\t\t test dl,40H\t\t;Check zero\n");\r
+ if (Condition)\r
+ {\r
+ fprintf(fp, "\t\t jnz near %s\n",Label);\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t jz near %s\n",Label);\r
+ }\r
+ break;\r
+\r
+ case 8: /* VC */\r
+ fprintf(fp, "\t\t test dh,8H\t\t;Check Overflow\n");\r
+ if (Condition)\r
+ {\r
+ fprintf(fp, "\t\t jz near %s\n", Label);\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t jnz near %s\n", Label);\r
+ }\r
+ break;\r
+\r
+ case 9: /* VS */\r
+ fprintf(fp, "\t\t test dh,8H\t\t;Check Overflow\n");\r
+ if (Condition)\r
+ {\r
+ fprintf(fp, "\t\t jnz near %s\n", Label);\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t jz near %s\n", Label);\r
+ }\r
+ break;\r
+\r
+ case 10: /* PL */\r
+ fprintf(fp,"\t\t test dl,80H\t\t;Check Sign\n");\r
+ if (Condition)\r
+ {\r
+ fprintf(fp, "\t\t jz near %s\n", Label);\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t jnz near %s\n", Label);\r
+ }\r
+ break;\r
+\r
+ case 11: /* MI */\r
+ fprintf(fp,"\t\t test dl,80H\t\t;Check Sign\n");\r
+ if (Condition)\r
+ {\r
+ fprintf(fp, "\t\t jnz near %s\n", Label);\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t jz near %s\n", Label);\r
+ }\r
+ break;\r
+\r
+ case 12: /* GE */\r
+ fprintf(fp, "\t\t or edx,200h\n");\r
+ fprintf(fp, "\t\t push edx\n");\r
+ fprintf(fp, "\t\t popf\n");\r
+ if (Condition)\r
+ {\r
+ fprintf(fp, "\t\t jge near %s\n",Label);\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t jl near %s\n",Label);\r
+ }\r
+ break;\r
+\r
+ case 13: /* LT */\r
+ fprintf(fp, "\t\t or edx,200h\n");\r
+ fprintf(fp, "\t\t push edx\n");\r
+ fprintf(fp, "\t\t popf\n");\r
+ if (Condition)\r
+ {\r
+ fprintf(fp, "\t\t jl near %s\n",Label);\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t jge near %s\n",Label);\r
+ }\r
+ break;\r
+\r
+ case 14: /* GT */\r
+ fprintf(fp, "\t\t or edx,200h\n");\r
+ fprintf(fp, "\t\t push edx\n");\r
+ fprintf(fp, "\t\t popf\n");\r
+ if (Condition)\r
+ {\r
+ fprintf(fp, "\t\t jg near %s\n",Label);\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t jle near %s\n",Label);\r
+ }\r
+ break;\r
+\r
+ case 15: /* LE */\r
+ fprintf(fp, "\t\t or edx,200h\n");\r
+ fprintf(fp, "\t\t push edx\n");\r
+ fprintf(fp, "\t\t popf\n");\r
+ if (Condition)\r
+ {\r
+ fprintf(fp, "\t\t jle near %s\n",Label);\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t jg near %s\n",Label);\r
+ }\r
+ break;\r
+ }\r
+\r
+ return Label;\r
+}\r
+\r
+/*\r
+ * mode = condition to check for\r
+ * SetWhat = text for assembler command (usually AL or address descriptor)\r
+ *\r
+ * Some conditions clobber AH\r
+ */\r
+\r
+void ConditionCheck(int mode, char *SetWhat)\r
+{\r
+ switch (mode)\r
+ {\r
+\r
+ case 0: /* A - Always */\r
+ fprintf(fp, "\t\t mov %s,byte 0ffh\n",SetWhat);\r
+ break;\r
+\r
+ case 1: /* F - Never */\r
+ if (SetWhat[1] == 'L')\r
+ {\r
+ ClearRegister(EAX);\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t mov %s,byte 0h\n",SetWhat);\r
+ }\r
+ break;\r
+\r
+ case 2: /* Hi */\r
+ fprintf(fp, "\t\t mov ah,dl\n");\r
+ fprintf(fp, "\t\t sahf\n");\r
+ fprintf(fp, "\t\t seta %s\n",SetWhat);\r
+ fprintf(fp, "\t\t neg byte %s\n",SetWhat);\r
+ break;\r
+\r
+ case 3: /* Ls */\r
+ fprintf(fp, "\t\t mov ah,dl\n");\r
+ fprintf(fp, "\t\t sahf\n");\r
+ fprintf(fp, "\t\t setbe %s\n",SetWhat);\r
+ fprintf(fp, "\t\t neg byte %s\n",SetWhat);\r
+ break;\r
+\r
+ case 4: /* CC */\r
+ fprintf(fp, "\t\t test dl,1\t\t;Check Carry\n");\r
+ fprintf(fp, "\t\t setz %s\n",SetWhat);\r
+ fprintf(fp, "\t\t neg byte %s\n",SetWhat);\r
+ break;\r
+\r
+ case 5: /* CS */\r
+ fprintf(fp, "\t\t test dl,1\t\t;Check Carry\n");\r
+ fprintf(fp, "\t\t setnz %s\n",SetWhat);\r
+ fprintf(fp, "\t\t neg byte %s\n",SetWhat);\r
+ break;\r
+\r
+ case 6: /* NE */\r
+ fprintf(fp, "\t\t test dl,40H\t\t;Check Zero\n");\r
+ fprintf(fp, "\t\t setz %s\n",SetWhat);\r
+ fprintf(fp, "\t\t neg byte %s\n",SetWhat);\r
+ break;\r
+\r
+ case 7: /* EQ */\r
+ fprintf(fp, "\t\t test dl,40H\t\t;Check Zero\n");\r
+ fprintf(fp, "\t\t setnz %s\n",SetWhat);\r
+ fprintf(fp, "\t\t neg byte %s\n",SetWhat);\r
+ break;\r
+\r
+ case 8: /* VC */\r
+ fprintf(fp, "\t\t test dh,8H\t\t;Check Overflow\n");\r
+ fprintf(fp, "\t\t setz %s\n",SetWhat);\r
+ fprintf(fp, "\t\t neg byte %s\n",SetWhat);\r
+ break;\r
+\r
+ case 9: /* VS */\r
+ fprintf(fp, "\t\t test dh,8H\t\t;Check Overflow\n");\r
+ fprintf(fp, "\t\t setnz %s\n",SetWhat);\r
+ fprintf(fp, "\t\t neg byte %s\n",SetWhat);\r
+ break;\r
+\r
+ case 10: /* PL */\r
+ fprintf(fp, "\t\t test dl,80H\t\t;Check Sign\n");\r
+ fprintf(fp, "\t\t setz %s\n",SetWhat);\r
+ fprintf(fp, "\t\t neg byte %s\n",SetWhat);\r
+ break;\r
+\r
+ case 11: /* MI */\r
+ fprintf(fp, "\t\t test dl,80H\t\t;Check Sign\n");\r
+ fprintf(fp, "\t\t setnz %s\n",SetWhat);\r
+ fprintf(fp, "\t\t neg byte %s\n",SetWhat);\r
+ break;\r
+\r
+ case 12: /* GE */\r
+ fprintf(fp, "\t\t or edx,200h\n");\r
+ fprintf(fp, "\t\t push edx\n");\r
+ fprintf(fp, "\t\t popf\n");\r
+ fprintf(fp, "\t\t setge %s\n",SetWhat);\r
+ fprintf(fp, "\t\t neg byte %s\n",SetWhat);\r
+ break;\r
+\r
+ case 13: /* LT */\r
+ fprintf(fp, "\t\t or edx,200h\n");\r
+ fprintf(fp, "\t\t push edx\n");\r
+ fprintf(fp, "\t\t popf\n");\r
+ fprintf(fp, "\t\t setl %s\n",SetWhat);\r
+ fprintf(fp, "\t\t neg byte %s\n",SetWhat);\r
+ break;\r
+\r
+ case 14: /* GT */\r
+ fprintf(fp, "\t\t or edx,200h\n");\r
+ fprintf(fp, "\t\t push edx\n");\r
+ fprintf(fp, "\t\t popf\n");\r
+ fprintf(fp, "\t\t setg %s\n",SetWhat);\r
+ fprintf(fp, "\t\t neg byte %s\n",SetWhat);\r
+ break;\r
+\r
+ case 15: /* LE */\r
+ fprintf(fp, "\t\t or edx,200h\n");\r
+ fprintf(fp, "\t\t push edx\n");\r
+ fprintf(fp, "\t\t popf\n");\r
+ fprintf(fp, "\t\t setle %s\n",SetWhat);\r
+ fprintf(fp, "\t\t neg byte %s\n",SetWhat);\r
+ break;\r
+ }\r
+}\r
+\r
+\r
+/**********************************************************************/\r
+/* Instructions - Each routine generates a range of instruction codes */\r
+/**********************************************************************/\r
+\r
+/*\r
+ * Immediate Commands\r
+ *\r
+ * ORI 00xx\r
+ * ANDI 02xx\r
+ * SUBI 04xx\r
+ * ADDI 06xx\r
+ * EORI 0axx\r
+ * CMPI 0cxx\r
+ *\r
+ */\r
+\r
+void dump_imm( int type, int leng, int mode, int sreg )\r
+{\r
+ int Opcode,BaseCode ;\r
+ char Size=' ' ;\r
+ char * RegnameEBX="" ;\r
+ char * Regname="" ;\r
+ char * OpcodeName[16] = {"or ", "and", "sub", "add",0,"xor","cmp",0} ;\r
+ int allow[] = {1,0,1,1, 1,1,1,1, 1,0,0,0, 0,0,0,0, 0,0,0,1, 1} ;\r
+\r
+ Opcode = (type << 9) | ( leng << 6 ) | ( mode << 3 ) | sreg;\r
+\r
+ BaseCode = Opcode & 0xfff8;\r
+\r
+ if (mode == 7) BaseCode |= sreg ;\r
+\r
+#ifdef A7ROUTINE\r
+ if ((leng == 0) && (sreg == 7) && (mode > 2) && (mode < 5))\r
+ {\r
+ BaseCode |= sreg ;\r
+ }\r
+#endif\r
+\r
+ if (type != 4) /* Not Valid (for this routine) */\r
+ {\r
+ int Dest = EAtoAMN(Opcode, FALSE);\r
+ int SetX;\r
+\r
+ /* ADDI & SUBI also set X flag */\r
+\r
+ SetX = ((type == 2) || (type == 3));\r
+\r
+ switch (leng)\r
+ {\r
+ case 0:\r
+ Size = 'B';\r
+ Regname = regnamesshort[0];\r
+ RegnameEBX = regnamesshort[EBX];\r
+ break;\r
+ case 1:\r
+ Size = 'W';\r
+ Regname = regnamesword[0];\r
+ RegnameEBX = regnamesword[EBX];\r
+ break;\r
+ case 2:\r
+ Size = 'L';\r
+ Regname = regnameslong[0];\r
+ RegnameEBX = regnameslong[EBX];\r
+ break;\r
+ }\r
+\r
+ if (allow[Dest])\r
+ {\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ /* Save Previous PC if Memory Access */\r
+\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ if (mode < 2)\r
+ {\r
+ if (Size != 'L')\r
+ TimingCycles += (CPU==2) ? 4 : 8;\r
+ else\r
+ {\r
+ TimingCycles += (CPU==2) ? 8 : 14;\r
+ if ((type != 1) && (type!=6))\r
+ TimingCycles += 2 ;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (type != 6)\r
+ {\r
+ if (Size != 'L')\r
+ TimingCycles += (CPU==2) ? 4 : 12 ;\r
+ else\r
+ TimingCycles += (CPU==2) ? 4 : 20 ;\r
+ }\r
+ else\r
+ {\r
+ if (Size != 'L')\r
+ TimingCycles += (CPU==2) ? 4 : 8 ;\r
+ else\r
+ TimingCycles += (CPU==2) ? 4 : 12 ;\r
+ }\r
+ }\r
+\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+\r
+ /* Immediate Mode Data */\r
+ EffectiveAddressRead(11,Size,EBX,EBX,"--C-S-B",FALSE);\r
+\r
+ /* Source Data */\r
+ EffectiveAddressRead(Dest,Size,ECX,EAX,"-BC-SDB",FALSE);\r
+\r
+ /* The actual work */\r
+ fprintf(fp, "\t\t %s %s,%s\n", OpcodeName[type], Regname, RegnameEBX );\r
+\r
+ SetFlags(Size,EAX,FALSE,SetX,TRUE);\r
+\r
+ if (type != 6) /* CMP no update */\r
+ EffectiveAddressWrite(Dest,Size,ECX,EAX,"---DS-B",FALSE);\r
+\r
+ Completed();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Logicals are allowed to alter SR/CCR */\r
+\r
+ if ((!SetX) && (Dest == 11) && (Size != 'L') && (type != 6))\r
+ {\r
+ Align();\r
+\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+ TimingCycles += 20 ;\r
+\r
+ if (Size=='W')\r
+ {\r
+ /* If SR then must be in Supervisor Mode */\r
+\r
+ char *Label = GenerateLabel(0,1);\r
+\r
+ fprintf(fp, "\t\t test byte [%s],20h \t\t\t; Supervisor Mode ?\n",REG_SRH);\r
+ fprintf(fp, "\t\t jne near %s\n\n",Label);\r
+\r
+ /* User Mode - Exception */\r
+\r
+ Exception(8,BaseCode);\r
+\r
+ fprintf(fp, "%s:\n",Label);\r
+ }\r
+\r
+ /* Immediate Mode Data */\r
+ EffectiveAddressRead(11,Size,EBX,EBX,"---DS-B",TRUE);\r
+\r
+ ReadCCR(Size,ECX);\r
+\r
+ fprintf(fp, "\t\t %s %s,%s\n", OpcodeName[type], Regname, RegnameEBX );\r
+\r
+ WriteCCR(Size);\r
+\r
+ Completed();\r
+ }\r
+ else\r
+ {\r
+\r
+ /* Illegal Opcode */\r
+\r
+ OpcodeArray[BaseCode] = -1;\r
+ BaseCode = -1;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ BaseCode = -2;\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode;\r
+}\r
+\r
+void immediate(void)\r
+{\r
+ int type, size, mode, sreg ;\r
+\r
+ for (type = 0 ; type < 0x7; type++)\r
+ for (size = 0 ; size < 3 ; size++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ dump_imm( type, size, mode, sreg ) ;\r
+}\r
+\r
+\r
+/*\r
+ * Bitwise Codes\r
+ *\r
+ */\r
+\r
+void dump_bit_dynamic( int sreg, int type, int mode, int dreg )\r
+{\r
+ int Opcode, BaseCode ;\r
+ char Size ;\r
+ char *EAXReg,*ECXReg, *Label ;\r
+ char allow[] = "0-2345678-------" ;\r
+ int Dest ;\r
+\r
+ /* BTST allows x(PC) and x(PC,xr.s) - others do not */\r
+\r
+ if (type == 0)\r
+ {\r
+ allow[9] = '9';\r
+ allow[10] = 'a';\r
+ allow[11] = 'b'; // dave fix to nhl\r
+ }\r
+\r
+ Opcode = 0x0100 | (sreg << 9) | (type<<6) | (mode<<3) | dreg ;\r
+\r
+ BaseCode = Opcode & 0x01f8 ;\r
+ if (mode == 7) BaseCode |= dreg ;\r
+\r
+\r
+ // A7+, A7-\r
+\r
+#ifdef A7ROUTINE\r
+ if ((mode > 2) && (mode < 5))\r
+ {\r
+ if (dreg == 7) BaseCode |= dreg;\r
+ }\r
+#endif\r
+\r
+ Dest = EAtoAMN(Opcode, FALSE);\r
+\r
+ if (allow[Dest&0xf] != '-')\r
+ {\r
+ if (mode == 0) /* long*/\r
+ {\r
+ /* Modify register memory directly */\r
+\r
+ Size = 'L' ;\r
+ EAXReg = REG_DAT_EBX;\r
+ ECXReg = regnameslong[ECX];\r
+ }\r
+ else\r
+ {\r
+ Size = 'B' ;\r
+ EAXReg = regnamesshort[EAX];\r
+ ECXReg = regnamesshort[ECX];\r
+ }\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ /* Save Previous PC if Memory Access */\r
+\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ if (mode<2)\r
+ {\r
+ switch (type)\r
+ {\r
+ case 0:\r
+ TimingCycles += 6 ;\r
+ break;\r
+ case 1:\r
+ case 3:\r
+ TimingCycles += 8 ;\r
+ break;\r
+ case 2:\r
+ TimingCycles += 10;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (type==0)\r
+ TimingCycles += 4;\r
+ else\r
+ TimingCycles += 8;\r
+ }\r
+\r
+ /* Only need this sorted out if a register is involved */\r
+\r
+ if (Dest < 7)\r
+ {\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+ fprintf(fp, "\t\t and ebx,byte 7\n");\r
+ }\r
+\r
+ /* Get bit number and create mask in ECX */\r
+\r
+ fprintf(fp, "\t\t shr ecx, byte 9\n");\r
+ fprintf(fp, "\t\t and ecx, byte 7\n");\r
+ fprintf(fp, "\t\t mov ecx, [%s+ECX*4]\n",REG_DAT);\r
+\r
+ if (Size == 'L')\r
+ fprintf(fp, "\t\t and ecx, byte 31\n");\r
+ else\r
+ fprintf(fp, "\t\t and ecx, byte 7\n");\r
+\r
+ #ifdef QUICKZERO\r
+ fprintf(fp,"\t\t mov eax,1\n");\r
+ #else\r
+ fprintf(fp,"\t\t xor eax,eax\n");\r
+ fprintf(fp,"\t\t inc eax\n");\r
+ #endif\r
+\r
+ fprintf(fp,"\t\t shl eax,cl\n");\r
+ fprintf(fp,"\t\t mov ecx,eax\n");\r
+\r
+ if (mode != 0)\r
+ EffectiveAddressRead(Dest,Size,EBX,EAX,"-BCDSDB",TRUE);\r
+\r
+\r
+ /* All commands copy existing bit to Zero Flag */\r
+\r
+ Label = GenerateLabel(0,1);\r
+\r
+ fprintf(fp,"\t\t or edx,byte 40h\t; Set Zero Flag\n");\r
+ fprintf(fp,"\t\t test %s,%s\n",EAXReg,ECXReg);\r
+ fprintf(fp,"\t\t jz short %s\n",Label);\r
+ fprintf(fp,"\t\t xor edx,byte 40h\t; Clear Zero Flag\n");\r
+ fprintf(fp,"%s:\n",Label);\r
+\r
+ /* Some then modify the data */\r
+\r
+ switch (type)\r
+ {\r
+ case 0: /* btst*/\r
+ break;\r
+\r
+ case 1: /* bchg*/\r
+ fprintf(fp,"\t\t xor %s,%s\n",EAXReg,ECXReg);\r
+ break;\r
+\r
+ case 2: /* bclr*/\r
+ fprintf(fp,"\t\t not ecx\n");\r
+ fprintf(fp,"\t\t and %s,%s\n",EAXReg,ECXReg);\r
+ break;\r
+\r
+ case 3: /* bset*/\r
+ fprintf(fp,"\t\t or %s,%s\n",EAXReg,ECXReg);\r
+ break;\r
+ }\r
+\r
+ if ((mode !=0) && (type != 0))\r
+ EffectiveAddressWrite(Dest,Size,EBX,FALSE,"---DS-B",TRUE);\r
+\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+}\r
+\r
+void bitdynamic(void) /* dynamic non-immediate bit operations*/\r
+{\r
+ int type, sreg, mode, dreg ;\r
+\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ for (type = 0 ; type < 4 ; type++)\r
+ for (mode = 0 ; mode < 8 ;mode++)\r
+ for (dreg = 0 ; dreg < 8 ;dreg++)\r
+ dump_bit_dynamic( sreg, type, mode, dreg ) ;\r
+}\r
+\r
+void dump_bit_static(int type, int mode, int dreg )\r
+{\r
+ int Opcode, BaseCode ;\r
+ char Size ;\r
+ char *EAXReg,*ECXReg, *Label ;\r
+ char allow[] = "0-2345678-------" ;\r
+ int Dest ;\r
+\r
+ /* BTST allows x(PC) and x(PC,xr.s) - others do not */\r
+\r
+ if (type == 0)\r
+ {\r
+ allow[9] = '9';\r
+ allow[10] = 'a';\r
+ }\r
+\r
+ Opcode = 0x0800 | (type<<6) | (mode<<3) | dreg ;\r
+ BaseCode = Opcode & 0x08f8 ;\r
+ if (mode == 7) BaseCode |= dreg ;\r
+\r
+ // A7+, A7-\r
+\r
+#ifdef A7ROUTINE\r
+ if ((mode > 2) && (mode < 5))\r
+ {\r
+ if (dreg == 7) BaseCode |= dreg;\r
+ }\r
+#endif\r
+\r
+ Dest = EAtoAMN(Opcode, FALSE);\r
+\r
+ if (allow[Dest&0xf] != '-')\r
+ {\r
+ if (mode == 0) /* long*/\r
+ {\r
+ /* Modify register memory directly */\r
+\r
+ Size = 'L' ;\r
+ EAXReg = REG_DAT_EBX;\r
+ ECXReg = regnameslong[ECX];\r
+ }\r
+ else\r
+ {\r
+ Size = 'B' ;\r
+ EAXReg = regnamesshort[EAX];\r
+ ECXReg = regnamesshort[ECX];\r
+ }\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ /* Save Previous PC if Memory Access */\r
+\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ if (mode<2)\r
+ {\r
+ switch (type)\r
+ {\r
+ case 0:\r
+ TimingCycles += 10 ;\r
+ break ;\r
+ case 1:\r
+ case 3:\r
+ TimingCycles += 12 ;\r
+ break ;\r
+ case 2:\r
+ TimingCycles += 14 ;\r
+ break ;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (type != 0)\r
+ TimingCycles += 12 ;\r
+ else\r
+ TimingCycles += 8 ;\r
+ }\r
+\r
+ /* Only need this sorted out if a register is involved */\r
+\r
+ if (Dest < 7)\r
+ {\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+ fprintf(fp, "\t\t and ebx, byte 7\n");\r
+ }\r
+\r
+ /* Get bit number and create mask in ECX */\r
+\r
+ Memory_Fetch('W',ECX,FALSE);\r
+ fprintf(fp, "\t\t add esi,byte 2\n");\r
+\r
+ if (Size == 'L')\r
+ fprintf(fp, "\t\t and ecx, byte 31\n");\r
+ else\r
+ fprintf(fp, "\t\t and ecx, byte 7\n");\r
+\r
+ #ifdef QUICKZERO\r
+ fprintf(fp,"\t\t mov eax,1\n");\r
+ #else\r
+ fprintf(fp,"\t\t xor eax,eax\n");\r
+ fprintf(fp,"\t\t inc eax\n");\r
+ #endif\r
+\r
+ fprintf(fp,"\t\t shl eax,cl\n");\r
+ fprintf(fp,"\t\t mov ecx,eax\n");\r
+\r
+ if (mode != 0)\r
+ EffectiveAddressRead(Dest,Size,EBX,EAX,"-BCDSDB",TRUE);\r
+\r
+ /* All commands copy existing bit to Zero Flag */\r
+\r
+ Label = GenerateLabel(0,1);\r
+\r
+ fprintf(fp,"\t\t or edx,byte 40h\t; Set Zero Flag\n");\r
+ fprintf(fp,"\t\t test %s,%s\n",EAXReg,ECXReg);\r
+ fprintf(fp,"\t\t jz short %s\n",Label);\r
+ fprintf(fp,"\t\t xor edx,byte 40h\t; Clear Zero Flag\n");\r
+ fprintf(fp,"%s:\n",Label);\r
+\r
+ /* Some then modify the data */\r
+\r
+ switch (type)\r
+ {\r
+ case 0: /* btst*/\r
+ break;\r
+\r
+ case 1: /* bchg*/\r
+ fprintf(fp,"\t\t xor %s,%s\n",EAXReg,ECXReg);\r
+ break;\r
+\r
+ case 2: /* bclr*/\r
+ fprintf(fp,"\t\t not ecx\n");\r
+ fprintf(fp,"\t\t and %s,%s\n",EAXReg,ECXReg);\r
+ break;\r
+\r
+ case 3: /* bset*/\r
+ fprintf(fp,"\t\t or %s,%s\n",EAXReg,ECXReg);\r
+ break;\r
+ }\r
+\r
+ if ((mode !=0) && (type != 0))\r
+ EffectiveAddressWrite(Dest,Size,EBX,FALSE,"---DS-B",TRUE);\r
+\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+}\r
+\r
+\r
+void bitstatic(void) /* static non-immediate bit operations*/\r
+{\r
+ int type, mode, dreg ;\r
+\r
+ for (type = 0 ; type < 4 ; type++)\r
+ for (mode = 0 ; mode < 8 ;mode++)\r
+ for (dreg = 0 ; dreg < 8 ;dreg++)\r
+ dump_bit_static( type, mode, dreg ) ;\r
+}\r
+\r
+/*\r
+ * Move Peripheral\r
+ *\r
+ */\r
+\r
+void movep(void)\r
+{\r
+ int sreg,dir,leng,dreg ;\r
+ int Opcode, BaseCode ;\r
+\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ for (dir = 0 ; dir < 2 ; dir++)\r
+ {\r
+ for (leng = 0 ; leng < 2 ; leng++)\r
+ {\r
+ for (dreg = 0 ; dreg < 8 ; dreg++)\r
+ {\r
+ Opcode = 0x0108 | (sreg<<9) | (dir<<7) | (leng<<6) | dreg;\r
+ BaseCode = Opcode & 0x01c8 ;\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ SavePreviousPC();\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ if (leng == 0) /* word */\r
+ TimingCycles += 16 ;\r
+ else\r
+ TimingCycles += 24 ;\r
+\r
+ /* Save Flags Register (so we only do it once) */\r
+\r
+ fprintf(fp, "\t\t push edx\n");\r
+\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+ fprintf(fp, "\t\t and ebx,byte 7\n");\r
+\r
+ /* Get Address to Read/Write in EDI */\r
+\r
+ EffectiveAddressCalculate(5,'L',EBX,FALSE);\r
+\r
+ fprintf(fp, "\t\t shr ecx,byte 9\n");\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+\r
+\r
+ if (dir == 0) /* from memory to register*/\r
+ {\r
+ Memory_Read('B',EDI,"-BC-SDB",2); /* mask first call */\r
+ fprintf(fp,"\t\t mov bh,al\n");\r
+ fprintf(fp,"\t\t add edi,byte 2\n");\r
+ Memory_Read('B',EDI,"-BC-SDB",0); /* not needed then */\r
+ fprintf(fp,"\t\t mov bl,al\n");\r
+\r
+ if (leng == 0) /* word d(Ax) into Dx.W*/\r
+ {\r
+ fprintf(fp,"\t\t mov [%s+ecx*4],bx\n",REG_DAT);\r
+ }\r
+ else /* long d(Ax) into Dx.L*/\r
+ {\r
+ fprintf(fp,"\t\t add edi,byte 2\n");\r
+ fprintf(fp,"\t\t shl ebx,16\n");\r
+ Memory_Read('B',EDI,"-BC-SDB",0);\r
+ fprintf(fp,"\t\t mov bh,al\n");\r
+ fprintf(fp,"\t\t add edi,byte 2\n");\r
+ Memory_Read('B',EDI,"-BC-S-B",0);\r
+ fprintf(fp,"\t\t mov bl,al\n");\r
+ fprintf(fp,"\t\t mov [%s+ecx*4],ebx\n",REG_DAT);\r
+ }\r
+ }\r
+ else /* Register to Memory*/\r
+ {\r
+ fprintf(fp,"\t\t mov eax,[%s+ecx*4]\n",REG_DAT);\r
+\r
+ /* Move bytes into Line */\r
+\r
+ if (leng == 1)\r
+ fprintf(fp,"\t\t rol eax,byte 8\n");\r
+ else\r
+ fprintf(fp,"\t\t rol eax,byte 24\n");\r
+\r
+ Memory_Write('B',EDI,EAX,"A---SDB",2); /* Mask First */\r
+ fprintf(fp,"\t\t add edi,byte 2\n");\r
+ fprintf(fp,"\t\t rol eax,byte 8\n");\r
+\r
+ if (leng == 1) /* long*/\r
+ {\r
+ Memory_Write('B',EDI,EAX,"A---SDB",0);\r
+ fprintf(fp,"\t\t add edi,byte 2\n");\r
+ fprintf(fp,"\t\t rol eax,byte 8\n");\r
+ Memory_Write('B',EDI,EAX,"A---SDB",0);\r
+ fprintf(fp,"\t\t add edi,byte 2\n");\r
+ fprintf(fp,"\t\t rol eax,byte 8\n");\r
+ }\r
+ Memory_Write('B',EDI,EAX,"A---S-B",0);\r
+ }\r
+\r
+ fprintf(fp, "\t\t pop edx\n");\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+void movecodes(int allowfrom[],int allowto[],int Start,char Size) /* MJC */\r
+{\r
+ int Opcode;\r
+ int Src,Dest;\r
+ int SaveEDX;\r
+ int BaseCode;\r
+\r
+ for (Opcode=Start;Opcode<Start+0x1000;Opcode++)\r
+ {\r
+ /* Mask our Registers */\r
+\r
+ BaseCode = Opcode & (Start + 0x1f8);\r
+\r
+ /* Unless Mode = 7 */\r
+\r
+ if ((BaseCode & 0x38) == 0x38) BaseCode |= (Opcode & 7);\r
+ if ((BaseCode & 0x1c0) == 0x1c0) BaseCode |= (Opcode & 0xE00);\r
+\r
+ /* If mode = 3 or 4 and Size = byte and register = A7 */\r
+ /* then make it a separate code */\r
+\r
+#ifdef A7ROUTINE\r
+ if (Size == 'B')\r
+ {\r
+ if (((Opcode & 0x3F) == 0x1F) || ((Opcode & 0x3F) == 0x27))\r
+ {\r
+ BaseCode |= 0x07;\r
+ }\r
+\r
+ if (((Opcode & 0xFC0) == 0xEC0) || ((Opcode & 0xFC0) == 0xF00))\r
+ {\r
+ BaseCode |= 0x0E00;\r
+ }\r
+ }\r
+#endif\r
+\r
+ /* If Source = Data or Address register - combine into same routine */\r
+\r
+ if (((Opcode & 0x38) == 0x08) && (allowfrom[1]))\r
+ {\r
+ BaseCode &= 0xfff7;\r
+ }\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Src = EAtoAMN(Opcode, FALSE);\r
+ Dest = EAtoAMN(Opcode >> 6, TRUE);\r
+\r
+ if ((allowfrom[(Src & 15)]) && (allowto[(Dest & 15)]))\r
+ {\r
+ /* If we are not going to calculate the flags */\r
+ /* we need to preserve the existing ones */\r
+\r
+ SaveEDX = (Dest == 1);\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ if (((Src >= 2) && (Src <= 10)) || ((Dest >= 2) && (Dest <=10)))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+\r
+ TimingCycles += 4 ;\r
+\r
+ if (Src < 7)\r
+ {\r
+ if (Dest < 7)\r
+ {\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+\r
+ if ((Src == 0) && allowfrom[1])\r
+ fprintf(fp, "\t\t and ebx,byte 15\n");\r
+ else\r
+ fprintf(fp, "\t\t and ebx,byte 7\n");\r
+\r
+ EffectiveAddressRead(Src,Size,EBX,EAX,"--CDS-B",SaveEDX);\r
+ }\r
+ else\r
+ {\r
+ if ((Src == 0) && allowfrom[1])\r
+ fprintf(fp, "\t\t and ecx,byte 15\n");\r
+ else\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+\r
+ EffectiveAddressRead(Src,Size,ECX,EAX,"---DS-B",SaveEDX);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (Dest < 7)\r
+ EffectiveAddressRead(Src,Size,EBX,EAX,"--CDS-B",SaveEDX);\r
+ else\r
+ EffectiveAddressRead(Src,Size,EBX,EAX,"---DS-B",SaveEDX);\r
+ }\r
+\r
+ /* No flags if Destination Ax */\r
+\r
+ if (!SaveEDX)\r
+ {\r
+ SetFlags(Size,EAX,TRUE,FALSE,TRUE);\r
+ }\r
+\r
+ if (Dest < 7)\r
+ {\r
+ fprintf(fp, "\t\t shr ecx,9\n");\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ }\r
+\r
+ EffectiveAddressWrite(Dest,Size,ECX,TRUE,"---DS-B",SaveEDX);\r
+\r
+ Completed();\r
+ }\r
+ else\r
+ {\r
+ BaseCode = -1; /* Invalid Code */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ BaseCode = OpcodeArray[BaseCode];\r
+ }\r
+\r
+ if (OpcodeArray[Opcode] < 0)\r
+ OpcodeArray[Opcode] = BaseCode;\r
+ }\r
+}\r
+\r
+void moveinstructions(void)\r
+{\r
+ int allowfrom[] = {1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0};\r
+ int allowto[] = {1,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0};\r
+\r
+ /* For Byte */\r
+\r
+ movecodes(allowfrom,allowto,0x1000,'B');\r
+\r
+ /* For Word & Long */\r
+\r
+ allowto[1] = 1;\r
+ movecodes(allowfrom,allowto,0x2000,'L');\r
+ movecodes(allowfrom,allowto,0x3000,'W');\r
+}\r
+\r
+/*\r
+ *\r
+ * Opcodes 5###\r
+ *\r
+ * ADDQ,SUBQ,Scc and DBcc\r
+ *\r
+ */\r
+\r
+void opcode5(void)\r
+{\r
+ /* ADDQ,SUBQ,Scc and DBcc */\r
+\r
+ int allowtoScc[] = {1,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0};\r
+ int allowtoADDQ[] = {1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0};\r
+ int Opcode,BaseCode;\r
+ char Label[32];\r
+ char Label2[32];\r
+ char Size=' ';\r
+ char* Regname="";\r
+ char* RegnameECX="";\r
+\r
+ for (Opcode = 0x5000;Opcode < 0x6000;Opcode++)\r
+ {\r
+ if ((Opcode & 0xc0) == 0xc0)\r
+ {\r
+ /* Scc or DBcc */\r
+\r
+ BaseCode = Opcode & 0x5FF8;\r
+ if ((BaseCode & 0x38) == 0x38) BaseCode |= (Opcode & 7);\r
+\r
+ /* If mode = 3 or 4 and register = A7 */\r
+ /* then make it a separate code */\r
+\r
+#ifdef A7ROUTINE\r
+ if (((Opcode & 0x3F) == 0x1F) || ((Opcode & 0x3F) == 0x27))\r
+ {\r
+ BaseCode |= 0x07;\r
+ }\r
+#endif\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ OpcodeArray[BaseCode] = BaseCode;\r
+\r
+ if ((BaseCode & 0x38) == 0x8)\r
+ {\r
+ /* DBcc */\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ TimingCycles += 10 ;\r
+\r
+\r
+ strcpy(Label,GenerateLabel(BaseCode,1)) ;\r
+ strcpy(Label2,ConditionDecode((Opcode >> 8) & 0x0F,TRUE));\r
+\r
+ /* False - Decrement Counter - Loop if not -1 */\r
+\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ fprintf(fp, "\t\t mov ax,[%s+ecx*4]\n",REG_DAT);\r
+ fprintf(fp, "\t\t dec ax\n");\r
+ fprintf(fp, "\t\t mov [%s+ecx*4],ax\n",REG_DAT);\r
+ fprintf(fp, "\t\t inc ax\t\t; Is it -1\n");\r
+ fprintf(fp, "\t\t jz short %s\n",Label);\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+ Memory_Fetch('W',EAX,TRUE);\r
+ fprintf(fp, "\t\t add esi,eax\n");\r
+ Completed();\r
+\r
+ /* True - Exit Loop */\r
+ fprintf(fp, "%s:\n",Label);\r
+\r
+ fprintf(fp, "%s:\n",Label2);\r
+ fprintf(fp, "\t\t add esi,byte 4\n");\r
+ TimingCycles += 2 ;\r
+\r
+ Completed();\r
+ }\r
+ else\r
+ {\r
+ /* Scc */\r
+\r
+ int Dest = EAtoAMN(Opcode, FALSE);\r
+\r
+ if (allowtoScc[(Dest & 15)])\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ if (Dest > 1)\r
+ TimingCycles += 8 ;\r
+ else\r
+ TimingCycles += 4 ;\r
+\r
+ if (Dest < 7)\r
+ {\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ }\r
+\r
+ if (Dest > 1)\r
+ {\r
+ EffectiveAddressCalculate(Dest,'B',ECX,TRUE);\r
+ /* ASG - no longer need to mask addresses here */\r
+/* fprintf(fp,"\t\t and edi,0FFFFFFh\n");*/\r
+ }\r
+\r
+ ConditionCheck((Opcode >> 8) & 0x0F,"AL");\r
+\r
+ EffectiveAddressWrite(Dest,'B',ECX,FALSE,"---DS-B",TRUE);\r
+\r
+ /* take advantage of AL being 0 for false, 0xff for true */\r
+ /* need to add 2 cycles if register and condition is true */\r
+\r
+ if (Dest == 0)\r
+ {\r
+ fprintf(fp, "\t\t and eax,byte 2\n");\r
+ fprintf(fp, "\t\t add eax,byte %d\n",TimingCycles);\r
+ fprintf(fp, "\t\t sub dword [%s],eax\n",ICOUNT);\r
+\r
+ TimingCycles = -1;\r
+ }\r
+ Completed();\r
+ }\r
+ else\r
+ {\r
+ OpcodeArray[BaseCode] = -1;\r
+ BaseCode = -1;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ BaseCode = OpcodeArray[BaseCode];\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode;\r
+ }\r
+ else\r
+ {\r
+ /* ADDQ or SUBQ */\r
+\r
+ BaseCode = Opcode & 0x51F8;\r
+ if ((BaseCode & 0x38) == 0x38) BaseCode |= (Opcode & 7);\r
+\r
+ /* Special for Address Register Direct - Force LONG */\r
+\r
+ if ((Opcode & 0x38) == 0x8) BaseCode = ((BaseCode & 0xFF3F) | 0x80);\r
+\r
+\r
+ /* If mode = 3 or 4 and Size = byte and register = A7 */\r
+ /* then make it a separate code */\r
+\r
+#ifdef A7ROUTINE\r
+ if ((Opcode & 0xC0) == 0)\r
+ {\r
+ if (((Opcode & 0x3F) == 0x1F) || ((Opcode & 0x3F) == 0x27))\r
+ {\r
+ BaseCode |= 0x07;\r
+ }\r
+ }\r
+#endif\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ char *Operation;\r
+ int Dest = EAtoAMN(Opcode, FALSE);\r
+ int SaveEDX = (Dest == 1);\r
+\r
+ if (allowtoADDQ[(Dest & 15)])\r
+ {\r
+ switch (BaseCode & 0xC0)\r
+ {\r
+ case 0:\r
+ Size = 'B';\r
+ Regname = regnamesshort[0];\r
+ RegnameECX = regnamesshort[ECX];\r
+ break;\r
+\r
+ case 0x40:\r
+ Size = 'W';\r
+ Regname = regnamesword[0];\r
+ RegnameECX = regnamesword[ECX];\r
+ break;\r
+\r
+ case 0x80:\r
+ Size = 'L';\r
+ Regname = regnameslong[0];\r
+ RegnameECX = regnameslong[ECX];\r
+ break;\r
+ }\r
+\r
+ OpcodeArray[BaseCode] = BaseCode;\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ if (Dest == 0) /* write to Dx */\r
+ {\r
+ if (Size != 'L')\r
+ TimingCycles += 4 ;\r
+ else\r
+ TimingCycles += 8 ;\r
+ }\r
+\r
+ if (Dest == 1)\r
+ {\r
+ if ((Size == 'L') || (Opcode & 0x100)) /* if long or SUBQ */\r
+ TimingCycles += 8 ;\r
+ else\r
+ TimingCycles += 4 ;\r
+ }\r
+\r
+ if (Dest > 1) /* write to mem */\r
+ {\r
+ if (Size != 'L')\r
+ TimingCycles += 8 ;\r
+ else\r
+ TimingCycles += 12 ;\r
+ }\r
+\r
+ if (Dest < 7)\r
+ {\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+ fprintf(fp, "\t\t and ebx,byte 7\n");\r
+ }\r
+\r
+ if (Dest > 1)\r
+ {\r
+ EffectiveAddressRead(Dest,Size,EBX,EAX,"-BCDSDB",SaveEDX);\r
+ }\r
+\r
+ /* Sub Immediate from Opcode */\r
+\r
+ fprintf(fp, "\t\t shr ecx,9\n");\r
+\r
+ Immediate8();\r
+\r
+ if (Opcode & 0x100)\r
+ {\r
+ /* SUBQ */\r
+ Operation = "sub";\r
+ }\r
+ else\r
+ {\r
+ /* ADDQ */\r
+ Operation = "add";\r
+ }\r
+\r
+ /* For Data or Address register, operate directly */\r
+ /* on the memory location. Don't load into EAX */\r
+\r
+ if (Dest < 2)\r
+ {\r
+ if (Dest == 0)\r
+ {\r
+ fprintf(fp, "\t\t %s [%s+ebx*4],%s\n",Operation,REG_DAT,RegnameECX);\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t %s [%s+ebx*4],%s\n",Operation,REG_ADD,RegnameECX);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t %s %s,%s\n",Operation,Regname,RegnameECX);\r
+ }\r
+\r
+ /* No Flags for Address Direct */\r
+\r
+ if (!SaveEDX)\r
+ {\r
+ /* Directly after ADD or SUB, so test not needed */\r
+\r
+ SetFlags(Size,EAX,FALSE,TRUE,TRUE);\r
+ }\r
+\r
+ if (Dest > 1)\r
+ {\r
+ EffectiveAddressWrite(Dest,Size,EBX,FALSE,"---DS-B",FALSE);\r
+ }\r
+\r
+ Completed();\r
+ }\r
+ else\r
+ {\r
+ OpcodeArray[BaseCode] = -1;\r
+ BaseCode = -1;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ BaseCode = OpcodeArray[BaseCode];\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode;\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * Branch Instructions\r
+ *\r
+ * BSR, Bcc\r
+ *\r
+ */\r
+\r
+void branchinstructions(void)\r
+{\r
+ int Opcode,BaseCode;\r
+ int Counter;\r
+ char *Label;\r
+ char jmpLabel[40] ;\r
+\r
+ for (Opcode = 0x60;Opcode < 0x70;Opcode++)\r
+ {\r
+ /* Displacement = 0 -> 16 Bit displacement */\r
+\r
+ BaseCode = Opcode * 0x100;\r
+ OpcodeArray[BaseCode] = BaseCode;\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 10 ;\r
+\r
+ if (Opcode == 0x60)\r
+ {\r
+ Memory_Fetch('W',EAX,TRUE);\r
+ fprintf(fp, "\t\t add esi,eax\n");\r
+ MemoryBanking(BaseCode);\r
+ Completed();\r
+ }\r
+ else\r
+ {\r
+ if (Opcode != 0x61)\r
+ {\r
+ Label = ConditionDecode(Opcode & 0x0F,TRUE);\r
+\r
+ /* Code for Failed branch */\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n");\r
+\r
+ /* 2 less cycles for Failure */\r
+\r
+ TimingCycles -= 2;\r
+ Completed();\r
+ TimingCycles += 2;\r
+\r
+ /* Successful Branch */\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",Label);\r
+\r
+ Memory_Fetch('W',EAX,TRUE);\r
+ fprintf(fp, "\t\t add esi,eax\n");\r
+ MemoryBanking(BaseCode+2);\r
+ Completed();\r
+\r
+ }\r
+ else\r
+ {\r
+ /* BSR - Special Case */\r
+\r
+ TimingCycles += 8 ;\r
+\r
+ Memory_Fetch('W',EBX,TRUE);\r
+ fprintf(fp, "\t\t add ebx,esi\n");\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n");\r
+ PushPC(ECX,EAX,"-B-DS-B",1);\r
+\r
+ fprintf(fp, "\t\t mov esi,ebx\n");\r
+ MemoryBanking(BaseCode+3);\r
+ Completed();\r
+ }\r
+ }\r
+\r
+ /* 8 Bit Displacement */\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode+1,0));\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 10 ;\r
+\r
+ if (Opcode > 0x60)\r
+ {\r
+ if (Opcode != 0x61)\r
+ {\r
+ Label = ConditionDecode(Opcode & 0x0F,TRUE);\r
+\r
+ /* Code for Failed branch */\r
+\r
+ TimingCycles -= 2;\r
+ Completed();\r
+ TimingCycles += 2;\r
+\r
+ /* Successful Branch */\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",Label);\r
+ }\r
+ else\r
+ {\r
+ /* BSR - Special Case */\r
+\r
+ TimingCycles += 8 ;\r
+\r
+ PushPC(EDI,EBX,"--CDS-B",1);\r
+ }\r
+ }\r
+\r
+ /* Common Ending */\r
+\r
+ fprintf(fp, "\t\t movsx eax,cl ; Sign Extend displacement\n");\r
+ fprintf(fp, "\t\t add esi,eax\n");\r
+ MemoryBanking(BaseCode+5);\r
+ Completed();\r
+\r
+ /* Fill up Opcode Array */\r
+\r
+ for (Counter=1;Counter<0x100;Counter++)\r
+ OpcodeArray[BaseCode+Counter] = BaseCode+1;\r
+\r
+ if(CPU==2)\r
+ {\r
+\r
+ /* 8 bit 0xff & 68020 instruction - 32 bit displacement */\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode+0xff,0));\r
+ sprintf( jmpLabel, GenerateLabel(BaseCode+0xff,1) ) ;\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 10 ;\r
+\r
+ if (Opcode == 0x60)\r
+ {\r
+ /* bra - always branch */\r
+ Memory_Fetch('L',EAX,FALSE);\r
+ fprintf(fp, "\t\t add esi,eax\n");\r
+ MemoryBanking(BaseCode+6);\r
+ Completed();\r
+ }\r
+ else\r
+ {\r
+ if (Opcode != 0x61)\r
+ {\r
+ Label = ConditionDecode(Opcode & 0x0F,TRUE);\r
+\r
+ /* Code for Failed branch */\r
+ fprintf(fp, "\t\t add esi,byte 4\n");\r
+\r
+ TimingCycles -= 2;\r
+ Completed();\r
+ TimingCycles += 2;\r
+\r
+ /* Successful Branch */\r
+ Align();\r
+ fprintf(fp, "%s:\n",Label);\r
+\r
+ Memory_Fetch('L',EAX,FALSE);\r
+ fprintf(fp, "\t\t add esi,eax\n");\r
+ MemoryBanking(BaseCode+8);\r
+ Completed();\r
+ }\r
+ else\r
+ {\r
+ /* BSR - Special Case */\r
+\r
+ TimingCycles += 8 ;\r
+\r
+ Memory_Fetch('L',EBX,TRUE);\r
+ fprintf(fp, "\t\t add ebx,esi\n");\r
+\r
+ fprintf(fp, "\t\t add esi,byte 4\n");\r
+ PushPC(ECX,EAX,"-B-DS-B",1);\r
+\r
+ fprintf(fp, "\t\t mov esi,ebx\n");\r
+ MemoryBanking(BaseCode+9);\r
+ Completed();\r
+ }\r
+ }\r
+\r
+ OpcodeArray[BaseCode+0xff] = BaseCode+0xff;\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * Move Quick Commands\r
+ *\r
+ * Fairly simple, as only allowed to Data Registers\r
+ *\r
+ */\r
+\r
+void moveq(void)\r
+{\r
+ int Count;\r
+\r
+ /* The Code */\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(0x7000,0));\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 4 ;\r
+\r
+ fprintf(fp, "\t\t movsx eax,cl\n");\r
+ fprintf(fp, "\t\t shr ecx,9\n");\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ SetFlags('L',EAX,TRUE,FALSE,FALSE);\r
+ EffectiveAddressWrite(0,'L',ECX,TRUE,"---DS-B",FALSE);\r
+ Completed();\r
+\r
+ /* Set OpcodeArray (Not strictly correct, since some are illegal!) */\r
+\r
+ for (Count=0x7000;Count<0x8000;Count++)\r
+ {\r
+ OpcodeArray[Count] = 0x7000;\r
+ }\r
+}\r
+\r
+/*\r
+ * Extended version of Add & Sub commands\r
+ *\r
+ */\r
+\r
+void addx_subx(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int regx,type,leng,rm,regy,mode ;\r
+ int ModeModX;\r
+ int ModeModY;\r
+ char Size=' ' ;\r
+ char * Regname="" ;\r
+ char * RegnameEBX="" ;\r
+ char * Operand="";\r
+ char * Label;\r
+\r
+ for (type = 0 ; type < 2 ; type ++) /* 0=subx, 1=addx */\r
+ for (regx = 0 ; regx < 8 ; regx++)\r
+ for (leng = 0 ; leng < 3 ; leng++)\r
+ for (rm = 0 ; rm < 2 ; rm++)\r
+ for (regy = 0 ; regy < 8 ; regy++)\r
+ {\r
+ Opcode = 0x9100 | (type<<14) | (regx<<9) | (leng<<6) | (rm<<3) | regy ;\r
+\r
+ BaseCode = Opcode & 0xd1c8 ;\r
+\r
+ ModeModX = 0;\r
+ ModeModY = 0;\r
+\r
+#ifdef A7ROUTINE\r
+ if ((rm == 1) && (leng == 0))\r
+ {\r
+ if (regx == 7)\r
+ {\r
+ BaseCode |= (regx << 9);\r
+ ModeModY = 16;\r
+ }\r
+ if (regy == 7)\r
+ {\r
+ BaseCode |= regy;\r
+ ModeModX = 16;\r
+ }\r
+ }\r
+#endif\r
+\r
+ if (rm == 0)\r
+ mode = 0 ;\r
+ else\r
+ mode = 4 ;\r
+\r
+ switch (leng)\r
+ {\r
+ case 0:\r
+ Size = 'B';\r
+ Regname = regnamesshort[0];\r
+ RegnameEBX = regnamesshort[EBX];\r
+ break;\r
+ case 1:\r
+ Size = 'W';\r
+ Regname = regnamesword[0];\r
+ RegnameEBX = regnamesword[EBX];\r
+ break;\r
+ case 2:\r
+ Size = 'L';\r
+ Regname = regnameslong[0];\r
+ RegnameEBX = regnameslong[EBX];\r
+ break;\r
+ }\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ if (type == 0)\r
+ Operand = "sbb";\r
+ else\r
+ Operand = "adc";\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ if (mode == 4)\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ /* don't add in EA timing for ADDX,SUBX */\r
+\r
+ AddEACycles = 0 ;\r
+\r
+ if (rm == 0) /* reg to reg */\r
+ {\r
+ if (Size != 'L')\r
+ TimingCycles += 4 ;\r
+ else\r
+ TimingCycles += 8 ;\r
+ }\r
+ else\r
+ {\r
+ if (Size != 'L')\r
+ TimingCycles += 18 ;\r
+ else\r
+ TimingCycles += 30 ;\r
+ }\r
+\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+ fprintf(fp, "\t\t and ebx, byte 7\n");\r
+ fprintf(fp, "\t\t shr ecx, byte 9\n");\r
+ fprintf(fp, "\t\t and ecx, byte 7\n");\r
+\r
+ /* Get Source */\r
+\r
+ EffectiveAddressRead(mode+ModeModX,Size,EBX,EBX,"--CDS-B",FALSE);\r
+\r
+ /* Get Destination (if needed) */\r
+\r
+ if (mode == 4)\r
+ EffectiveAddressRead(mode+ModeModY,Size,ECX,EAX,"-BCDSDB",FALSE);\r
+\r
+ /* Copy the X flag into the Carry Flag */\r
+\r
+ CopyX();\r
+\r
+ /* Do the sums */\r
+\r
+ if (mode == 0)\r
+ fprintf(fp, "\t\t %s [%s+ecx*4],%s\n",Operand,REG_DAT,RegnameEBX);\r
+ else\r
+ fprintf(fp, "\t\t %s %s,%s\n",Operand,Regname,RegnameEBX);\r
+\r
+ /* Preserve old Z flag */\r
+\r
+ fprintf(fp, "\t\t mov ebx,edx\n");\r
+\r
+ /* Set the Flags */\r
+\r
+ SetFlags(Size,EAX,FALSE,TRUE,FALSE);\r
+\r
+ /* Handle the Z flag */\r
+\r
+ Label = GenerateLabel(0,1);\r
+\r
+ fprintf(fp, "\t\t jnz short %s\n\n",Label);\r
+\r
+ fprintf(fp, "\t\t and dl,0BFh ; Remove Z\n");\r
+ fprintf(fp, "\t\t and bl,40h ; Mask out Old Z\n");\r
+ fprintf(fp, "\t\t or dl,bl ; Copy across\n\n");\r
+ fprintf(fp, "%s:\n",Label);\r
+\r
+ /* Update the Data (if needed) */\r
+\r
+ if (mode == 4)\r
+ EffectiveAddressWrite(mode,Size,ECX,FALSE,"---DS-B",TRUE);\r
+\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+}\r
+\r
+/*\r
+ * Logicals / Simple Maths (+ and -)\r
+ *\r
+ * OR,AND,CMP,EOR,ADD and SUB\r
+ *\r
+ */\r
+\r
+void dumpx( int start, int reg, int type, char * Op, int dir, int leng, int mode, int sreg )\r
+{\r
+ int Opcode,BaseCode ;\r
+ char Size=' ' ;\r
+ char * RegnameECX="" ;\r
+ char * Regname="" ;\r
+ int Dest ;\r
+ int SaveEDX ;\r
+ int SaveDir;\r
+ char * allow="" ;\r
+ char * allowtypes[] = { "0-23456789ab----", "--2345678-------",\r
+ "0123456789ab----", "0-2345678-------"};\r
+\r
+ SaveDir = dir;\r
+\r
+ switch (type)\r
+ {\r
+ case 0: /* or and*/\r
+ if (dir == 0)\r
+ allow = allowtypes[0];\r
+ else\r
+ allow = allowtypes[1];\r
+ break ;\r
+\r
+ case 1: /* cmp*/\r
+ allow = allowtypes[2] ;\r
+ break ;\r
+\r
+ case 2: /* eor*/\r
+ allow = allowtypes[3] ;\r
+ break ;\r
+\r
+ case 3: /* adda suba cmpa*/\r
+ allow = allowtypes[2] ;\r
+ break ;\r
+\r
+ case 4: /* sub add*/\r
+ if (dir == 0)\r
+ allow = allowtypes[0] ;\r
+ else\r
+ allow = allowtypes[1] ;\r
+ break ;\r
+ }\r
+\r
+ if ((type == 4) && (dir == 0) && (leng > 0))\r
+ {\r
+ allow = allowtypes[2] ; /* word and long ok*/\r
+ }\r
+\r
+ Opcode = start | (reg << 9 ) | (dir<<8) | (leng<<6) | (mode<<3) | sreg;\r
+\r
+ BaseCode = Opcode & 0xf1f8;\r
+\r
+ if (mode == 7) BaseCode |= sreg ;\r
+\r
+#ifdef A7ROUTINE\r
+ if ((mode == 3 || mode == 4) && ( leng == 0 ) && (sreg == 7 ))\r
+ BaseCode |= sreg ;\r
+#endif\r
+\r
+\r
+\r
+ /* If Source = Data or Address register - combine into same routine */\r
+\r
+ if (((Opcode & 0x38) == 0x08) && (allow[1] != '-'))\r
+ {\r
+ BaseCode &= 0xfff7;\r
+ }\r
+\r
+ Dest = EAtoAMN(Opcode, FALSE);\r
+ SaveEDX = (Dest == 1) || (type == 3);\r
+\r
+ if (allow[Dest&0xf] != '-')\r
+ {\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ switch (leng)\r
+ {\r
+ case 0:\r
+ Size = 'B';\r
+ Regname = regnamesshort[0];\r
+ RegnameECX = regnamesshort[ECX];\r
+ break;\r
+ case 1:\r
+ Size = 'W';\r
+ Regname = regnamesword[0];\r
+ RegnameECX = regnamesword[ECX];\r
+ break;\r
+ case 2:\r
+ Size = 'L';\r
+ Regname = regnameslong[0];\r
+ RegnameECX = regnameslong[ECX];\r
+ break;\r
+\r
+ case 3: /* cmpa adda suba */\r
+ if (dir == 0)\r
+ {\r
+ Size = 'W';\r
+ Regname = regnamesword[0];\r
+ RegnameECX = regnamesword[ECX];\r
+ }\r
+ else\r
+ {\r
+ Size = 'L';\r
+ Regname = regnameslong[0];\r
+ RegnameECX = regnameslong[ECX];\r
+ }\r
+ dir = 0 ;\r
+ break ;\r
+ }\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ if (dir==0)\r
+ {\r
+ if (Size != 'L')\r
+ TimingCycles += 4;\r
+ else\r
+ TimingCycles += 6;\r
+ }\r
+ else\r
+ {\r
+ if (Size != 'L')\r
+ TimingCycles += 8;\r
+ else\r
+ TimingCycles += 12;\r
+ }\r
+\r
+ if ((mode == 0) && (dir==0) && (Size == 'L'))\r
+ TimingCycles += 2 ;\r
+\r
+ if ((mode == 1) && (dir==0) && (Size != 'L'))\r
+ TimingCycles += 4 ;\r
+\r
+ if (Dest < 7) /* Others do not need reg.no. */\r
+ {\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+\r
+ if ((Dest == 0) & (allow[1] != '-'))\r
+ fprintf(fp, "\t\t and ebx,byte 15\n");\r
+ else\r
+ fprintf(fp, "\t\t and ebx,byte 7\n");\r
+ }\r
+\r
+ fprintf(fp, "\t\t shr ecx,byte 9\n");\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+\r
+ EffectiveAddressRead(Dest,Size,EBX,EAX,"-BCDSDB",SaveEDX);\r
+\r
+ if (dir == 0)\r
+ {\r
+ if (type != 3)\r
+ {\r
+ fprintf(fp, "\t\t %s [%s+ECX*4],%s\n",Op ,REG_DAT ,Regname ) ;\r
+\r
+ if (type == 4)\r
+ SetFlags(Size,EAX,FALSE,TRUE,FALSE);\r
+ else\r
+ SetFlags(Size,EAX,FALSE,FALSE,FALSE);\r
+ }\r
+ else\r
+ {\r
+ if (Size == 'W')\r
+ fprintf(fp, "\t\t cwde\n");\r
+\r
+ fprintf(fp, "\t\t %s [%s+ECX*4],EAX\n",Op ,REG_ADD);\r
+\r
+ if (Op[0] == 'c')\r
+ {\r
+ SetFlags('L',EAX,FALSE,FALSE,FALSE);\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t %s %s,[%s+ECX*4]\n", Op, Regname ,REG_DAT ) ;\r
+\r
+ if (type == 4)\r
+ SetFlags(Size,EAX,FALSE,TRUE,TRUE);\r
+ else\r
+ SetFlags(Size,EAX,FALSE,FALSE,TRUE);\r
+\r
+ EffectiveAddressWrite(Dest,Size,EBX,FALSE,"---DS-B",FALSE);\r
+ }\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode;\r
+ }\r
+\r
+ dir = SaveDir;\r
+}\r
+\r
+void typelogicalmath(void)\r
+{\r
+ int dir, leng, mode, sreg ,reg ;\r
+\r
+ for (reg = 0 ; reg < 8 ; reg++)\r
+ {\r
+ /* or */\r
+ for (dir = 0 ; dir < 2 ; dir++)\r
+ for (leng = 0 ; leng < 3; leng++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ dumpx( 0x8000, reg, 0, "or ", dir, leng, mode, sreg ) ;\r
+\r
+ /* sub */\r
+ for (dir = 0 ; dir < 2 ; dir++)\r
+ for (leng = 0 ; leng < 3; leng++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ dumpx( 0x9000, reg, 4, "sub", dir, leng, mode, sreg ) ;\r
+\r
+ /* suba */\r
+\r
+ for (dir = 0 ; dir < 2 ; dir++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ dumpx( 0x9000, reg, 3, "sub", dir, 3, mode, sreg ) ;\r
+\r
+\r
+ /* cmp */\r
+ for (leng = 0 ; leng < 3; leng++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ dumpx( 0xb000, reg, 1, "cmp", 0, leng, mode, sreg ) ;\r
+\r
+ /* cmpa */\r
+\r
+ for (dir = 0 ; dir < 2 ; dir++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ dumpx( 0xb000, reg, 3, "cmp", dir, 3, mode, sreg ) ;\r
+\r
+ /* adda */\r
+\r
+ for (dir = 0 ; dir < 2 ; dir++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ dumpx( 0xd000, reg, 3, "add", dir, 3, mode, sreg ) ;\r
+\r
+\r
+ /* eor */\r
+ for (leng = 0 ; leng < 3; leng++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ dumpx( 0xb100, reg, 2, "xor", 1, leng, mode, sreg ) ;\r
+\r
+ /* and */\r
+ for (dir = 0 ; dir < 2 ; dir++)\r
+ for (leng = 0 ; leng < 3; leng++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ dumpx( 0xc000, reg, 0, "and", dir, leng, mode, sreg ) ;\r
+\r
+ /* add */\r
+ for (dir = 0 ; dir < 2 ; dir++)\r
+ for (leng = 0 ; leng < 3; leng++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ dumpx( 0xd000, reg, 4, "add", dir, leng, mode, sreg ) ;\r
+ }\r
+}\r
+\r
+/*\r
+ * Single commands missed out by routines above\r
+ *\r
+ */\r
+\r
+void mul(void)\r
+{\r
+ int dreg, type, mode, sreg ;\r
+ int Opcode, BaseCode ;\r
+ int Dest ;\r
+ char allow[] = "0-23456789ab-----" ;\r
+\r
+ for (dreg = 0 ; dreg < 8 ; dreg++)\r
+ for (type = 0 ; type < 2 ; type++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0xc0c0 | (dreg<<9) | (type<<8) | (mode<<3) | sreg ;\r
+ BaseCode = Opcode & 0xc1f8 ;\r
+ if (mode == 7)\r
+ {\r
+ BaseCode |= sreg ;\r
+ }\r
+\r
+ Dest = EAtoAMN(Opcode, FALSE);\r
+ if (allow[Dest&0x0f] != '-')\r
+ {\r
+ if (OpcodeArray[ BaseCode ] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 70 ;\r
+\r
+ if (mode < 7)\r
+ {\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+ fprintf(fp, "\t\t and ebx,byte 7\n");\r
+ }\r
+\r
+ fprintf(fp, "\t\t shr ecx, byte 9\n");\r
+ fprintf(fp, "\t\t and ecx, byte 7\n");\r
+\r
+ EffectiveAddressRead(Dest,'W',EBX,EAX,"ABCDSDB",FALSE);\r
+\r
+ if (type == 0)\r
+ fprintf(fp, "\t\t mul word [%s+ECX*4]\n",REG_DAT);\r
+ else\r
+ fprintf(fp, "\t\t imul word [%s+ECX*4]\n",REG_DAT);\r
+\r
+ fprintf(fp, "\t\t shl edx, byte 16\n");\r
+ fprintf(fp, "\t\t mov dx,ax\n");\r
+ fprintf(fp, "\t\t mov [%s+ECX*4],edx\n",REG_DAT);\r
+ SetFlags('L',EDX,TRUE,FALSE,FALSE);\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+void mull(void)\r
+{\r
+ int mode, sreg ;\r
+ int Opcode, BaseCode ;\r
+ int Dest ;\r
+ char allow[] = "0-23456789ab-----" ;\r
+ char *Label = NULL ;\r
+\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0x4c00 | (mode<<3) | sreg ;\r
+ BaseCode = Opcode & 0x4c38 ;\r
+ if (mode == 7)\r
+ {\r
+ BaseCode |= sreg ;\r
+ }\r
+\r
+ Dest = EAtoAMN(Opcode, FALSE);\r
+ if (allow[Dest&0x0f] != '-')\r
+ {\r
+ if (OpcodeArray[ BaseCode ] == -2)\r
+ {\r
+ TimingCycles += 70 ;\r
+ Align();\r
+ Label = GenerateLabel(BaseCode,0);\r
+ fprintf(fp, "%s:\n",Label);\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ if (mode < 7)\r
+ {\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ }\r
+\r
+ Memory_Fetch('W', EBX, FALSE ); // fetch the next word\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ EffectiveAddressRead(Dest,'L',ECX,EAX,"ABCDSDB",FALSE); // read from the EA\r
+\r
+ fprintf(fp, "\t\t mov ecx,ebx\n"); // save 2nd word in ecx\r
+ fprintf(fp, "\t\t shr ebx,12\n"); // ebx = Dl register\r
+ fprintf(fp, "\t\t and ebx,7\n"); // 0-7\r
+\r
+ Label = GenerateLabel(BaseCode,1);\r
+\r
+ fprintf(fp, "\t\t test ecx,0x0800\n"); // signed/unsigned?\r
+ fprintf(fp, "\t\t jz short %s\n",Label); // skip if unsigned\r
+\r
+ fprintf(fp, "\t\t imul dword [%s+EBX*4]\n",REG_DAT); // signed 32x32->64\r
+ fprintf(fp, "\t\t jmp short %s_1\n",Label); // skip\r
+\r
+ fprintf(fp, "%s:\n",Label);\r
+ fprintf(fp, "\t\t mul dword [%s+EBX*4]\n",REG_DAT); // unsigned 32x32->64\r
+\r
+ fprintf(fp, "%s_1:\n",Label);\r
+ fprintf(fp, "\t\t mov [%s+EBX*4],eax\n",REG_DAT); // store Dl back\r
+\r
+ fprintf(fp, "\t\t test ecx,0x0400\n"); // do we care?\r
+ fprintf(fp, "\t\t jz short %s_2\n",Label); // if not, skip\r
+ fprintf(fp, "\t\t and ecx,7\n"); // get Dh register\r
+ fprintf(fp, "\t\t mov [%s+ECX*4],edx\n",REG_DAT); // store upper 32 bits\r
+ SetFlags('L',EDX,TRUE,FALSE,FALSE); // set the flags\r
+ fprintf(fp, "\t\t and edx,~0x0800\n"); // clear the overflow\r
+ fprintf(fp, "\t\t jmp short %s_3\n",Label); // skip\r
+\r
+ fprintf(fp, "%s_2:\n",Label);\r
+ fprintf(fp, "\t\t mov ebx,edx\n"); // save upper 32 in ebx\r
+ SetFlags('L',EAX,TRUE,FALSE,FALSE); // set the flags\r
+ fprintf(fp, "\t\t sar eax,31\n"); // eax = sign-extended\r
+ fprintf(fp, "\t\t test ecx,0x0800\n"); // signed/unsigned?\r
+ fprintf(fp, "\t\t jnz short %s_4\n",Label); // skip if signed\r
+ fprintf(fp, "\t\t xor eax,eax\n"); // always use 0 for unsigned\r
+ fprintf(fp, "%s_4:\n",Label);\r
+ fprintf(fp, "\t\t cmp eax,ebx\n"); // compare upper 32 against eax\r
+ fprintf(fp, "\t\t je short %s_3\n",Label); // if equal to sign extension, skip\r
+ fprintf(fp, "\t\t or edx,0x0800\n"); // set the overflow\r
+\r
+ fprintf(fp, "%s_3:\n",Label);\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+void divl(void)\r
+{\r
+ int mode, sreg ;\r
+ int Opcode, BaseCode ;\r
+ int Dest ;\r
+ char allow[] = "0-23456789ab-----" ;\r
+ char *Label = NULL ;\r
+\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0x4c40 | (mode<<3) | sreg ;\r
+ BaseCode = Opcode & 0x4c78 ;\r
+ if (mode == 7)\r
+ {\r
+ BaseCode |= sreg ;\r
+ }\r
+\r
+ Dest = EAtoAMN(Opcode, FALSE);\r
+ if (allow[Dest&0x0f] != '-')\r
+ {\r
+ if (OpcodeArray[ BaseCode ] == -2)\r
+ {\r
+ TimingCycles += 70 ;\r
+ Align();\r
+ Label = GenerateLabel(BaseCode,0);\r
+ fprintf(fp, "%s:\n",Label);\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t push edx\n"); // save edx\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+ fprintf(fp, "\t\t and ecx,byte 7\n"); // read from ea\r
+\r
+ Memory_Fetch('W', EDX, FALSE ); // fetch 2nd word in ecx\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ EffectiveAddressRead(Dest,'L',ECX,EBX,"---DSDB",FALSE);\r
+\r
+ fprintf(fp, "\t\t push esi\n"); // save and 0 esi\r
+ ClearRegister(ESI);\r
+\r
+ Label = GenerateLabel(BaseCode,1);\r
+\r
+ fprintf(fp, "\t\t test ebx,ebx\n"); // check divisor against 0\r
+ fprintf(fp, "\t\t jz near %s_ZERO\n",Label); // handle divide-by-zero\r
+// low part always used\r
+ fprintf(fp, "\t\t mov ecx,edx\n"); // ecx = extension word\r
+ fprintf(fp, "\t\t shr edx,12\n"); // edx = Dq register\r
+ fprintf(fp, "\t\t and edx,7\n"); // 0-7\r
+ fprintf(fp, "\t\t mov eax,[%s+edx*4]\n",REG_DAT); // eax = Dq register value\r
+\r
+ ClearRegister(EDX); // edx = 0\r
+ fprintf(fp, "\t\t test ecx,0x0400\n"); // check size\r
+ fprintf(fp, "\t\t jz short %s_1\n",Label); // skip if 32-bit dividend\r
+// high longword (64bit)\r
+ fprintf(fp, "\t\t mov edx,ecx\n"); // edx = extension word\r
+ fprintf(fp, "\t\t and edx,7\n"); // 0-7\r
+ fprintf(fp, "\t\t mov edx,[%s+edx*4]\n",REG_DAT); // fetch upper 32-bits\r
+\r
+ fprintf(fp, "\t\t test ecx,0x0800\n"); // signed?\r
+ fprintf(fp, "\t\t jz near %s_3\n",Label); // if not, skip to unsigned 64-bit\r
+ fprintf(fp, "\t\t jmp near %s_2\n",Label); // skip to signed 64-bit case\r
+\r
+ fprintf(fp, "%s_1:\n",Label); // short case\r
+ ClearRegister(EDX); // clear edx\r
+ fprintf(fp, "\t\t test ecx,0x0800\n"); // signed?\r
+ fprintf(fp, "\t\t jz short %s_3\n",Label); // if not, don't convert\r
+ fprintf(fp, "\t\t cdq\n"); // sign extend into edx\r
+// signed\r
+ fprintf(fp, "%s_2:\n",Label); // signed 32/64-bit case\r
+ fprintf(fp, "\t\t or esi,1\n"); // esi |= 1 to indicate signed\r
+ fprintf(fp, "\t\t test ebx,ebx\n"); // check divisor sign\r
+ fprintf(fp, "\t\t jge short %s_2b\n",Label); // if >= 0, don't set\r
+ fprintf(fp, "\t\t or esi,2\n"); // esi |= 2 to indicate negative divisor\r
+ fprintf(fp, "\t\t neg ebx\n"); // make positive\r
+ fprintf(fp, "%s_2b:\n",Label);\r
+ fprintf(fp, "\t\t test edx,edx\n"); // check dividend sign\r
+ fprintf(fp, "\t\t jge short %s_3\n",Label); // if >= 0, don't set\r
+ fprintf(fp, "\t\t push ebx\n"); // save ebx\r
+ fprintf(fp, "\t\t push ecx\n"); // save ecx\r
+ ClearRegister(EBX); // clear ebx\r
+ ClearRegister(ECX); // clear ecx\r
+ fprintf(fp, "\t\t sub ebx,eax\n"); // ebx = 0 - eax\r
+ fprintf(fp, "\t\t sbb ecx,edx\n"); // ecx = 0 - edx\r
+ fprintf(fp, "\t\t mov eax,ebx\n"); // eax = ebx\r
+ fprintf(fp, "\t\t mov edx,ecx\n"); // edx = ecx\r
+ fprintf(fp, "\t\t pop ecx\n"); // restore ecx\r
+ fprintf(fp, "\t\t pop ebx\n"); // restore ebx\r
+ fprintf(fp, "\t\t or esi,4\n"); // esi |= 4 to indicate negative dividend\r
+// unsigned\r
+ fprintf(fp, "%s_3:\n",Label); // unsigned 32/64-bit case\r
+ fprintf(fp, "\t\t cmp ebx,edx\n"); // check ebx against upper 32 bits\r
+ fprintf(fp, "\t\t jbe near %s_OVERFLOW\n",Label); // generate overflow\r
+ fprintf(fp, "\t\t div ebx\n"); // do the divide\r
+ fprintf(fp, "\t\t test esi,esi\n"); // see if we need to post process\r
+ fprintf(fp, "\t\t jz short %s_4\n",Label); // if not, skip\r
+ fprintf(fp, "\t\t jpo short %s_4\n",Label); // if PO (pos*pos or neg*neg), leave the result\r
+ fprintf(fp, "\t\t neg eax\n"); // negate the result\r
+\r
+// store results\r
+ fprintf(fp, "%s_4:\n",Label);\r
+ fprintf(fp, "\t\t mov ebx,ecx\n"); // ebx = extension word\r
+ fprintf(fp, "\t\t and ebx,7\n"); // get Dr in ebx\r
+ fprintf(fp, "\t\t shr ecx,12\n"); // ecx = Dq\r
+ fprintf(fp, "\t\t and ecx,7\n"); // 0-7\r
+ fprintf(fp, "\t\t mov [%s+ebx*4],edx\n",REG_DAT); // store remainder first\r
+ fprintf(fp, "\t\t mov [%s+ecx*4],eax\n",REG_DAT); // store quotient second\r
+ fprintf(fp, "\t\t pop esi\n"); // restore esi\r
+ fprintf(fp, "\t\t pop edx\n"); // restore edx\r
+ SetFlags('L',EAX,TRUE,FALSE,FALSE); // set the flags\r
+ fprintf(fp, "%s_5:\n",Label);\r
+ fprintf(fp, "\t\t and edx,~1\n"); // clear the carry\r
+ Completed();\r
+\r
+ fprintf(fp, "%s_ZERO:\t\t ;Do divide by zero trap\n", Label);\r
+ /* Correct cycle counter for error */\r
+ fprintf(fp, "\t\t pop esi\n"); // restore esi\r
+ fprintf(fp, "\t\t pop edx\n"); // restore edx\r
+ fprintf(fp, "\t\t add dword [%s],byte %d\n",ICOUNT,95);\r
+ fprintf(fp,"\t\t jmp short %s_5\n",Label);\r
+ Exception(5,BaseCode);\r
+\r
+ fprintf(fp, "%s_OVERFLOW:\n",Label);\r
+//set overflow\r
+ fprintf(fp, "\t\t pop esi\n"); // restore esi\r
+ fprintf(fp, "\t\t pop edx\n"); // restore edx\r
+ fprintf(fp, "\t\t or edx,0x0800\n"); // set the overflow bit\r
+ fprintf(fp, "\t\t jmp near %s_5\n",Label); // done\r
+\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+void bfext(void)\r
+{\r
+// just bfextu/bfexts for now\r
+ char allow[] = "0-2--56789a-----" ;\r
+ char *Label = NULL ;\r
+ int mode,dreg,sign,Opcode,BaseCode,Dest ;\r
+ for (mode=0; mode<8; mode++)\r
+ for (dreg=0; dreg<8; dreg++)\r
+ for (sign=0; sign<2; sign++)\r
+ {\r
+ Opcode = 0xe9c0 | (sign<<9) | (mode<<3) | dreg ;\r
+ BaseCode = Opcode & 0xebf8 ;\r
+ if (mode == 7)\r
+ BaseCode |= dreg ;\r
+ Dest = EAtoAMN(Opcode, FALSE);\r
+ if (allow[Dest&0xf] != '-')\r
+ {\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ Label = GenerateLabel(BaseCode,0);\r
+ fprintf(fp, "%s:\n",Label);\r
+ Label = GenerateLabel(BaseCode,1);\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ if (mode < 7)\r
+ {\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ }\r
+\r
+ Memory_Fetch('W', EAX, FALSE ) ;\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ EffectiveAddressRead(Dest,'L',ECX,EDX,"ABCDSDB",FALSE); // edx = dword\r
+\r
+ fprintf(fp, "\t\t mov ecx,eax\n");\r
+ fprintf(fp, "\t\t shr ecx,byte 6\n");\r
+ fprintf(fp, "\t\t test eax,0x0800\n");\r
+ fprintf(fp, "\t\t je short %s_1\n",Label);\r
+ //get offset from Dx\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ fprintf(fp, "\t\t mov ecx,[%s+ECX*4]\n",REG_DAT);\r
+ //get offset from extension\r
+ fprintf(fp, "%s_1:\n",Label);\r
+ fprintf(fp, "\t\t and ecx,31\n"); // ecx = offset\r
+ fprintf(fp, "\t\t mov ebx,eax\n");\r
+ fprintf(fp, "\t\t test eax,0x0020\n");\r
+ fprintf(fp, "\t\t je short %s_2\n",Label);\r
+ //get width from Dy\r
+ fprintf(fp, "\t\t and ebx,byte 7\n");\r
+ fprintf(fp, "\t\t mov ebx,[%s+EBX*4]\n",REG_DAT);\r
+ //get width from extension\r
+ fprintf(fp, "%s_2:\n",Label);\r
+ //fix 0=32\r
+ fprintf(fp, "\t\t sub ebx,byte 1\n");\r
+ fprintf(fp, "\t\t and ebx,byte 31\n");\r
+ fprintf(fp, "\t\t add ebx,byte 1\n"); // ebx = width\r
+ fprintf(fp, "\t\t rol edx,cl\n");\r
+ // check for N\r
+ fprintf(fp, "\t\t mov ecx,32\n");\r
+ fprintf(fp, "\t\t sub ecx,ebx\n");\r
+ fprintf(fp, "\t\t mov ebx,edx\n");\r
+ SetFlags('L',EBX,TRUE,FALSE,FALSE);\r
+ if (sign)\r
+ fprintf(fp, "\t\t sar ebx,cl\n");\r
+ else\r
+ fprintf(fp, "\t\t shr ebx,cl\n");\r
+ fprintf(fp, "\t\t shr eax,12\n");\r
+ fprintf(fp, "\t\t and eax,7\n");\r
+ fprintf(fp, "\t\t mov [%s+EAX*4],ebx\n",REG_DAT);\r
+ fprintf(fp, "\t\t test ebx,ebx\n");\r
+ fprintf(fp, "\t\t jnz short %s_3\n",Label);\r
+ //zero flag\r
+ fprintf(fp, "\t\t or edx,40h\n");\r
+ fprintf(fp, "%s_3:\n",Label);\r
+ Completed();\r
+ }\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * not\r
+ * clr\r
+ * neg\r
+ * negx\r
+ *\r
+ */\r
+\r
+void not(void)\r
+{\r
+ int type,leng, mode, sreg ;\r
+ int Opcode, BaseCode ;\r
+ int Dest ;\r
+ int SaveEDX=0;\r
+ char Size=' ' ;\r
+ char * Regname="" ;\r
+ char * RegnameECX ;\r
+ char * Label;\r
+\r
+ char allow[] = "0-2345678-------" ;\r
+\r
+ for (type = 0 ; type < 4 ; type++)\r
+ for (leng = 0 ; leng < 3 ; leng++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0x4000 | (type<<9) | (leng<<6) | (mode<<3) | sreg ;\r
+ BaseCode = Opcode & 0x46f8 ;\r
+ if (mode == 7)\r
+ {\r
+ BaseCode |= sreg ;\r
+ }\r
+\r
+ // A7+, A7-\r
+\r
+#ifdef A7ROUTINE\r
+ if ((leng == 0) && (sreg == 7) && (mode > 2) && (mode < 5))\r
+ {\r
+ BaseCode |= sreg ;\r
+ }\r
+#endif\r
+\r
+ Dest = EAtoAMN(Opcode, FALSE);\r
+\r
+ if (allow[Dest&0x0f] != '-')\r
+ {\r
+ switch (leng)\r
+ {\r
+ case 0:\r
+ Size = 'B';\r
+ Regname = regnamesshort[0];\r
+ RegnameECX = regnamesshort[ECX];\r
+ break;\r
+ case 1:\r
+ Size = 'W';\r
+ Regname = regnamesword[0];\r
+ RegnameECX = regnamesword[ECX];\r
+ break;\r
+ case 2:\r
+ Size = 'L';\r
+ Regname = regnameslong[0];\r
+ RegnameECX = regnameslong[ECX];\r
+ break;\r
+ }\r
+\r
+ if (OpcodeArray[ BaseCode ] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ if (Size != 'L')\r
+ TimingCycles += 4;\r
+ else\r
+ TimingCycles += 6;\r
+\r
+ if (Dest < 7)\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+\r
+ if (type == 0) SaveEDX = TRUE;\r
+ else SaveEDX = FALSE;\r
+\r
+ /* CLR does not need to read source (although it does on a real 68000) */\r
+\r
+ if (type != 1)\r
+ {\r
+ EffectiveAddressRead(Dest,Size,ECX,EAX,"A-CDS-B",SaveEDX);\r
+ }\r
+\r
+ switch (type)\r
+ {\r
+ case 0: /* negx */\r
+\r
+ /* Preserve old Z flag */\r
+\r
+ fprintf(fp, "\t\t mov ebx,edx\n");\r
+\r
+ CopyX();\r
+ fprintf(fp, "\t\t adc %s,byte 0\n", Regname ) ;\r
+ fprintf(fp, "\t\t neg %s\n", Regname ) ;\r
+\r
+ /* Set the Flags */\r
+\r
+ SetFlags(Size,EAX,FALSE,TRUE,FALSE);\r
+\r
+ /* Handle the Z flag */\r
+\r
+ Label = GenerateLabel(0,1);\r
+\r
+ fprintf(fp, "\t\t jnz short %s\n\n",Label);\r
+\r
+ fprintf(fp, "\t\t and edx,byte -65 ; Remove Z\n");\r
+ fprintf(fp, "\t\t and ebx,byte 40h ; Mask out Old Z\n");\r
+ fprintf(fp, "\t\t or edx,ebx ; Copy across\n\n");\r
+ fprintf(fp, "%s:\n",Label);\r
+\r
+ break;\r
+\r
+ case 1: /* clr */\r
+ ClearRegister(EAX);\r
+ EffectiveAddressWrite(Dest,Size,ECX,TRUE,"----S-B",FALSE);\r
+ fprintf(fp, "\t\t mov edx,40H\n");\r
+ break;\r
+\r
+ case 2: /* neg */\r
+ fprintf(fp, "\t\t neg %s\n",Regname ) ;\r
+ SetFlags(Size,EAX,FALSE,TRUE,TRUE);\r
+ break;\r
+\r
+ case 3: /* not */\r
+ fprintf(fp, "\t\t xor %s,-1\n",Regname ) ;\r
+ SetFlags(Size,EAX,FALSE,FALSE,TRUE);\r
+ break;\r
+ }\r
+\r
+ /* Update (unless CLR command) */\r
+\r
+ if (type != 1)\r
+ EffectiveAddressWrite(Dest,Size,ECX,FALSE,"---DS-B",TRUE);\r
+\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * Move to/from USP\r
+ *\r
+ */\r
+\r
+void moveusp(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int dir, sreg ;\r
+ char * Label;\r
+\r
+ for (dir = 0 ; dir < 2 ; dir++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0x4e60 | ( dir << 3 ) | sreg ;\r
+ BaseCode = Opcode & 0x4e68 ;\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ Label = GenerateLabel(BaseCode,0);\r
+ fprintf(fp, "%s\n", Label );\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 4;\r
+\r
+ fprintf(fp, "\t\t test byte [%s],20h \t\t\t; Supervisor Mode ?\n",REG_SRH);\r
+ fprintf(fp, "\t\t jz short OP%d_%4.4x_Trap\n",CPU,BaseCode);\r
+\r
+ fprintf(fp, "\t\t and ecx,7\n");\r
+\r
+ if (dir == 0) /* reg 2 USP */\r
+ {\r
+ fprintf(fp, "\t\t mov eax,[%s+ECX*4]\n",REG_ADD);\r
+ fprintf(fp, "\t\t mov [%s],eax\n",REG_USP);\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t mov eax,[%s]\n",REG_USP);\r
+ fprintf(fp, "\t\t mov [%s+ECX*4],eax\n",REG_ADD);\r
+ }\r
+ Completed();\r
+\r
+ fprintf(fp, "OP%d_%4.4x_Trap:\n",CPU,BaseCode);\r
+ Exception(8,BaseCode);\r
+ }\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Check\r
+ *\r
+ */\r
+\r
+void chk(void)\r
+{\r
+ int dreg,mode,sreg,size ;\r
+ int Opcode, BaseCode ;\r
+ int Dest ;\r
+ char * Label ;\r
+\r
+ char *allow = "0-23456789ab----" ;\r
+\r
+ for (size = 0 ; size < (CPU==2 ? 2 : 1); size++)\r
+ for (dreg = 0 ; dreg < 8; dreg++)\r
+ for (mode = 0 ; mode < 8; mode++)\r
+ for (sreg = 0 ; sreg < 8; sreg++)\r
+ {\r
+ if (size == 0) /* word */\r
+ Opcode = 0x4180 | (dreg<<9) | (mode<<3) | sreg ;\r
+ else /* long */\r
+ Opcode = 0x4100 | (dreg<<9) | (mode<<3) | sreg ;\r
+ BaseCode = Opcode & 0x41f8 ;\r
+\r
+ if (mode == 7)\r
+ {\r
+ BaseCode |= sreg ;\r
+ }\r
+\r
+ Dest = EAtoAMN(Opcode, FALSE);\r
+\r
+ if (allow[Dest&0xf] != '-')\r
+ {\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ Label = GenerateLabel(BaseCode,0);\r
+ fprintf(fp, "%s:\n", Label );\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 10;\r
+\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+ fprintf(fp, "\t\t shr ebx,byte 9\n");\r
+ fprintf(fp, "\t\t and ebx,byte 7\n");\r
+\r
+ if (Dest < 7)\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+\r
+ EffectiveAddressRead(Dest,(size == 0) ? 'W' : 'L',ECX,EAX,"----S-B",FALSE);\r
+\r
+ if (size == 0) /* word */\r
+ {\r
+ fprintf(fp, "\t\t movsx ebx,word [%s+EBX*4]\n",REG_DAT);\r
+ fprintf(fp, "\t\t movsx eax,ax\n");\r
+ }\r
+ else /* long */\r
+ fprintf(fp, "\t\t mov ebx,[%s+EBX*4]\n",REG_DAT);\r
+\r
+ fprintf(fp, "\t\t test ebx,ebx\n"); /* is word bx < 0 */\r
+ fprintf(fp, "\t\t jl near OP%d_%4.4x_Trap_minus\n",CPU,BaseCode);\r
+\r
+ fprintf(fp, "\t\t cmp ebx,eax\n");\r
+ fprintf(fp, "\t\t jg near OP%d_%4.4x_Trap_over\n",CPU,BaseCode);\r
+ Completed();\r
+\r
+ /* N is set if data less than zero */\r
+\r
+ Align();\r
+ fprintf(fp, "OP%d_%4.4x_Trap_minus:\n",CPU,BaseCode);\r
+ fprintf(fp, "\t\t or edx,0x0080\n"); /* N flag = 80H */\r
+ fprintf(fp, "\t\t jmp short OP%d_%4.4x_Trap_Exception\n",CPU,BaseCode);\r
+\r
+ /* N is cleared if greated than compared number */\r
+\r
+ Align();\r
+ fprintf(fp, "OP%d_%4.4x_Trap_over:\n",CPU,BaseCode);\r
+ fprintf(fp, "\t\t and edx,0x007f\n"); /* N flag = 80H */\r
+\r
+ fprintf(fp, "OP%d_%4.4x_Trap_Exception:\n",CPU,BaseCode);\r
+ fprintf(fp, "\t\t mov al,6\n");\r
+ Exception(-1,0x10000+BaseCode);\r
+ Completed();\r
+\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+void chk2(void)\r
+{\r
+#if 0\r
+ int mode,sreg,size ;\r
+ int Opcode, BaseCode ;\r
+ int Dest ;\r
+ char * Label ;\r
+\r
+ char *allow = "--2--56789a-----" ;\r
+\r
+ for (size = 0 ; size < 2; size++)\r
+ for (mode = 0 ; mode < 8; mode++)\r
+ for (sreg = 0 ; sreg < 8; sreg++)\r
+ {\r
+ Opcode = 0x00c0 | (size<<9) | (mode<<3) | sreg;\r
+ BaseCode = Opcode & 0xfff8 ;\r
+\r
+ if (mode == 7)\r
+ {\r
+ BaseCode |= sreg ;\r
+ }\r
+\r
+ Dest = EAtoAMN(Opcode, FALSE);\r
+\r
+ if (allow[Dest&0xf] != '-')\r
+ {\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ Label = GenerateLabel(BaseCode,0);\r
+ fprintf(fp, "%s:\n", Label );\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 10;\r
+\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+ fprintf(fp, "\t\t shr ebx,byte 9\n");\r
+ fprintf(fp, "\t\t and ebx,byte 7\n");\r
+\r
+ if (Dest < 7)\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+\r
+ EffectiveAddressRead(Dest,'W',ECX,EAX,"----S-B",FALSE);\r
+\r
+ if (size == 0) /* word */\r
+ {\r
+ fprintf(fp, "\t\t movsx ebx,word [%s+EBX*4]\n",REG_DAT);\r
+ fprintf(fp, "\t\t movsx eax,ax\n");\r
+ }\r
+ else /* long */\r
+ fprintf(fp, "\t\t mov ebx,[%s+EBX*4]\n",REG_DAT);\r
+\r
+ fprintf(fp, "\t\t test ebx,ebx\n"); /* is word bx < 0 */\r
+ fprintf(fp, "\t\t jl near OP%d_%4.4x_Trap_minus\n",CPU,BaseCode);\r
+\r
+ fprintf(fp, "\t\t cmp ebx,eax\n");\r
+ fprintf(fp, "\t\t jg near OP%d_%4.4x_Trap_over\n",CPU,BaseCode);\r
+ Completed();\r
+\r
+ /* N is set if data less than zero */\r
+\r
+ Align();\r
+ fprintf(fp, "OP%d_%4.4x_Trap_minus:\n",CPU,BaseCode);\r
+ fprintf(fp, "\t\t or edx,0x0080\n"); /* N flag = 80H */\r
+ fprintf(fp, "\t\t jmp short OP%d_%4.4x_Trap_Exception\n",CPU,BaseCode);\r
+\r
+ /* N is cleared if greated than compared number */\r
+\r
+ Align();\r
+ fprintf(fp, "OP%d_%4.4x_Trap_over:\n",CPU,BaseCode);\r
+ fprintf(fp, "\t\t and edx,0x007f\n"); /* N flag = 80H */\r
+\r
+ fprintf(fp, "OP%d_%4.4x_Trap_Exception:\n",CPU,BaseCode);\r
+ fprintf(fp, "\t\t mov al,6\n");\r
+ Exception(-1,0x10000+BaseCode);\r
+ Completed();\r
+\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+#endif\r
+}\r
+\r
+/*\r
+ * Load Effective Address\r
+ */\r
+\r
+void LoadEffectiveAddress(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int sreg,mode,dreg ;\r
+ int Dest ;\r
+ char allow[] = "--2--56789a-----" ;\r
+\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (dreg = 0 ; dreg < 8 ; dreg++)\r
+ {\r
+ Opcode = 0x41c0 | (sreg<<9) | (mode<<3) | dreg ;\r
+\r
+ BaseCode = Opcode & 0x41f8 ;\r
+\r
+ if (mode == 7)\r
+ BaseCode = BaseCode | dreg ;\r
+\r
+ Dest = EAtoAMN(BaseCode, FALSE);\r
+\r
+ if (allow[Dest&0x0f] != '-')\r
+ {\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ switch (mode)\r
+ {\r
+ case 2:\r
+ TimingCycles += 4;\r
+ break;\r
+ case 5:\r
+ case 7:\r
+ case 9:\r
+ TimingCycles += 8;\r
+ break;\r
+ case 6:\r
+ case 8:\r
+ case 10:\r
+ TimingCycles += 12;\r
+ break;\r
+ }\r
+\r
+ if (mode < 7)\r
+ {\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+ fprintf(fp, "\t\t and ebx,byte 7\n");\r
+ }\r
+\r
+ fprintf(fp, "\t\t shr ecx,byte 9\n");\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+\r
+ EffectiveAddressCalculate(Dest,'L',EBX,TRUE);\r
+ fprintf(fp, "\t\t mov [%s+ECX*4],edi\n",REG_ADD);\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * Negate BCD\r
+ *\r
+ */\r
+\r
+void nbcd(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int sreg,mode,Dest ;\r
+ char allow[] = "0-2345678-------" ;\r
+\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0x4800 | (mode<<3) | sreg ;\r
+ BaseCode = Opcode & 0x4838 ;\r
+\r
+ if (mode == 7)\r
+ BaseCode |= sreg ;\r
+\r
+ // A7+, A7-\r
+\r
+#ifdef A7ROUTINE\r
+ if ((sreg == 7) && (mode > 2) && (mode < 5))\r
+ {\r
+ BaseCode |= sreg;\r
+ }\r
+#endif\r
+\r
+ Dest = EAtoAMN(BaseCode, FALSE);\r
+\r
+ if (allow[Dest&0xf] != '-')\r
+ {\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ if (mode < 2)\r
+ TimingCycles += 6;\r
+ else\r
+ TimingCycles += 8;\r
+\r
+ fprintf(fp, "\t\t and ecx, byte 7\n");\r
+\r
+ EffectiveAddressRead(Dest,'B',ECX,EBX,"--C-SDB",FALSE);\r
+\r
+ ClearRegister(EAX);\r
+ CopyX();\r
+\r
+ fprintf(fp, "\t\t sbb al,bl\n");\r
+ fprintf(fp, "\t\t das\n");\r
+\r
+ SetFlags('B',EAX,FALSE,TRUE,TRUE);\r
+\r
+ EffectiveAddressWrite(Dest,'B',ECX,EAX,"----S-B",FALSE);\r
+ Completed();\r
+ }\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+void tas(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int sreg,mode,Dest ;\r
+ char allow[] = "0-2345678-------" ;\r
+\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0x4ac0 | (mode<<3) | sreg ;\r
+ BaseCode = Opcode & 0x4af8 ;\r
+\r
+ if (mode == 7)\r
+ BaseCode |= sreg ;\r
+\r
+#ifdef A7ROUTINE\r
+ if ((sreg == 7) && (mode > 2) && (mode < 5))\r
+ {\r
+ BaseCode |= sreg ;\r
+ }\r
+#endif\r
+\r
+ Dest = EAtoAMN(BaseCode, FALSE);\r
+\r
+ if (allow[Dest&0xf] != '-')\r
+ {\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ if (mode < 2)\r
+ TimingCycles += 4;\r
+ else\r
+ TimingCycles += 14;\r
+\r
+ fprintf(fp, "\t\t and ecx, byte 7\n");\r
+\r
+ EffectiveAddressRead(Dest,'B',ECX,EAX,"--C-SDB",FALSE);\r
+\r
+ SetFlags('B',EAX,TRUE,FALSE,TRUE);\r
+ fprintf(fp, "\t\t or al,128\n");\r
+\r
+ EffectiveAddressWrite(Dest,'B',ECX,EAX,"----S-B",FALSE);\r
+ Completed();\r
+ }\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * push Effective Address\r
+ */\r
+\r
+void PushEffectiveAddress(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int mode,dreg ;\r
+ int Dest ;\r
+ char allow[] = "--2--56789a-----" ;\r
+\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (dreg = 0 ; dreg < 8 ; dreg++)\r
+ {\r
+ Opcode = 0x4840 | (mode<<3) | dreg ;\r
+\r
+ BaseCode = Opcode & 0x4878 ;\r
+\r
+ if (mode == 7)\r
+ BaseCode = BaseCode | dreg ;\r
+\r
+ Dest = EAtoAMN(BaseCode, FALSE);\r
+\r
+ if (allow[Dest&0x0f] != '-')\r
+ {\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ SavePreviousPC();\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ switch (mode)\r
+ {\r
+ case 2:\r
+ TimingCycles += 12;\r
+ break;\r
+ case 5:\r
+ case 7:\r
+ case 9:\r
+ TimingCycles += 16;\r
+ break;\r
+ case 6:\r
+ case 8:\r
+ case 10:\r
+ TimingCycles += 20;\r
+ break;\r
+ }\r
+\r
+ if (mode < 7)\r
+ {\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ }\r
+\r
+ EffectiveAddressCalculate(Dest,'L',ECX,TRUE);\r
+\r
+ fprintf(fp, "\t\t mov ecx,[%s]\t ; Push onto Stack\n",REG_A7);\r
+ fprintf(fp, "\t\t sub ecx,byte 4\n");\r
+ fprintf(fp, "\t\t mov [%s],ecx\n",REG_A7);\r
+ Memory_Write('L',ECX,EDI,"---DS-B",2);\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * Test\r
+ *\r
+ */\r
+\r
+void tst(void)\r
+{\r
+ int leng, mode, sreg ;\r
+ int Opcode, BaseCode ;\r
+ int Dest ;\r
+ char Size=' ' ;\r
+ char * Regname ;\r
+ char * RegnameECX ;\r
+\r
+ char allow[] = "0-2345678-------" ;\r
+ if (CPU==2)\r
+ allow[1] = '1';\r
+\r
+ for (leng = 0 ; leng < 3 ; leng++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0x4a00 | (leng<<6) | (mode<<3) | sreg ;\r
+ BaseCode = Opcode & 0x4af8 ;\r
+ if (mode == 7)\r
+ {\r
+ BaseCode |= sreg ;\r
+ }\r
+\r
+ // A7+, A7-\r
+\r
+#ifdef A7ROUTINE\r
+ if ((leng == 0) && (sreg == 7) && (mode > 2) && (mode < 5))\r
+ {\r
+ BaseCode |= sreg ;\r
+ }\r
+#endif\r
+\r
+ Dest = EAtoAMN(Opcode, FALSE);\r
+\r
+ if ((allow[Dest&0x0f] != '-') || (( mode == 1 ) && (leng != 0)))\r
+ {\r
+ switch (leng)\r
+ {\r
+ case 0:\r
+ Size = 'B';\r
+ Regname = regnamesshort[0];\r
+ RegnameECX = regnamesshort[ECX];\r
+ break;\r
+ case 1:\r
+ Size = 'W';\r
+ Regname = regnamesword[0];\r
+ RegnameECX = regnamesword[ECX];\r
+ break;\r
+ case 2:\r
+ Size = 'L';\r
+ Regname = regnameslong[0];\r
+ RegnameECX = regnameslong[ECX];\r
+ break;\r
+ }\r
+\r
+ if (OpcodeArray[ BaseCode ] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 4;\r
+\r
+ if (Dest < 7)\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+\r
+ EffectiveAddressRead(Dest,Size,ECX,EAX,"----S-B",FALSE);\r
+\r
+ SetFlags(Size,EAX,TRUE,FALSE,FALSE);\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * Move registers too / from memory\r
+ *\r
+ */\r
+\r
+void movem_reg_ea(void)\r
+{\r
+ int leng,mode,sreg ;\r
+ int Opcode, BaseCode ;\r
+ int Dest ;\r
+ char Size ;\r
+ char * Label ;\r
+\r
+ char *allow = "--2-45678-------" ;\r
+\r
+ for (leng = 0 ; leng < 2; leng++)\r
+ for (mode = 0 ; mode < 8; mode++)\r
+ for (sreg = 0 ; sreg < 8; sreg++)\r
+ {\r
+ Opcode = 0x4880 | ( leng<<6) | (mode<<3) | sreg ;\r
+ BaseCode = Opcode & 0x4cf8 ;\r
+\r
+ if (mode == 7)\r
+ {\r
+ BaseCode |= sreg ;\r
+ }\r
+\r
+ Dest = EAtoAMN(Opcode, FALSE);\r
+\r
+ Size = "WL"[leng] ;\r
+\r
+ if (allow[Dest&0xf] != '-')\r
+ {\r
+ if (OpcodeArray[BaseCode] == - 2)\r
+ {\r
+ Align();\r
+ Label = GenerateLabel(BaseCode,0);\r
+ fprintf(fp, "%s:\n",Label ) ;\r
+ SavePreviousPC();\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ switch (mode)\r
+ {\r
+ case 2:\r
+ case 4:\r
+ TimingCycles += 8 ;\r
+ break;\r
+ case 5:\r
+ case 7:\r
+ TimingCycles += 12 ;\r
+ break;\r
+ case 6:\r
+ case 8:\r
+ TimingCycles += 14 ;\r
+ break;\r
+ }\r
+\r
+ fprintf(fp, "\t\t push edx\n");\r
+\r
+ Memory_Fetch('W',EDX,FALSE);\r
+ fprintf(fp, "\t\t add esi,byte 2\n");\r
+\r
+ if (mode < 7)\r
+ {\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ }\r
+\r
+ if (mode == 4)\r
+ {\r
+ fprintf(fp, "\t\t push ecx\n");\r
+ fprintf(fp, "\t\t mov edi,[%s+ECX*4]\n",REG_ADD);\r
+ }\r
+ else\r
+ EffectiveAddressCalculate(Dest,'L',ECX,TRUE);\r
+\r
+ fprintf(fp, "\t\t mov ebx,1\n");\r
+\r
+ /* predecrement uses d0-d7..a0-a7 a7 first*/\r
+ /* other modes use a7-a0..d7-d0 d0 first*/\r
+\r
+ if (Dest != 4)\r
+ ClearRegister(ECX);\r
+ else\r
+ fprintf(fp, "\t\t mov ecx,3Ch\n");\r
+\r
+ fprintf(fp, "OP%d_%4.4x_Again:\n",CPU,BaseCode);\r
+ fprintf(fp, "\t\t test edx,ebx\n");\r
+ fprintf(fp, "\t\t je OP%d_%4.4x_Skip\n",CPU,BaseCode);\r
+\r
+ fprintf(fp, "\t\t mov eax,[%s+ecx]\n",REG_DAT); /* load eax with current reg data */\r
+\r
+ if (Dest == 4)\r
+ {\r
+ if (Size == 'W') /* adjust pointer before write */\r
+ fprintf(fp, "\t\t sub edi,byte 2\n");\r
+ else\r
+ fprintf(fp, "\t\t sub edi,byte 4\n");\r
+ }\r
+\r
+ Memory_Write(Size,EDI,EAX,"-BCDSDB",1);\r
+\r
+ if (Dest != 4)\r
+ {\r
+ if (Size == 'W') /* adjust pointer after write */\r
+ fprintf(fp, "\t\t add edi,byte 2\n");\r
+ else\r
+ fprintf(fp, "\t\t add edi,byte 4\n");\r
+ }\r
+\r
+ /* Update Cycle Count */\r
+\r
+ if (Size == 'W')\r
+ fprintf(fp, "\t\t sub dword [%s],byte 4\n",ICOUNT);\r
+ else\r
+ fprintf(fp, "\t\t sub dword [%s],byte 8\n",ICOUNT);\r
+\r
+ fprintf(fp, "OP%d_%4.4x_Skip:\n",CPU,BaseCode);\r
+\r
+ if (Dest != 4)\r
+ fprintf(fp, "\t\t add ecx,byte 4h\n");\r
+ else\r
+ fprintf(fp, "\t\t sub ecx,byte 4h\n");\r
+\r
+ fprintf(fp, "\t\t add ebx,ebx\n"); /* faster than shl ebx,1 */\r
+ fprintf(fp, "\t\t test bx,bx\n"); /* check low 16 bits */\r
+ fprintf(fp, "\t\t jnz OP%d_%4.4x_Again\n",CPU,BaseCode);\r
+\r
+ if (Dest == 4)\r
+ {\r
+ fprintf(fp, "\t\t pop ecx\n");\r
+ fprintf(fp, "\t\t mov [%s+ECX*4],edi\n",REG_ADD);\r
+ }\r
+\r
+ fprintf(fp, "\t\t pop edx\n");\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+void movem_ea_reg(void)\r
+{\r
+ int leng,mode,sreg ;\r
+ int Opcode, BaseCode ;\r
+ int Dest ;\r
+ char Size ;\r
+ char * Label ;\r
+\r
+ char *allow = "--23-56789a-----" ;\r
+\r
+ for (leng = 0 ; leng < 2; leng++)\r
+ for (mode = 0 ; mode < 8; mode++)\r
+ for (sreg = 0 ; sreg < 8; sreg++)\r
+ {\r
+ Opcode = 0x4c80 | ( leng<<6) | (mode<<3) | sreg ;\r
+ BaseCode = Opcode & 0x4cf8 ;\r
+\r
+ if (mode == 7)\r
+ {\r
+ BaseCode |= sreg ;\r
+ }\r
+\r
+ Dest = EAtoAMN(Opcode, FALSE);\r
+\r
+ Size = "WL"[leng] ;\r
+\r
+ if (allow[Dest&0xf] != '-')\r
+ {\r
+ if (OpcodeArray[BaseCode] == - 2)\r
+ {\r
+ Align();\r
+ Label = GenerateLabel(BaseCode,0);\r
+\r
+ fprintf(fp, "%s:\n",Label ) ;\r
+ SavePreviousPC();\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ switch (mode)\r
+ {\r
+ case 2:\r
+ case 4:\r
+ TimingCycles += 8 ;\r
+ break;\r
+ case 5:\r
+ case 7:\r
+ TimingCycles += 12 ;\r
+ break;\r
+ case 6:\r
+ case 8:\r
+ TimingCycles += 14 ;\r
+ break;\r
+ }\r
+\r
+ fprintf(fp, "\t\t push edx\n"); /* save edx because sr is unaffected */\r
+\r
+ Memory_Fetch('W',EDX,FALSE);\r
+ fprintf(fp, "\t\t add esi,byte 2\n");\r
+\r
+ if (mode < 7)\r
+ {\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ }\r
+\r
+ if (mode == 3)\r
+ fprintf(fp, "\t\t push ecx\n"); /* if (An)+ then it needed later */\r
+\r
+ EffectiveAddressCalculate(Dest,'L',ECX,TRUE);\r
+\r
+ fprintf(fp, "\t\t mov ebx,1\n"); /* setup register list mask */\r
+\r
+ /* predecrement uses d0-d7..a0-a7 a7 first*/\r
+ /* other modes use a7-a0..d7-d0 d0 first*/\r
+\r
+ ClearRegister(ECX); /* always start with D0 */\r
+\r
+ fprintf(fp, "OP%d_%4.4x_Again:\n",CPU,BaseCode);\r
+ fprintf(fp, "\t\t test edx,ebx\n"); /* is bit set for this register? */\r
+ fprintf(fp, "\t\t je OP%d_%4.4x_Skip\n",CPU,BaseCode);\r
+\r
+ Memory_Read(Size,EDI,"-BCDSDB",1);\r
+\r
+ if (Size == 'W')\r
+ fprintf(fp, "\t\t cwde\n"); /* word size must be sign extended */\r
+\r
+ fprintf(fp, "\t\t mov [%s+ecx],eax\n",REG_DAT); /* load current reg with eax */\r
+\r
+ if (Size == 'W') /* adjust pointer after write */\r
+ fprintf(fp, "\t\t add edi,byte 2\n");\r
+ else\r
+ fprintf(fp, "\t\t add edi,byte 4\n");\r
+\r
+ /* Update Cycle Count */\r
+\r
+ if (Size == 'W')\r
+ fprintf(fp, "\t\t sub dword [%s],byte 4\n",ICOUNT);\r
+ else\r
+ fprintf(fp, "\t\t sub dword [%s],byte 8\n",ICOUNT);\r
+\r
+ fprintf(fp, "OP%d_%4.4x_Skip:\n",CPU,BaseCode);\r
+ fprintf(fp, "\t\t add ecx,byte 4\n"); /* adjust pointer to next reg */\r
+ fprintf(fp, "\t\t add ebx,ebx\n"); /* Faster than shl ebx,1 */\r
+ fprintf(fp, "\t\t test bx,bx\n"); /* check low 16 bits */\r
+ fprintf(fp, "\t\t jnz OP%d_%4.4x_Again\n",CPU,BaseCode);\r
+\r
+ if (mode == 3)\r
+ {\r
+ fprintf(fp, "\t\t pop ecx\n");\r
+ fprintf(fp, "\t\t mov [%s+ECX*4],edi\n",REG_ADD); /* reset Ax if mode = (Ax)+ */\r
+ }\r
+\r
+ fprintf(fp, "\t\t pop edx\n"); /* restore flags */\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * Link / Unlink\r
+ *\r
+ * Local stack space\r
+ *\r
+ */\r
+\r
+void link(void)\r
+{\r
+ int sreg ;\r
+ int Opcode, BaseCode ;\r
+\r
+ for (sreg = 0 ; sreg < 8; sreg++)\r
+ {\r
+ Opcode = 0x4e50 | sreg ;\r
+ BaseCode = 0x4e50 ;\r
+\r
+ if (OpcodeArray[BaseCode] == - 2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ SavePreviousPC();\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 16;\r
+\r
+ fprintf(fp, "\t\t sub dword [%s],byte 4\n",REG_A7);\r
+\r
+ fprintf(fp, "\t\t and ecx, byte 7\n");\r
+ fprintf(fp, "\t\t mov eax,[%s+ECX*4]\n",REG_ADD);\r
+ fprintf(fp, "\t\t mov edi,[%s]\n",REG_A7);\r
+ fprintf(fp, "\t\t mov [%s+ECX*4],edi\n",REG_ADD);\r
+\r
+ Memory_Write('L',EDI,EAX,"---DS-B",1);\r
+\r
+ Memory_Fetch('W',EAX,TRUE);\r
+ fprintf(fp, "\t\t add esi,byte 2\n");\r
+ fprintf(fp, "\t\t add [%s],eax\n",REG_A7);\r
+\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+}\r
+\r
+void unlinkasm(void)\r
+{\r
+ int sreg ;\r
+ int Opcode, BaseCode ;\r
+\r
+ for (sreg = 0 ; sreg < 8; sreg++)\r
+ {\r
+ Opcode = 0x4e58 | sreg ;\r
+ BaseCode = 0x4e58 ;\r
+\r
+ if (OpcodeArray[BaseCode] == - 2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ SavePreviousPC();\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 12;\r
+\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+ fprintf(fp, "\t\t and ebx, byte 7\n");\r
+ fprintf(fp, "\t\t mov edi,[%s+EBX*4]\n",REG_ADD);\r
+\r
+ Memory_Read('L',EDI,"-B-DSDB",1);\r
+\r
+ fprintf(fp, "\t\t mov [%s+EBX*4],eax\n",REG_ADD);\r
+ fprintf(fp, "\t\t add edi,byte 4\n");\r
+ fprintf(fp, "\t\t mov dword [%s],EDI\n",REG_A7);\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+}\r
+\r
+void trap(void)\r
+{\r
+ int Count;\r
+ int BaseCode = 0x4E40;\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ fprintf(fp, "\t\t mov eax,ecx\n");\r
+ fprintf(fp, "\t\t and eax,byte 15\n");\r
+ fprintf(fp, "\t\t or eax,byte 32\n");\r
+ Exception(-1,BaseCode);\r
+ Completed();\r
+ }\r
+\r
+ for (Count=0;Count<=15;Count++)\r
+ OpcodeArray[BaseCode+Count] = BaseCode;\r
+}\r
+\r
+void reset(void)\r
+{\r
+ int BaseCode = 0x4E70;\r
+ char * Label;\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ Label = GenerateLabel(BaseCode,0);\r
+\r
+ TimingCycles += 132;\r
+\r
+ fprintf(fp, "%s:\n", Label );\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+ fprintf(fp, "\t\t test byte [%s],20h \t\t\t; Supervisor Mode ?\n",REG_SRH);\r
+ fprintf(fp, "\t\t jnz near OP%d_%4.4x_RESET\n",CPU,BaseCode);\r
+ Exception(8,BaseCode);\r
+\r
+ fprintf(fp, "\nOP%d_%4.4x_RESET:\n",CPU,BaseCode);\r
+\r
+ /* Prefetch next instruction */\r
+\r
+ if(CPU==2)\r
+ {\r
+ /* 32 bit memory version */\r
+\r
+ fprintf(fp, "\t\t xor esi,2\n"); /* ASG */\r
+#ifdef STALLCHECK\r
+ ClearRegister(ECX);\r
+ fprintf(fp, "\t\t mov cx,[esi+ebp]\n");\r
+#else\r
+ fprintf(fp, "\t\t movzx ecx,word [esi+ebp]\n");\r
+#endif\r
+ fprintf(fp, "\t\t xor esi,2\n"); /* ASG */\r
+ }\r
+ else\r
+ {\r
+ /* 16 bit memory */\r
+#ifdef STALLCHECK\r
+ ClearRegister(ECX);\r
+ fprintf(fp, "\t\t mov cx,[esi+ebp]\n");\r
+#else\r
+ fprintf(fp, "\t\t movzx ecx,word [esi+ebp]\n");\r
+#endif\r
+ }\r
+\r
+ fprintf(fp, "\t\t mov eax,dword [%s]\n", REG_RESET_CALLBACK);\r
+ fprintf(fp, "\t\t test eax,eax\n");\r
+ fprintf(fp, "\t\t jz near OP%d_%4.4x_END\n",CPU,BaseCode);\r
+\r
+ /* Callback for Reset */\r
+\r
+ fprintf(fp, "\t\t mov [%s],ESI,\n",REG_PC);\r
+ fprintf(fp, "\t\t mov [%s],edx\n",REG_CCR);\r
+ fprintf(fp, "\t\t push ECX\n");\r
+\r
+ fprintf(fp, "\t\t call [eax]\n");\r
+\r
+ fprintf(fp, "\t\t mov ESI,[%s]\n",REG_PC);\r
+ fprintf(fp, "\t\t mov edx,[%s]\n",REG_CCR);\r
+ fprintf(fp, "\t\t pop ECX\n");\r
+ fprintf(fp, "\t\t mov ebp,dword [_OP_ROM]\n");\r
+\r
+ fprintf(fp, "OP%d_%4.4x_END:\n",CPU,BaseCode);\r
+ fprintf(fp, "\t\t sub dword [%s],%d\n",ICOUNT,TimingCycles);\r
+ fprintf(fp, "\t\t jmp [%s_OPCODETABLE+ecx*4]\n\n", CPUtype);\r
+ }\r
+ OpcodeArray[BaseCode] = BaseCode ;\r
+}\r
+\r
+void nop(void)\r
+{\r
+ int BaseCode = 0x4e71 ;\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 4;\r
+\r
+ Completed();\r
+ OpcodeArray[BaseCode] = BaseCode ;\r
+ }\r
+}\r
+\r
+void stop(void)\r
+{\r
+ char TrueLabel[16];\r
+ int BaseCode = 0x4e72 ;\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 4;\r
+\r
+ /* Must be in Supervisor Mode */\r
+\r
+ sprintf(TrueLabel,GenerateLabel(0,1));\r
+\r
+ fprintf(fp, "\t\t test byte [%s],20h \t\t\t; Supervisor Mode ?\n",REG_SRH);\r
+ fprintf(fp, "\t\t je near %s\n\n",TrueLabel);\r
+\r
+ /* Next WORD is new SR */\r
+\r
+ Memory_Fetch('W',EAX,FALSE);\r
+ fprintf(fp, "\t\t add esi,byte 2\n");\r
+\r
+ WriteCCR('W');\r
+\r
+ /* See if Valid interrupt waiting */\r
+\r
+ CheckInterrupt = 0;\r
+\r
+ fprintf(fp, "\t\t mov eax,[%s]\n",REG_IRQ);\r
+ fprintf(fp, "\t\t and eax,byte 07H\n");\r
+\r
+ fprintf(fp, "\t\t cmp al,7\t\t ; Always take 7\n");\r
+ fprintf(fp, "\t\t je near procint\n\n");\r
+\r
+ fprintf(fp, "\t\t mov ebx,[%s]\t\t; int mask\n",REG_SRH);\r
+ fprintf(fp, "\t\t and ebx,byte 07H\n");\r
+ fprintf(fp, "\t\t cmp eax,ebx\n");\r
+ fprintf(fp, "\t\t jg near procint\n\n");\r
+\r
+ /* No int waiting - clear count, set stop */\r
+\r
+ ClearRegister(ECX);\r
+ fprintf(fp, "\t\t mov [%s],ecx\n",ICOUNT);\r
+ fprintf(fp, "\t\t or byte [%s],80h\n",REG_IRQ);\r
+ Completed();\r
+\r
+ /* User Mode - Exception */\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",TrueLabel);\r
+ Exception(8,BaseCode);\r
+\r
+ OpcodeArray[BaseCode] = BaseCode ;\r
+ }\r
+}\r
+\r
+void ReturnFromException(void)\r
+{\r
+ char TrueLabel[16];\r
+\r
+ int BaseCode = 0x4e73;\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ SavePreviousPC();\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 20;\r
+\r
+ /* Check in Supervisor Mode */\r
+\r
+ sprintf(TrueLabel,GenerateLabel(0,1));\r
+ fprintf(fp, "\t\t test byte [%s],20h \t\t\t; Supervisor Mode ?\n",REG_SRH);\r
+ fprintf(fp, "\t\t je near %s\n\n",TrueLabel);\r
+\r
+ /* Get SR - Save in EBX */\r
+\r
+ fprintf(fp, "\t\t mov edi,[%s]\n",REG_A7);\r
+ fprintf(fp, "\t\t add dword [%s],byte 6\n",REG_A7);\r
+ Memory_Read('W',EDI,"-----DB",2);\r
+ fprintf(fp, "\t\t add edi,byte 2\n");\r
+ fprintf(fp, "\t\t mov esi,eax\n");\r
+\r
+ /* Get PC */\r
+\r
+ Memory_Read('L',EDI,"----S-B",0);\r
+ fprintf(fp, "\t\t xchg esi,eax\n");\r
+\r
+ /* Update CCR (and A7) */\r
+\r
+ WriteCCR('W');\r
+\r
+ MemoryBanking(BaseCode);\r
+ Completed();\r
+\r
+ fprintf(fp, "%s:\n",TrueLabel);\r
+ Exception(8,0x10000+BaseCode);\r
+\r
+ OpcodeArray[BaseCode] = BaseCode;\r
+}\r
+\r
+void trapv(void)\r
+{\r
+ int BaseCode = 0x4E76;\r
+ char * Label;\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ Label = GenerateLabel(BaseCode,0);\r
+ fprintf(fp, "%s\n", Label );\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 4;\r
+\r
+ fprintf(fp, "\t\t test dh,08h\n");\r
+ fprintf(fp, "\t\t jz near OP%d_%4.4x_Clear\n",CPU,BaseCode);\r
+ Exception(7,BaseCode);\r
+\r
+ fprintf(fp, "OP%d_%4.4x_Clear:\n",CPU,BaseCode);\r
+ Completed();\r
+ }\r
+ OpcodeArray[BaseCode] = BaseCode ;\r
+}\r
+\r
+void illegal_opcode(void)\r
+{\r
+ Align();\r
+ fprintf(fp, "ILLEGAL:\n");\r
+ fprintf(fp, "\t\t mov [_illegal_op],ecx\n");\r
+ fprintf(fp, "\t\t mov [_illegal_pc],esi\n");\r
+\r
+#ifdef MAME_DEBUG\r
+ fprintf(fp, "\t\t jmp ecx\n");\r
+ fprintf(fp, "\t\t pushad\n");\r
+ fprintf(fp, "\t\t call _m68k_illegal_opcode\n");\r
+ fprintf(fp, "\t\t popad\n");\r
+#endif\r
+\r
+ Exception(4,0xFFFE);\r
+}\r
+\r
+/*\r
+ * Return from subroutine\r
+ * restoring flags as well\r
+ *\r
+ */\r
+\r
+void ReturnandRestore(void)\r
+{\r
+ int BaseCode = 0x4e77;\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ SavePreviousPC();\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 20;\r
+\r
+ /* Get SR into ESI */\r
+\r
+ fprintf(fp, "\t\t mov edi,[%s]\n",REG_A7);\r
+ fprintf(fp, "\t\t add dword [%s],byte 6\n",REG_A7);\r
+\r
+ Memory_Read('W',EDI,"-----DB",2);\r
+ fprintf(fp, "\t\t add edi,byte 2\n");\r
+ fprintf(fp, "\t\t mov esi,eax\n");\r
+\r
+ /* Get PC */\r
+\r
+ Memory_Read('L',EDI,"----SDB",0);\r
+ fprintf(fp, "\t\t xchg esi,eax\n");\r
+\r
+ /* Update flags */\r
+\r
+ WriteCCR('B');\r
+\r
+ MemoryBanking(BaseCode);\r
+ Completed();\r
+\r
+ OpcodeArray[BaseCode] = BaseCode;\r
+}\r
+\r
+/*\r
+ * Return from Subroutine\r
+ *\r
+ */\r
+\r
+void rts(void)\r
+{\r
+ int BaseCode = 0x4e75 ;\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ SavePreviousPC();\r
+\r
+ TimingCycles += 16;\r
+\r
+ OpcodeArray[BaseCode] = BaseCode ;\r
+\r
+ fprintf(fp, "\t\t mov eax,[%s]\n",REG_A7);\r
+ fprintf(fp, "\t\t add dword [%s],byte 4\n",REG_A7);\r
+ Memory_Read('L',EAX,"---D--B",1);\r
+ fprintf(fp, "\t\t mov esi,eax\n");\r
+ MemoryBanking(BaseCode);\r
+ Completed();\r
+ }\r
+}\r
+\r
+void jmp_jsr(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int dreg,mode,type ;\r
+ int Dest ;\r
+ char allow[] = "--2--56789a-----" ;\r
+\r
+ for (type = 0 ; type < 2 ; type++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (dreg = 0 ; dreg < 8 ; dreg++)\r
+ {\r
+ Opcode = 0x4e80 | (type<<6) | (mode<<3) | dreg ;\r
+ BaseCode = Opcode & 0x4ef8 ;\r
+ if (mode == 7)\r
+ BaseCode = BaseCode | dreg ;\r
+\r
+ Dest = EAtoAMN(BaseCode, FALSE);\r
+ if (allow[Dest&0x0f] != '-')\r
+ {\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ SavePreviousPC();\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ switch (mode)\r
+ {\r
+ case 2:\r
+ TimingCycles += 8;\r
+ break;\r
+ case 5:\r
+ case 7:\r
+ case 9:\r
+ TimingCycles += 10;\r
+ break;\r
+ case 8:\r
+ TimingCycles += 12;\r
+ break;\r
+ case 6:\r
+ case 10:\r
+ TimingCycles += 14;\r
+ break;\r
+ }\r
+\r
+ if (type == 0) /* jsr takes 8 more than jmp */\r
+ TimingCycles += 8;\r
+\r
+ if (mode < 7)\r
+ {\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ }\r
+ EffectiveAddressCalculate(Dest,'L',ECX,TRUE);\r
+\r
+ /* jsr needs to push PC onto stack */\r
+\r
+ if (type == 0)\r
+ {\r
+ PushPC(EBX,EAX,"---D-DB",1);\r
+ }\r
+\r
+ fprintf(fp, "\t\t mov esi,edi\n");\r
+ MemoryBanking(BaseCode);\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+void cmpm(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int regx,leng,regy ;\r
+ int ModeModX, ModeModY;\r
+ char Size=' ' ;\r
+ char * Regname="" ;\r
+ char * RegnameEBX="" ;\r
+\r
+ for (regx = 0 ; regx < 8 ; regx++)\r
+ for (leng = 0 ; leng < 3 ; leng++)\r
+ for (regy = 0 ; regy < 8 ; regy++)\r
+ {\r
+ Opcode = 0xb108 | (regx<<9) | (leng<<6) | regy ;\r
+ BaseCode = Opcode & 0xb1c8 ;\r
+\r
+ ModeModX = 0;\r
+ ModeModY = 0;\r
+\r
+#ifdef A7ROUTINE\r
+ if (leng==0)\r
+ {\r
+ if (regx==7)\r
+ {\r
+ BaseCode |= (regx<<9);\r
+ ModeModX = 16;\r
+ }\r
+\r
+ if (regy==7)\r
+ {\r
+ BaseCode |= regy;\r
+ ModeModY = 16;\r
+ }\r
+ }\r
+#endif\r
+\r
+ switch (leng)\r
+ {\r
+ case 0:\r
+ Size = 'B';\r
+ Regname = regnamesshort[EAX];\r
+ RegnameEBX = regnamesshort[EBX];\r
+ break;\r
+ case 1:\r
+ Size = 'W';\r
+ Regname = regnamesword[EAX];\r
+ RegnameEBX = regnamesword[EBX];\r
+ break;\r
+ case 2:\r
+ Size = 'L';\r
+ Regname = regnameslong[EAX];\r
+ RegnameEBX = regnameslong[EBX];\r
+ break;\r
+ }\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ SavePreviousPC();\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ AddEACycles = 0 ;\r
+\r
+ if (Size != 'L')\r
+ TimingCycles += 12 ;\r
+ else\r
+ TimingCycles += 20 ;\r
+\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+ fprintf(fp, "\t\t and ebx, byte 7\n");\r
+ fprintf(fp, "\t\t shr ecx, byte 9\n");\r
+ fprintf(fp, "\t\t and ecx, byte 7\n");\r
+\r
+ EffectiveAddressRead(3+ModeModY,Size,EBX,EBX,"--C-S-B",FALSE);\r
+ EffectiveAddressRead(3+ModeModX,Size,ECX,EAX,"-B--S-B",FALSE);\r
+\r
+ fprintf(fp, "\t\t cmp %s,%s\n",Regname,RegnameEBX);\r
+ SetFlags(Size,EAX,FALSE,FALSE,FALSE);\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+}\r
+\r
+void exg(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int regx,type,regy ;\r
+ int opmask[3] = { 0x08, 0x09, 0x11} ;\r
+\r
+ for (regx = 0 ; regx < 8 ; regx++)\r
+ for (type = 0 ; type < 3 ; type++)\r
+ for (regy = 0 ; regy < 8 ; regy++)\r
+ {\r
+ Opcode = 0xc100 | (regx<<9) | (opmask[type]<<3) | regy ;\r
+ BaseCode = Opcode & 0xc1c8 ;\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 6 ;\r
+\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+ fprintf(fp, "\t\t and ebx,byte 7\n");\r
+ fprintf(fp, "\t\t shr ecx,byte 9\n");\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+\r
+ if (type == 0)\r
+ {\r
+ fprintf(fp, "\t\t mov eax,[%s+ECX*4]\n",REG_DAT);\r
+ fprintf(fp, "\t\t mov edi,[%s+EBX*4]\n",REG_DAT);\r
+ fprintf(fp, "\t\t mov [%s+ECX*4],edi\n",REG_DAT);\r
+ fprintf(fp, "\t\t mov [%s+EBX*4],eax\n",REG_DAT);\r
+ }\r
+ if (type == 1)\r
+ {\r
+ fprintf(fp, "\t\t mov eax,[%s+ECX*4]\n",REG_ADD);\r
+ fprintf(fp, "\t\t mov edi,[%s+EBX*4]\n",REG_ADD);\r
+ fprintf(fp, "\t\t mov [%s+ECX*4],edi\n",REG_ADD);\r
+ fprintf(fp, "\t\t mov [%s+EBX*4],eax\n",REG_ADD);\r
+ }\r
+ if (type == 2)\r
+ {\r
+ fprintf(fp, "\t\t mov eax,[%s+ECX*4]\n",REG_DAT);\r
+ fprintf(fp, "\t\t mov edi,[%s+EBX*4]\n",REG_ADD);\r
+ fprintf(fp, "\t\t mov [%s+ECX*4],edi\n",REG_DAT);\r
+ fprintf(fp, "\t\t mov [%s+EBX*4],eax\n",REG_ADD);\r
+ }\r
+\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+}\r
+\r
+void ext(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int type,regy ;\r
+\r
+ for (type = 2 ; type < 8 ; type++)\r
+ for (regy = 0 ; regy < 8 ; regy++)\r
+ {\r
+ if (type > 3 && type < 7)\r
+ continue ;\r
+ Opcode = 0x4800 | (type<<6) | regy ;\r
+ BaseCode = Opcode & 0x48c0 ;\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 4 ;\r
+\r
+ fprintf(fp, "\t\t and ecx, byte 7\n");\r
+\r
+ if (type == 2) /* byte to word */\r
+ {\r
+ fprintf(fp, "\t\t movsx eax,byte [%s+ECX*4]\n",REG_DAT);\r
+ fprintf(fp, "\t\t mov [%s+ECX*4],ax\n",REG_DAT);\r
+ SetFlags('W',EAX,TRUE,FALSE,FALSE);\r
+ }\r
+ if (type == 3) /* word to long */\r
+ {\r
+ fprintf(fp, "\t\t movsx eax,word [%s+ECX*4]\n",REG_DAT);\r
+ fprintf(fp, "\t\t mov [%s+ECX*4],eax\n",REG_DAT);\r
+ SetFlags('L',EAX,TRUE,FALSE,FALSE);\r
+ }\r
+ if (type == 7) /* byte to long */\r
+ {\r
+ fprintf(fp, "\t\t movsx eax,byte [%s+ECX*4]\n",REG_DAT);\r
+ fprintf(fp, "\t\t mov [%s+ECX*4],eax\n",REG_DAT);\r
+ SetFlags('L',EAX,TRUE,FALSE,FALSE);\r
+ }\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+}\r
+\r
+void swap(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int sreg ;\r
+\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0x4840 | sreg ;\r
+ BaseCode = Opcode & 0x4840;\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 4 ;\r
+\r
+ fprintf(fp, "\t\t and ecx, byte 7\n");\r
+ fprintf(fp, "\t\t mov eax, dword [%s+ECX*4]\n",REG_DAT);\r
+ fprintf(fp, "\t\t ror eax, 16\n");\r
+ fprintf(fp, "\t\t test eax,eax\n");\r
+ fprintf(fp, "\t\t mov dword [%s+ECX*4],eax\n",REG_DAT);\r
+ SetFlags('L',EAX,FALSE,FALSE,FALSE);\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+}\r
+\r
+/*\r
+ * Line A and Line F commands\r
+ *\r
+ */\r
+\r
+void LineA(void)\r
+{\r
+ int Count;\r
+\r
+ /* Line A */\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(0xA000,0));\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+ Exception(0x0A,0xA000);\r
+\r
+ for (Count=0xA000;Count<0xB000;Count++)\r
+ {\r
+ OpcodeArray[Count] = 0xA000;\r
+ }\r
+}\r
+\r
+void LineF(void)\r
+{\r
+ int Count;\r
+\r
+ /* Line F */\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(0xF000,0));\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+ Exception(0x0B,0xF000);\r
+\r
+ for (Count=0xF000;Count<0x10000;Count++)\r
+ {\r
+ OpcodeArray[Count] = 0xF000;\r
+ }\r
+}\r
+\r
+/*\r
+ * Moves To/From CCR and SR\r
+ *\r
+ * (Move from CCR is 68010 command)\r
+ *\r
+ */\r
+\r
+void movesr(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int type, mode, sreg ;\r
+ int Dest ;\r
+ char allow[] = "0-2345678-------" ;\r
+ char Size;\r
+\r
+ for (type = 0 ; type < 4 ; type++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0x40c0 | (type << 9) | ( mode << 3 ) | sreg ;\r
+\r
+ /* To has extra modes */\r
+\r
+ if (type > 1)\r
+ {\r
+ allow[0x9] = '9';\r
+ allow[0xa] = 'a';\r
+ allow[0xb] = 'b' ;\r
+ }\r
+\r
+ if ((type == 0) | (type == 3))\r
+ Size = 'W'; /* SR */\r
+ else\r
+ Size = 'B'; /* CCR */\r
+\r
+ BaseCode = Opcode & 0x46f8 ;\r
+\r
+ if (mode == 7)\r
+ BaseCode |= sreg ;\r
+\r
+ Dest = EAtoAMN(BaseCode, FALSE);\r
+\r
+ if (allow[Dest&0xf] != '-')\r
+ {\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ char TrueLabel[16];\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ if (type > 1) /* move to */\r
+ TimingCycles += 12 ;\r
+ else\r
+ {\r
+ if (mode < 2)\r
+ TimingCycles += 6 ;\r
+ else\r
+ TimingCycles += 8 ;\r
+ }\r
+\r
+ /* If Move to SR then must be in Supervisor Mode */\r
+\r
+ if (type == 3)\r
+ {\r
+ sprintf(TrueLabel,GenerateLabel(0,1));\r
+\r
+ fprintf(fp, "\t\t test byte [%s],20h \t\t\t; Supervisor Mode ?\n",REG_SRH);\r
+ fprintf(fp, "\t\t je near %s\n\n",TrueLabel);\r
+ }\r
+\r
+ /* 68010 Command ? */\r
+ if (type==1) CheckCPUtype(1);\r
+\r
+\r
+ if (mode < 7)\r
+ {\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ }\r
+\r
+ /* Always read/write word 2 bytes */\r
+ if (type < 2)\r
+ {\r
+ ReadCCR(Size,EBX);\r
+ EffectiveAddressWrite(Dest & 15,'W',ECX,TRUE,"---DS-B",TRUE);\r
+ }\r
+ else\r
+ {\r
+ EffectiveAddressRead(Dest & 15,'W',ECX,EAX,"----S-B",FALSE);\r
+ WriteCCR(Size);\r
+ }\r
+ Completed();\r
+\r
+ /* Exception if not Supervisor Mode */\r
+\r
+ if (type == 3)\r
+ {\r
+ /* Was in User Mode - Exception */\r
+\r
+ fprintf(fp, "%s:\n",TrueLabel);\r
+ Exception(8,BaseCode);\r
+ }\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * Decimal mode Add / Subtracts\r
+ *\r
+ */\r
+\r
+void abcd_sbcd(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int regx,type,rm,regy,mode ;\r
+ int ModeModX;\r
+ int ModeModY;\r
+ char *Label;\r
+\r
+ for (type = 0 ; type < 2 ; type ++) /* 0=sbcd, 1=abcd */\r
+ for (regx = 0 ; regx < 8 ; regx++)\r
+ for (rm = 0 ; rm < 2 ; rm++)\r
+ for (regy = 0 ; regy < 8 ; regy++)\r
+ {\r
+ Opcode = 0x8100 | (type<<14) | (regx<<9) | (rm<<3) | regy ;\r
+ BaseCode = Opcode & 0xc108 ;\r
+\r
+ ModeModX = 0;\r
+ ModeModY = 0;\r
+\r
+ if (rm == 0)\r
+ mode = 0 ;\r
+ else\r
+ {\r
+ mode = 4 ;\r
+\r
+#ifdef A7ROUTINE\r
+\r
+ if (regx == 7)\r
+ {\r
+ BaseCode |= (regx << 9);\r
+ ModeModY = 16;\r
+ }\r
+ if (regy == 7)\r
+ {\r
+ BaseCode |= regy;\r
+ ModeModX = 16;\r
+ }\r
+\r
+#endif\r
+ }\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ if (mode == 4)\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ AddEACycles = 0 ;\r
+\r
+ if (rm == 0)\r
+ TimingCycles += 6 ;\r
+ else\r
+ TimingCycles += 18 ;\r
+\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+ fprintf(fp, "\t\t and ebx, byte 7\n");\r
+ fprintf(fp, "\t\t shr ecx, byte 9\n");\r
+ fprintf(fp, "\t\t and ecx, byte 7\n");\r
+\r
+ EffectiveAddressRead(mode+ModeModX,'B',EBX,EBX,"--C-S-B",TRUE);\r
+ EffectiveAddressRead(mode+ModeModY,'B',ECX,EAX,"-BC-SDB",TRUE);\r
+\r
+ CopyX();\r
+\r
+ if (type == 0)\r
+ {\r
+ fprintf(fp, "\t\t sbb al,bl\n");\r
+ fprintf(fp, "\t\t das\n");\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t adc al,bl\n");\r
+ fprintf(fp, "\t\t daa\n");\r
+ }\r
+\r
+ /* Should only clear Zero flag if not zero */\r
+\r
+ Label = GenerateLabel(0,1);\r
+\r
+ fprintf(fp, "\t\t mov ebx,edx\n");\r
+ fprintf(fp, "\t\t setc dl\n");\r
+\r
+ fprintf(fp, "\t\t jnz short %s\n\n",Label);\r
+\r
+ /* Keep original Zero flag */\r
+ fprintf(fp, "\t\t and bl,40h ; Mask out Old Z\n");\r
+ fprintf(fp, "\t\t or dl,bl ; Copy across\n\n");\r
+\r
+ fprintf(fp, "%s:\n",Label);\r
+\r
+ fprintf(fp, "\t\t mov bl,dl\n"); /* copy carry into sign */\r
+ fprintf(fp, "\t\t and bl,1\n");\r
+ fprintf(fp, "\t\t shl bl,7\n");\r
+ fprintf(fp, "\t\t and dl,7Fh\n");\r
+ fprintf(fp, "\t\t or dl,bl\n");\r
+\r
+ fprintf(fp, "\t\t mov [%s],edx\n",REG_X);\r
+\r
+ EffectiveAddressWrite(mode,'B',ECX,EAX,"---DS-B",TRUE);\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+}\r
+\r
+/*\r
+ * Rotate Left / Right\r
+ *\r
+ */\r
+\r
+void rol_ror(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int dreg, dr, leng, ir, sreg ;\r
+ char Size=' ';\r
+ char * Label ;\r
+ char * Regname="" ;\r
+ char * RegnameECX ;\r
+\r
+ for (dreg = 0 ; dreg < 8 ; dreg++)\r
+ for (dr = 0 ; dr < 2 ; dr++)\r
+ for (leng = 0 ; leng < 3 ; leng++)\r
+ for (ir = 0 ; ir < 2 ; ir++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0xe018 | (dreg<<9) | (dr<<8) | (leng<<6) | (ir<<5) | sreg ;\r
+ BaseCode = Opcode & 0xe1f8 ;\r
+\r
+ switch (leng)\r
+ {\r
+ case 0:\r
+ Size = 'B';\r
+ Regname = regnamesshort[0];\r
+ RegnameECX = regnamesshort[ECX];\r
+ break;\r
+ case 1:\r
+ Size = 'W';\r
+ Regname = regnamesword[0];\r
+ RegnameECX = regnamesword[ECX];\r
+ break;\r
+ case 2:\r
+ Size = 'L';\r
+ Regname = regnameslong[0];\r
+ RegnameECX = regnameslong[ECX];\r
+ break;\r
+ }\r
+\r
+ if (OpcodeArray[ BaseCode ] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ if (Size != 'L')\r
+ TimingCycles += 6 ;\r
+ else\r
+ TimingCycles += 8 ;\r
+\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+ fprintf(fp, "\t\t and ebx,byte 7\n");\r
+ fprintf(fp, "\t\t shr ecx,byte 9\n");\r
+\r
+ if (ir == 0)\r
+ {\r
+ Immediate8();\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ EffectiveAddressRead(0,'L',ECX,ECX,"-B--S-B",FALSE);\r
+ fprintf(fp, "\t\t and ecx,byte 63\n");\r
+ }\r
+\r
+ EffectiveAddressRead(0,Size,EBX,EAX,"-BC-S-B",FALSE);\r
+\r
+ /* shift 0 - no time, no shift and clear carry */\r
+\r
+ Label = GenerateLabel(0,1);\r
+ fprintf(fp, "\t\t jecxz %s\n",Label);\r
+\r
+ /* allow 2 cycles per shift */\r
+\r
+ fprintf(fp, "\t\t mov edx,ecx\n");\r
+ fprintf(fp, "\t\t add edx,edx\n");\r
+ fprintf(fp, "\t\t sub dword [%s],edx\n",ICOUNT);\r
+\r
+ if (dr == 0)\r
+ fprintf(fp, "\t\t ror %s,cl\n",Regname);\r
+ else\r
+ fprintf(fp, "\t\t rol %s,cl\n",Regname);\r
+\r
+ fprintf(fp, "\t\t setc ch\n");\r
+\r
+ fprintf(fp, "%s:\n",Label);\r
+\r
+ SetFlags(Size,EAX,TRUE,FALSE,FALSE);\r
+/* fprintf(fp, "\t\t and dl,254\n"); Test clears Carry */\r
+ fprintf(fp, "\t\t or dl,ch\n");\r
+\r
+ EffectiveAddressWrite(0,Size,EBX,EAX,"--C-S-B",TRUE);\r
+\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+}\r
+\r
+void rol_ror_ea(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int dr, mode, sreg ;\r
+ int Dest ;\r
+ char allow[] = "--2345678-------" ;\r
+\r
+ for (dr = 0 ; dr < 2 ; dr++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0xe6c0 | (dr<<8) | (mode<<3) | sreg ;\r
+ BaseCode = Opcode & 0xfff8 ;\r
+\r
+ if (mode == 7)\r
+ BaseCode |= sreg ;\r
+\r
+ Dest = EAtoAMN(BaseCode, FALSE);\r
+\r
+ if (allow[Dest&0xf] != '-')\r
+ {\r
+ if (OpcodeArray[ BaseCode ] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 8 ;\r
+\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ EffectiveAddressRead(Dest&0xf,'W',ECX,EAX,"--C-SDB",FALSE);\r
+\r
+ if (dr == 0)\r
+ fprintf(fp, "\t\t ror ax,1\n");\r
+ else\r
+ fprintf(fp, "\t\t rol ax,1\n");\r
+\r
+ fprintf(fp, "\t\t setc bl\n");\r
+ SetFlags('W',EAX,TRUE,FALSE,FALSE);\r
+/* fprintf(fp, "\t\t and dl,254\n"); Test clears Carry */\r
+ fprintf(fp, "\t\t or dl,bl\n");\r
+\r
+ EffectiveAddressWrite(Dest&0xf,'W',ECX,EAX,"---DS-B",TRUE);\r
+\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * Logical Shift Left / Right\r
+ *\r
+ */\r
+\r
+void lsl_lsr(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int dreg, dr, leng, ir, sreg ;\r
+ char Size=' ';\r
+ char * Regname="" ;\r
+ char * RegnameECX="" ;\r
+ char * RegnameEDX="" ;\r
+ char * Label ;\r
+\r
+ for (dreg = 0 ; dreg < 8 ; dreg++)\r
+ for (dr = 0 ; dr < 2 ; dr++)\r
+ for (leng = 0 ; leng < 3 ; leng++)\r
+ for (ir = 0 ; ir < 2 ; ir++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0xe008 | (dreg<<9) | (dr<<8) | (leng<<6) | (ir<<5) | sreg ;\r
+ BaseCode = Opcode & 0xe1f8 ;\r
+\r
+ switch (leng)\r
+ {\r
+ case 0:\r
+ Size = 'B';\r
+ Regname = regnamesshort[0];\r
+ RegnameECX = regnamesshort[ECX];\r
+ RegnameEDX = regnamesshort[EDX];\r
+ break;\r
+ case 1:\r
+ Size = 'W';\r
+ Regname = regnamesword[0];\r
+ RegnameECX = regnamesword[ECX];\r
+ RegnameEDX = regnamesword[EDX];\r
+ break;\r
+ case 2:\r
+ Size = 'L';\r
+ Regname = regnameslong[0];\r
+ RegnameECX = regnameslong[ECX];\r
+ RegnameEDX = regnameslong[EDX];\r
+ break;\r
+ }\r
+\r
+ if (OpcodeArray[ BaseCode ] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ if (Size != 'L')\r
+ TimingCycles += 6 ;\r
+ else\r
+ TimingCycles += 8 ;\r
+\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+ fprintf(fp, "\t\t and ebx,byte 7\n");\r
+ fprintf(fp, "\t\t shr ecx,byte 9\n");\r
+\r
+ if (ir == 0)\r
+ {\r
+ Immediate8();\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ EffectiveAddressRead(0,'L',ECX,ECX,"-B--S-B",FALSE);\r
+ fprintf(fp, "\t\t and ecx,byte 63\n");\r
+ }\r
+\r
+ /* and 2 cycles per shift */\r
+\r
+ fprintf(fp, "\t\t mov edx,ecx\n");\r
+ fprintf(fp, "\t\t add edx,edx\n");\r
+ fprintf(fp, "\t\t sub dword [%s],edx\n",ICOUNT);\r
+\r
+ EffectiveAddressRead(0,Size,EBX,EAX,"-BC-S-B",FALSE);\r
+\r
+ /* ASG: on the 68k, the shift count is mod 64; on the x86, the */\r
+ /* shift count is mod 32; we need to check for shifts of 32-63 */\r
+ /* and produce zero */\r
+ Label = GenerateLabel(0,1);\r
+ fprintf(fp, "\t\t test cl,0x20\n");\r
+ fprintf(fp, "\t\t jnz %s_BigShift\n",Label);\r
+\r
+ fprintf(fp, "%s_Continue:\n",Label);\r
+ if (dr == 0)\r
+ fprintf(fp, "\t\t shr %s,cl\n",Regname);\r
+ else\r
+ fprintf(fp, "\t\t shl %s,cl\n",Regname);\r
+\r
+ SetFlags(Size,EAX,FALSE,FALSE,FALSE);\r
+\r
+ /* Clear Overflow flag */\r
+ fprintf(fp, "\t\t xor dh,dh\n");\r
+\r
+ EffectiveAddressWrite(0,Size,EBX,EAX,"--CDS-B",TRUE);\r
+\r
+ /* if shift count is zero clear carry */\r
+\r
+ fprintf(fp, "\t\t jecxz %s\n",Label);\r
+\r
+ fprintf(fp, "\t\t mov [%s],edx\n",REG_X);\r
+ Completed();\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",Label);\r
+ fprintf(fp, "\t\t and dl,254\t\t;clear C flag\n");\r
+ Completed();\r
+\r
+ fprintf(fp, "%s_BigShift:\n",Label);\r
+ if (dr == 0)\r
+ {\r
+ fprintf(fp, "\t\t shr %s,16\n",Regname);\r
+ fprintf(fp, "\t\t shr %s,16\n",Regname);\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t shl %s,16\n",Regname);\r
+ fprintf(fp, "\t\t shl %s,16\n",Regname);\r
+ }\r
+ fprintf(fp, "\t\t jmp %s_Continue\n",Label);\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+}\r
+\r
+void lsl_lsr_ea(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int dr, mode, sreg ;\r
+ int Dest ;\r
+ char allow[] = "--2345678-------" ;\r
+\r
+ for (dr = 0 ; dr < 2 ; dr++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0xe2c0 | (dr<<8) | (mode<<3) | sreg ;\r
+ BaseCode = Opcode & 0xfff8 ;\r
+\r
+ if (mode == 7)\r
+ BaseCode |= sreg ;\r
+\r
+ Dest = EAtoAMN(BaseCode, FALSE);\r
+\r
+ if (allow[Dest&0xf] != '-')\r
+ {\r
+ if (OpcodeArray[ BaseCode ] == -2)\r
+ {\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 8 ;\r
+\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ EffectiveAddressRead(Dest&0xf,'W',ECX,EAX,"--C-SDB",FALSE);\r
+\r
+ if (dr == 0)\r
+ fprintf(fp, "\t\t shr ax,1\n");\r
+ else\r
+ fprintf(fp, "\t\t shl ax,1\n");\r
+\r
+ SetFlags('W',EAX,FALSE,TRUE,FALSE);\r
+\r
+ /* Clear Overflow flag */\r
+\r
+ fprintf(fp, "\t\t xor dh,dh\n");\r
+\r
+ EffectiveAddressWrite(Dest&0xf,'W',ECX,EAX,"---DS-B",TRUE);\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * Rotate Left / Right though Extend\r
+ *\r
+ */\r
+\r
+void roxl_roxr(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int dreg, dr, leng, ir, sreg ;\r
+ char Size=' ' ;\r
+ char * Regname="" ;\r
+ char * RegnameECX="" ;\r
+ char * Label ;\r
+\r
+ for (dreg = 0 ; dreg < 8 ; dreg++)\r
+ for (dr = 0 ; dr < 2 ; dr++)\r
+ for (leng = 0 ; leng < 3 ; leng++)\r
+ for (ir = 0 ; ir < 2 ; ir++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0xe010 | (dreg<<9) | (dr<<8) | (leng<<6) | (ir<<5) | sreg ;\r
+ BaseCode = Opcode & 0xe1f8 ;\r
+\r
+ switch (leng)\r
+ {\r
+ case 0:\r
+ Size = 'B';\r
+ Regname = regnamesshort[0];\r
+ RegnameECX = regnamesshort[ECX];\r
+ break;\r
+ case 1:\r
+ Size = 'W';\r
+ Regname = regnamesword[0];\r
+ RegnameECX = regnamesword[ECX];\r
+ break;\r
+ case 2:\r
+ Size = 'L';\r
+ Regname = regnameslong[0];\r
+ RegnameECX = regnameslong[ECX];\r
+ break;\r
+ }\r
+\r
+ if (OpcodeArray[ BaseCode ] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ if (Size != 'L')\r
+ TimingCycles += 6 ;\r
+ else\r
+ TimingCycles += 8 ;\r
+\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+ fprintf(fp, "\t\t and ebx,byte 7\n");\r
+ fprintf(fp, "\t\t shr ecx,byte 9\n");\r
+\r
+ if (ir == 0)\r
+ {\r
+ Immediate8();\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ EffectiveAddressRead(0,'L',ECX,ECX,"-B--S-B",FALSE);\r
+ fprintf(fp, "\t\t and ecx,byte 63\n");\r
+ }\r
+\r
+ /* allow 2 cycles per shift */\r
+\r
+ fprintf(fp, "\t\t mov edx,ecx\n");\r
+ fprintf(fp, "\t\t add edx,edx\n");\r
+ fprintf(fp, "\t\t sub dword [%s],edx\n",ICOUNT);\r
+\r
+ EffectiveAddressRead(0,Size,EBX,EAX,"-BC-SDB",FALSE);\r
+\r
+ /* move X into C so RCR & RCL can be used */\r
+ /* RCR & RCL only set the carry flag */\r
+\r
+ CopyX();\r
+\r
+ if (dr == 0)\r
+ fprintf(fp, "\t\t rcr %s,cl\n",Regname);\r
+ else\r
+ fprintf(fp, "\t\t rcl %s,cl\n",Regname);\r
+\r
+ fprintf(fp, "\t\t setc ch\n");\r
+ SetFlags(Size,EAX,TRUE,FALSE,FALSE);\r
+/* fprintf(fp, "\t\t and dl,254\n"); Test Clears Carry */\r
+\r
+ EffectiveAddressWrite(0,Size,EBX,EAX,"--CDS-B",TRUE);\r
+\r
+ /* if shift count is zero clear carry */\r
+\r
+ Label = GenerateLabel(0,1);\r
+ fprintf(fp, "\t\t test cl,cl\n");\r
+ fprintf(fp, "\t\t jz %s\n",Label);\r
+\r
+ /* Add in Carry Flag */\r
+\r
+ fprintf(fp, "\t\t or dl,ch\n");\r
+ fprintf(fp, "\t\t mov [%s],dl\n",REG_X);\r
+ Completed();\r
+\r
+\r
+ /* copy X onto C when shift is zero */\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",Label);\r
+ fprintf(fp, "\t\t mov ecx,[%s]\n",REG_X);\r
+ fprintf(fp, "\t\t and ecx,byte 1\n");\r
+ fprintf(fp, "\t\t or edx,ecx\n");\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+}\r
+\r
+void roxl_roxr_ea(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int dr, mode, sreg ;\r
+ int Dest ;\r
+ char allow[] = "--2345678-------" ;\r
+\r
+ for (dr = 0 ; dr < 2 ; dr++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0xe4c0 | (dr<<8) | (mode<<3) | sreg ;\r
+ BaseCode = Opcode & 0xfff8 ;\r
+\r
+ if (mode == 7)\r
+ BaseCode |= sreg ;\r
+\r
+ Dest = EAtoAMN(BaseCode, FALSE);\r
+\r
+ if (allow[Dest&0xf] != '-')\r
+ {\r
+ if (OpcodeArray[ BaseCode ] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 8 ;\r
+\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ EffectiveAddressRead(Dest&0xf,'W',ECX,EAX,"--C-SDB",FALSE);\r
+\r
+ /* move X into C so RCR & RCL can be used */\r
+ /* RCR & RCL only set the carry flag */\r
+\r
+ CopyX();\r
+\r
+ if (dr == 0)\r
+ fprintf(fp, "\t\t rcr ax,1\n");\r
+ else\r
+ fprintf(fp, "\t\t rcl ax,1\n");\r
+\r
+ fprintf(fp, "\t\t setc bl\n");\r
+ SetFlags('W',EAX,TRUE,FALSE,FALSE);\r
+/* fprintf(fp, "\t\t and dl,254\n"); - Intel Clears on Test */\r
+ fprintf(fp, "\t\t or dl,bl\n");\r
+\r
+ EffectiveAddressWrite(Dest&0xf,'W',ECX,EAX,"---DS-B",TRUE);\r
+\r
+ fprintf(fp, "\t\t mov [%s],edx\n",REG_X);\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * Arithmetic Shift Left / Right\r
+ *\r
+ */\r
+\r
+void asl_asr(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int dreg, dr, leng, ir, sreg ;\r
+ char Size=' ';\r
+ char * Sizename="" ;\r
+ char * Regname="" ;\r
+ char * RegnameEDX="" ;\r
+ char * RegnameECX="" ;\r
+ char * Label;\r
+\r
+ /* Normal routines for codes */\r
+\r
+ for (dreg = 0 ; dreg < 8 ; dreg++)\r
+ for (dr = 0 ; dr < 2 ; dr++)\r
+ for (leng = 0 ; leng < 3 ; leng++)\r
+ for (ir = 0 ; ir < 2 ; ir++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0xe000 | (dreg<<9) | (dr<<8) | (leng<<6) | (ir<<5) | sreg ;\r
+ BaseCode = Opcode & 0xe1f8 ;\r
+\r
+ switch (leng)\r
+ {\r
+ case 0:\r
+ Size = 'B';\r
+ Regname = regnamesshort[0];\r
+ RegnameECX = regnamesshort[ECX];\r
+ RegnameEDX = regnamesshort[EDX];\r
+ break;\r
+ case 1:\r
+ Size = 'W';\r
+ Regname = regnamesword[0];\r
+ RegnameECX = regnamesword[ECX];\r
+ RegnameEDX = regnamesword[EDX];\r
+ break;\r
+ case 2:\r
+ Size = 'L';\r
+ Regname = regnameslong[0];\r
+ RegnameECX = regnameslong[ECX];\r
+ RegnameEDX = regnameslong[EDX];\r
+ break;\r
+ }\r
+\r
+ if (OpcodeArray[ BaseCode ] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ Label = GenerateLabel(0,1);\r
+\r
+ if (Size != 'L')\r
+ TimingCycles += 6 ;\r
+ else\r
+ TimingCycles += 8 ;\r
+\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+ fprintf(fp, "\t\t and ebx,byte 7\n");\r
+ fprintf(fp, "\t\t shr ecx,byte 9\n");\r
+\r
+ EffectiveAddressRead(0,Size,EBX,EAX,"-BC-S-B",FALSE);\r
+\r
+ if (ir == 0)\r
+ {\r
+ Immediate8();\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ EffectiveAddressRead(0,'L',ECX,ECX,"-B--S-B",FALSE);\r
+ fprintf(fp, "\t\t and ecx,byte 63\n");\r
+ fprintf(fp, "\t\t jz short %s\n",Label);\r
+ }\r
+\r
+ /* allow 2 cycles per shift */\r
+\r
+ fprintf(fp, "\t\t mov edx,ecx\n");\r
+ fprintf(fp, "\t\t add edx,edx\n");\r
+ fprintf(fp, "\t\t sub dword [%s],edx\n",ICOUNT);\r
+\r
+ if (dr == 0)\r
+ {\r
+ /* ASR */\r
+\r
+ /* ASG: on the 68k, the shift count is mod 64; on the x86, the */\r
+ /* shift count is mod 32; we need to check for shifts of 32-63 */\r
+ /* and effectively shift 31 */\r
+ fprintf(fp, "\t\t shrd edx,ecx,6\n");\r
+ fprintf(fp, "\t\t sar edx,31\n");\r
+ fprintf(fp, "\t\t and edx,31\n");\r
+ fprintf(fp, "\t\t or ecx,edx\n");\r
+\r
+ fprintf(fp, "\t\t sar %s,cl\n",Regname);\r
+\r
+ /* Mode 0 write does not affect Flags */\r
+ EffectiveAddressWrite(0,Size,EBX,EAX,"---DS-B",TRUE);\r
+\r
+ /* Update Flags */\r
+ fprintf(fp, "\t\t lahf\n");\r
+\r
+#ifdef STALLCHECK\r
+ ClearRegister(EDX);\r
+ fprintf(fp, "\t\t mov dl,ah\n");\r
+#else\r
+ fprintf(fp, "\t\t movzx edx,ah\n");\r
+#endif\r
+\r
+ fprintf(fp, "\t\t mov [%s],edx\n",REG_X);\r
+ }\r
+ else\r
+ {\r
+ /* ASL */\r
+\r
+ /* Check to see if Overflow should be set */\r
+\r
+ fprintf(fp,"\t\t mov edi,eax\t\t; Save It\n");\r
+\r
+ ClearRegister(EDX);\r
+ fprintf(fp,"\t\t stc\n");\r
+ fprintf(fp,"\t\t rcr %s,1\t\t; d=1xxxx\n",RegnameEDX);\r
+ fprintf(fp,"\t\t sar %s,cl\t\t; d=1CCxx\n",RegnameEDX);\r
+ fprintf(fp,"\t\t and eax,edx\n");\r
+ fprintf(fp,"\t\t jz short %s_V\t\t; No Overflow\n",Label);\r
+ fprintf(fp,"\t\t cmp eax,edx\n");\r
+ fprintf(fp,"\t\t je short %s_V\t\t; No Overflow\n",Label);\r
+\r
+ /* Set Overflow */\r
+ fprintf(fp,"\t\t mov edx,0x800\n");\r
+ fprintf(fp,"\t\t jmp short %s_OV\n",Label);\r
+\r
+ fprintf(fp,"%s_V:\n",Label);\r
+ ClearRegister(EDX);\r
+\r
+ fprintf(fp,"%s_OV:\n",Label);\r
+\r
+ /* more than 31 shifts and long */\r
+\r
+ if ((ir==1) && (leng==2))\r
+ {\r
+ fprintf(fp,"\t\t test cl,0x20\n");\r
+ fprintf(fp,"\t\t jnz short %s_32\n\n",Label);\r
+ }\r
+\r
+ fprintf(fp,"\t\t mov eax,edi\t\t; Restore It\n");\r
+\r
+ fprintf(fp, "\t\t sal %s,cl\n",Regname);\r
+\r
+ EffectiveAddressWrite(0,Size,EBX,EAX,"---DS-B",TRUE);\r
+ fprintf(fp, "\t\t lahf\n");\r
+ fprintf(fp, "\t\t mov dl,ah\n");\r
+ fprintf(fp, "\t\t mov [%s],edx\n",REG_X);\r
+ }\r
+ Completed();\r
+\r
+ if (ir != 0)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",Label);\r
+\r
+\r
+ if (dr == 0)\r
+ {\r
+ /* ASR - Test clears V and C */\r
+ SetFlags(Size,EAX,TRUE,FALSE,FALSE);\r
+ }\r
+ else\r
+ {\r
+ /* ASL - Keep existing Carry flag, Clear V */\r
+ fprintf(fp, "\t\t mov ebx,edx\n");\r
+ fprintf(fp, "\t\t and ebx,byte 1\n");\r
+ SetFlags(Size,EAX,TRUE,FALSE,FALSE);\r
+ fprintf(fp, "\t\t or edx,ebx\n");\r
+\r
+ if (leng==2)\r
+ {\r
+ Completed();\r
+\r
+ /* > 31 Shifts */\r
+\r
+ fprintf(fp, "%s_32:\n",Label);\r
+ fprintf(fp, "\t\t mov dl,40h\n"); // Zero flag\r
+ ClearRegister(EAX);\r
+ EffectiveAddressWrite(0,Size,EBX,EAX,"----S-B",TRUE);\r
+ }\r
+ }\r
+\r
+ Completed();\r
+ }\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+\r
+ /* End with special routines for ASL.x #1,Dx */\r
+ /* To do correct V setting, ASL needs quite a */\r
+ /* bit of additional code. A Shift of one has */\r
+ /* correct flags on Intel, and is very common */\r
+ /* in 68000 programs. */\r
+\r
+ for (leng = 0 ; leng < 3 ; leng++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0xe300 | (leng<<6) | sreg ;\r
+ BaseCode = Opcode & 0xe3c8 ;\r
+\r
+ switch (leng)\r
+ {\r
+ case 0:\r
+ Sizename = "byte";\r
+ break;\r
+ case 1:\r
+ Sizename = "word";\r
+ break;\r
+ case 2:\r
+ Sizename = "long";\r
+ break;\r
+ }\r
+\r
+ if (sreg == 0)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ Label = GenerateLabel(0,1);\r
+\r
+ if (Size != 'L')\r
+ TimingCycles += 6 ;\r
+ else\r
+ TimingCycles += 8 ;\r
+\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ fprintf(fp, "\t\t sal %s [%s+ecx*4],1\n",Sizename,REG_DAT);\r
+ SetFlags('L',EAX,FALSE,TRUE,FALSE);\r
+ Completed();\r
+\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+}\r
+\r
+void asl_asr_ea(void)\r
+{\r
+ int Opcode, BaseCode ;\r
+ int dr, mode, sreg ;\r
+ int Dest ;\r
+ char allow[] = "--2345678-------" ;\r
+\r
+ for (dr = 0 ; dr < 2 ; dr++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0xe0c0 | (dr<<8) | (mode<<3) | sreg ;\r
+ BaseCode = Opcode & 0xfff8 ;\r
+\r
+ if (mode == 7)\r
+ BaseCode |= sreg ;\r
+\r
+ Dest = EAtoAMN(BaseCode, FALSE);\r
+\r
+ if (allow[Dest&0xf] != '-')\r
+ {\r
+ if (OpcodeArray[ BaseCode ] == -2)\r
+ {\r
+\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+ TimingCycles += 8 ;\r
+\r
+ fprintf(fp, "\t\t and ecx,byte 7\n");\r
+ EffectiveAddressRead(Dest&0xf,'W',ECX,EAX,"--C-SDB",FALSE);\r
+\r
+ if (dr == 0)\r
+ fprintf(fp, "\t\t sar ax,1\n");\r
+ else\r
+ fprintf(fp, "\t\t sal ax,1\n");\r
+\r
+ SetFlags('W',EAX,FALSE,TRUE,TRUE);\r
+\r
+ EffectiveAddressWrite(Dest&0xf,'W',ECX,EAX,"----S-B",FALSE);\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * Divide Commands\r
+ */\r
+\r
+void divides(void)\r
+{\r
+ int dreg, type, mode, sreg ;\r
+ int Opcode, BaseCode ;\r
+ int Dest ;\r
+ char allow[] = "0-23456789ab-----" ;\r
+ char TrapLabel[16];\r
+ int Cycles;\r
+\r
+ int divide_cycles[12] =\r
+ {\r
+ 38,0,42,42,44,46,50,46,50,46,48,42\r
+ };\r
+\r
+ for (dreg = 0 ; dreg < 8 ; dreg++)\r
+ for (type = 0 ; type < 2 ; type++)\r
+ for (mode = 0 ; mode < 8 ; mode++)\r
+ for (sreg = 0 ; sreg < 8 ; sreg++)\r
+ {\r
+ Opcode = 0x80c0 | (dreg<<9) | (type<<8) | (mode<<3) | sreg ;\r
+ BaseCode = Opcode & 0x81f8 ;\r
+ if (mode == 7)\r
+ {\r
+ BaseCode |= sreg ;\r
+ }\r
+\r
+ Dest = EAtoAMN(Opcode, FALSE);\r
+ if (allow[Dest&0x0f] != '-')\r
+ {\r
+ if (OpcodeArray[ BaseCode ] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ if ((Dest >= 2) && (Dest <=10))\r
+ SavePreviousPC();\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n\n");\r
+\r
+\r
+ /* Save EDX (in case of overflow) */\r
+\r
+ fprintf(fp, "\t\t and edx,byte -2\n");\r
+ fprintf(fp, "\t\t mov [%s],edx\n",REG_CCR);\r
+\r
+\r
+ /* Cycle Timing (if succeeds OK) */\r
+\r
+ Cycles = divide_cycles[Dest & 0x0f] + 95 + (type * 17);\r
+\r
+ if (Cycles > 127)\r
+ fprintf(fp, "\t\t sub dword [%s],%d\n",ICOUNT,Cycles);\r
+ else\r
+ fprintf(fp, "\t\t sub dword [%s],byte %d\n",ICOUNT,Cycles);\r
+\r
+ if (mode < 7)\r
+ {\r
+ fprintf(fp, "\t\t mov ebx,ecx\n");\r
+ fprintf(fp, "\t\t and ebx,byte 7\n");\r
+ }\r
+\r
+ fprintf(fp, "\t\t shr ecx, byte 9\n");\r
+ fprintf(fp, "\t\t and ecx, byte 7\n");\r
+\r
+ sprintf(TrapLabel, "%s", GenerateLabel(0,1) ) ;\r
+\r
+ EffectiveAddressRead(Dest,'W',EBX,EAX,"A-C-SDB",FALSE); /* source */\r
+\r
+ fprintf(fp, "\t\t test ax,ax\n");\r
+ fprintf(fp, "\t\t je near %s_ZERO\t\t;do div by zero trap\n", TrapLabel);\r
+\r
+ if (type == 1) /* signed */\r
+ {\r
+ fprintf(fp, "\t\t movsx ebx,ax\n");\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t movzx ebx,ax\n");\r
+ }\r
+\r
+ EffectiveAddressRead(0,'L',ECX,EAX,"ABC-SDB",FALSE); /* dest */\r
+\r
+ if (type == 1) /* signed */\r
+ {\r
+ fprintf(fp, "\t\t cdq\n"); /* EDX:EAX = 64 bit signed */\r
+ fprintf(fp, "\t\t idiv ebx\n"); /* EBX = 32 bit */\r
+\r
+ /* Check for Overflow */\r
+\r
+ fprintf(fp, "\t\t movsx ebx,ax\n");\r
+ fprintf(fp, "\t\t cmp eax,ebx\n");\r
+ fprintf(fp, "\t\t jne short %s_OVER\n",TrapLabel);\r
+ }\r
+ else\r
+ {\r
+ ClearRegister(EDX);\r
+ fprintf(fp, "\t\t div ebx\n");\r
+\r
+ /* Check for Overflow */\r
+\r
+ fprintf(fp, "\t\t test eax, 0FFFF0000H\n");\r
+ fprintf(fp, "\t\t jnz short %s_OVER\n",TrapLabel);\r
+ }\r
+\r
+ /* Sort out Result */\r
+\r
+ fprintf(fp, "\t\t shl edx, byte 16\n");\r
+ fprintf(fp, "\t\t mov dx,ax\n");\r
+ fprintf(fp, "\t\t mov [%s+ECX*4],edx\n",REG_DAT);\r
+ SetFlags('W',EDX,TRUE,FALSE,FALSE);\r
+\r
+ Completed();\r
+\r
+\r
+ /* Overflow */\r
+\r
+ Align();\r
+ fprintf(fp, "%s_OVER:\n",TrapLabel);\r
+ fprintf(fp, "\t\t mov edx,[%s]\n",REG_CCR);\r
+ fprintf(fp, "\t\t or edx,0x0800\t\t;V flag\n");\r
+ Completed();\r
+\r
+\r
+ /* Division by Zero */\r
+\r
+ Align();\r
+ fprintf(fp, "%s_ZERO:\t\t ;Do divide by zero trap\n", TrapLabel);\r
+\r
+ /* Correct cycle counter for error */\r
+\r
+ fprintf(fp, "\t\t add dword [%s],byte %d\n",ICOUNT,95 + (type * 17));\r
+ fprintf(fp, "\t\t mov al,5\n");\r
+ Exception(-1,BaseCode);\r
+ Completed();\r
+ }\r
+\r
+ OpcodeArray[Opcode] = BaseCode ;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * 68010 Extra Opcodes\r
+ *\r
+ * move from CCR is done above\r
+ *\r
+ */\r
+\r
+void ReturnandDeallocate(void)\r
+{\r
+ int BaseCode = 0x4e74 ;\r
+\r
+ if (OpcodeArray[BaseCode] == -2)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode,0));\r
+\r
+ CheckCPUtype(1);\r
+\r
+ SavePreviousPC();\r
+\r
+ TimingCycles += 16;\r
+\r
+ OpcodeArray[BaseCode] = BaseCode ;\r
+\r
+ /* Get Return Address */\r
+\r
+ fprintf(fp, "\t\t mov eax,[%s]\n",REG_A7);\r
+ Memory_Read('L',EAX,"---D--B",1);\r
+\r
+\r
+ /* Get Displacement */\r
+\r
+ Memory_Fetch('W',EBX,TRUE);\r
+\r
+\r
+ /* Set PC = New Address */\r
+\r
+ fprintf(fp, "\t\t mov esi,eax\n");\r
+\r
+\r
+ /* Correct Stack for Return Address and Displacement */\r
+\r
+ fprintf(fp, "\t\t add ebx,byte 4\n");\r
+ fprintf(fp, "\t\t add dword [%s],ebx\n",REG_A7);\r
+\r
+ MemoryBanking(BaseCode);\r
+ Completed();\r
+ }\r
+}\r
+\r
+void MoveControlRegister(void)\r
+{\r
+ int Direction;\r
+ int BaseCode = 0x4e7a ;\r
+\r
+ for (Direction=0;Direction<2;Direction++)\r
+ {\r
+ Align();\r
+ fprintf(fp, "%s:\n",GenerateLabel(BaseCode+Direction,0));\r
+\r
+ TimingCycles += 4; /* Assume same as move usp */\r
+\r
+ CheckCPUtype(1);\r
+\r
+ fprintf(fp, "\t\t test byte [%s],20h \t\t\t; Supervisor Mode ?\n",REG_SRH);\r
+ fprintf(fp, "\t\t jz short OP%d_%4.4x_Trap\n",CPU,BaseCode+Direction);\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n");\r
+ if (CPU==2)\r
+ fprintf(fp, "\t\t xor esi,2\n"); /* ASG */\r
+#ifdef STALLCHECK\r
+ ClearRegister(EBX);\r
+ fprintf(fp, "\t\t mov bx,[esi+ebp]\n");\r
+#else\r
+ fprintf(fp, "\t\t movzx ebx,word [esi+ebp]\n");\r
+#endif\r
+ if (CPU==2)\r
+ fprintf(fp, "\t\t xor esi,2\n"); /* ASG */\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n");\r
+ fprintf(fp, "\t\t mov eax,ebx\n");\r
+ fprintf(fp, "\t\t mov ecx,ebx\n");\r
+\r
+ /* Sort out Register */\r
+\r
+ fprintf(fp, "\t\t shr ebx,12\n");\r
+\r
+ /* Sort out Control Register ID */\r
+\r
+ fprintf(fp, "\t\t and eax,byte 1\n");\r
+ fprintf(fp, "\t\t shr ecx,10\n");\r
+ fprintf(fp, "\t\t and ecx,2\n");\r
+ fprintf(fp, "\t\t or ecx,eax\n");\r
+\r
+ if (Direction==0)\r
+ {\r
+ /* from Control */\r
+\r
+ fprintf(fp, "\t\t mov eax,[%s+ecx*4]\n",REG_SFC);\r
+ fprintf(fp, "\t\t mov %s,eax\n",REG_DAT_EBX);\r
+ }\r
+ else\r
+ {\r
+ /* To Control */\r
+\r
+ fprintf(fp, "\t\t mov eax,%s\n",REG_DAT_EBX);\r
+\r
+ /* Mask out for SFC & DFC */\r
+\r
+ fprintf(fp, "\t\t test cl,2\n");\r
+ fprintf(fp, "\t\t jne short OP%d_%4.4x_Mask\n",CPU,BaseCode+Direction);\r
+ fprintf(fp, "\t\t and eax,byte 7\n");\r
+ fprintf(fp, "OP%d_%4.4x_Mask:\n",CPU,BaseCode+Direction);\r
+\r
+ /* Write to control */\r
+\r
+ fprintf(fp, "\t\t mov [%s+ecx*4],eax\n",REG_SFC);\r
+ }\r
+\r
+ Completed();\r
+\r
+ /* Not Supervisor Mode */\r
+\r
+ Align();\r
+ fprintf(fp, "OP%d_%4.4x_Trap:\n",CPU,BaseCode+Direction);\r
+ Exception(8,BaseCode+Direction);\r
+\r
+ OpcodeArray[BaseCode+Direction] = BaseCode+Direction;\r
+ }\r
+}\r
+\r
+void MoveAddressSpace(void)\r
+{\r
+}\r
+\r
+/*\r
+ * Generate Jump Table\r
+ *\r
+ */\r
+\r
+void JumpTable(void)\r
+{\r
+ int Opcode,l,op;\r
+\r
+ fprintf(fp, "DD OP%d_1000\n",CPU);\r
+\r
+ l = 0 ;\r
+ for (Opcode=0x0;Opcode<0x10000;)\r
+ {\r
+\r
+ op = OpcodeArray[Opcode];\r
+\r
+ fprintf(fp, "DD ");\r
+\r
+ l = 1 ;\r
+ while (op == OpcodeArray[Opcode+l] && ((Opcode+l) & 0xfff) != 0)\r
+ {\r
+ l++ ;\r
+ }\r
+\r
+ Opcode += l ;\r
+\r
+ if (l > 255)\r
+ {\r
+ if (op > -1)\r
+ fprintf(fp, "OP%d_%4.4x - OP%d_1000\n",CPU,op,CPU);\r
+ else\r
+ fprintf(fp, "ILLEGAL - OP%d_1000\n",CPU);\r
+\r
+ fprintf(fp, "DW %d\n", l);\r
+ }\r
+ else\r
+ {\r
+ if (op > -1)\r
+ fprintf(fp, "(OP%d_%4.4x - OP%d_1000) + (%d * 1000000h)\n",CPU,op,CPU,l);\r
+ else\r
+ fprintf(fp, "(ILLEGAL - OP%d_1000) + (%d * 1000000h)\n",CPU,l);\r
+ }\r
+ }\r
+}\r
+\r
+void CodeSegmentBegin(void)\r
+{\r
+\r
+/* Messages */\r
+\r
+ fprintf(fp, "; Make68K - V%s - Copyright 1998, Mike Coates (mame@btinternet.com)\n", VERSION);\r
+ fprintf(fp, "; & Darren Olafson (deo@mail.island.net)\n\n");\r
+\r
+/* Needed code to make it work! */\r
+\r
+ fprintf(fp, "\t\t BITS 32\n\n");\r
+\r
+ fprintf(fp, "\t\t GLOBAL %s_RUN\n",CPUtype);\r
+ fprintf(fp, "\t\t GLOBAL %s_RESET\n",CPUtype);\r
+ fprintf(fp, "\t\t GLOBAL %s_regs\n",CPUtype);\r
+ fprintf(fp, "\t\t GLOBAL %s_COMPTABLE\n",CPUtype);\r
+ fprintf(fp, "\t\t GLOBAL %s_OPCODETABLE\n",CPUtype);\r
+\r
+ /* ASG - only one interface to memory now */\r
+ fprintf(fp, "\t\t EXTERN _m68k_ICount\n");\r
+ fprintf(fp, "\t\t EXTERN _a68k_memory_intf\n");\r
+ fprintf(fp, "\t\t EXTERN _mem_amask\n");\r
+\r
+ fprintf(fp, "; Vars Mame declares / needs access to\n\n");\r
+\r
+ fprintf(fp, "\t\t EXTERN _mame_debug\n");\r
+ fprintf(fp, "\t\t EXTERN _illegal_op\n");\r
+ fprintf(fp, "\t\t EXTERN _illegal_pc\n");\r
+\r
+ fprintf(fp, "\t\t EXTERN _OP_ROM\n");\r
+ fprintf(fp, "\t\t EXTERN _OP_RAM\n");\r
+\r
+ fprintf(fp, "\t\t EXTERN _opcode_entry\n");\r
+ fprintf(fp, "\t\t EXTERN _cur_mrhard\n");\r
+\r
+//#ifdef MAME_DEBUG\r
+ fprintf(fp, "\t\t EXTERN _m68k_illegal_opcode\n");\r
+//#endif\r
+\r
+#ifdef OS2\r
+ fprintf(fp, "\t\t SECTION maincode USE32 FLAT CLASS=CODE\n\n");\r
+#else\r
+ fprintf(fp, "\t\t SECTION .text\n\n");\r
+#endif\r
+\r
+\r
+\r
+/* Reset routine */\r
+\r
+ fprintf(fp, "%s_RESET:\n",CPUtype);\r
+\r
+ fprintf(fp, "\t\t pushad\n\n");\r
+\r
+ fprintf(fp, "; Build Jump Table (not optimised!)\n\n");\r
+\r
+ fprintf(fp, "\t\t lea edi,[%s_OPCODETABLE]\t\t; Jump Table\n", CPUtype);\r
+ fprintf(fp, "\t\t lea esi,[%s_COMPTABLE]\t\t; RLE Compressed Table\n", CPUtype);\r
+\r
+ /* Reference Point in EBP */\r
+\r
+ fprintf(fp, "\t\t mov ebp,[esi]\n");\r
+ fprintf(fp, "\t\t add esi,byte 4\n");\r
+\r
+ fprintf(fp, "RESET0:\n");\r
+ fprintf(fp, "\t\t mov eax,[esi]\n");\r
+ fprintf(fp, "\t\t mov ecx,eax\n");\r
+ fprintf(fp, "\t\t and eax,0xffffff\n");\r
+ fprintf(fp, "\t\t add eax,ebp\n");\r
+ fprintf(fp, "\t\t add esi,byte 4\n");\r
+\r
+ /* if count is zero, then it's a word RLE length */\r
+\r
+ fprintf(fp, "\t\t shr ecx,24\n");\r
+ fprintf(fp, "\t\t jne short RESET1\n");\r
+\r
+#ifdef STALLCHECK\r
+ ClearRegister(ECX);\r
+ fprintf(fp, "\t\t mov cx,[esi]\t\t; Repeats\n");\r
+#else\r
+ fprintf(fp, "\t\t movzx ecx,word [esi]\t\t; Repeats\n");\r
+#endif\r
+\r
+ fprintf(fp, "\t\t add esi,byte 2\n");\r
+ fprintf(fp, "\t\t jecxz RESET2\t\t; Finished!\n");\r
+\r
+ fprintf(fp, "RESET1:\n");\r
+ fprintf(fp, "\t\t mov [edi],eax\n");\r
+ fprintf(fp, "\t\t add edi,byte 4\n");\r
+ fprintf(fp, "\t\t dec ecx\n");\r
+ fprintf(fp, "\t\t jnz short RESET1\n");\r
+ fprintf(fp, "\t\t jmp short RESET0\n");\r
+\r
+ fprintf(fp, "RESET2:\n");\r
+ fprintf(fp, "\t\t popad\n");\r
+ fprintf(fp, "\t\t ret\n\n");\r
+\r
+/* Emulation Entry Point */\r
+\r
+ Align();\r
+\r
+ fprintf(fp, "%s_RUN:\n",CPUtype);\r
+\r
+ fprintf(fp, "\t\t pushad\n");\r
+ fprintf(fp, "\t\t mov esi,[%s]\n",REG_PC);\r
+ fprintf(fp, "\t\t mov edx,[%s]\n",REG_CCR);\r
+ fprintf(fp, "\t\t mov ebp,dword [_OP_ROM]\n");\r
+\r
+ fprintf(fp,"; Check for Interrupt waiting\n\n");\r
+ fprintf(fp,"\t\t test [%s],byte 07H\n",REG_IRQ);\r
+ fprintf(fp,"\t\t jne near interrupt\n\n");\r
+\r
+ fprintf(fp, "IntCont:\n");\r
+\r
+ /* See if was only called to check for Interrupt */\r
+\r
+ fprintf(fp, "\t\t test dword [%s],-1\n",ICOUNT);\r
+ fprintf(fp, "\t\t js short MainExit\n\n");\r
+\r
+ if(CPU==2)\r
+ {\r
+ /* 32 Bit */\r
+ fprintf(fp, "\t\t mov eax,2\n"); /* ASG */\r
+ fprintf(fp, "\t\t xor eax,esi\n"); /* ASG */\r
+#ifdef STALLCHECK\r
+ ClearRegister(ECX);\r
+ fprintf(fp, "\t\t mov cx,[eax+ebp]\n");\r
+#else\r
+ fprintf(fp, "\t\t movzx ecx,word [eax+ebp]\n");\r
+#endif\r
+ }\r
+ else\r
+ {\r
+ /* 16 Bit Fetch */\r
+#ifdef STALLCHECK\r
+ ClearRegister(ECX);\r
+ fprintf(fp, "\t\t mov cx,[esi+ebp]\n");\r
+#else\r
+ fprintf(fp, "\t\t movzx ecx,word [esi+ebp]\n");\r
+#endif\r
+ }\r
+ fprintf(fp, "\t\t jmp [%s_OPCODETABLE+ecx*4]\n", CPUtype);\r
+\r
+ Align();\r
+\r
+ fprintf(fp, "MainExit:\n");\r
+ fprintf(fp, "\t\t mov [%s],esi\t\t; Save PC\n",REG_PC);\r
+ fprintf(fp, "\t\t mov [%s],edx\n",REG_CCR);\r
+ fprintf(fp, "\t\t test byte [%s],20H\n",REG_SRH);\r
+ fprintf(fp, "\t\t mov eax,[%s]\t\t; Get A7\n",REG_A7);\r
+ fprintf(fp, "\t\t jne short ME1\t\t; Mode ?\n");\r
+ fprintf(fp, "\t\t mov [%s],eax\t\t;Save in USP\n",REG_USP);\r
+ fprintf(fp, "\t\t jmp short MC68Kexit\n");\r
+ fprintf(fp, "ME1:\n");\r
+ fprintf(fp, "\t\t mov [%s],eax\n",REG_ISP);\r
+ fprintf(fp, "MC68Kexit:\n");\r
+\r
+ /* If in Debug mode make normal SR register */\r
+\r
+#ifdef MAME_DEBUG\r
+\r
+ ReadCCR('W', ECX);\r
+ fprintf(fp, "\t\t mov [%s],eax\n\n",REG_S);\r
+\r
+#endif\r
+\r
+ fprintf(fp, "\t\t popad\n");\r
+ fprintf(fp, "\t\t ret\n");\r
+\r
+/* Check for Pending Interrupts */\r
+\r
+ Align();\r
+ fprintf(fp, "; Interrupt check\n\n");\r
+\r
+ fprintf(fp, "interrupt:\n");\r
+\r
+ /* check to exclude interrupts */\r
+\r
+ fprintf(fp, "\t\t mov eax,[%s]\n",REG_IRQ);\r
+ fprintf(fp, "\t\t and eax,byte 07H\n");\r
+\r
+ fprintf(fp, "\t\t cmp al,7\t\t ; Always take 7\n");\r
+ fprintf(fp, "\t\t je short procint\n\n");\r
+\r
+ fprintf(fp, "\t\t mov ebx,[%s]\t\t; int mask\n",REG_SRH);\r
+ fprintf(fp, "\t\t and ebx,byte 07H\n");\r
+ fprintf(fp, "\t\t cmp eax,ebx\n");\r
+ fprintf(fp, "\t\t jle near IntCont\n\n");\r
+\r
+ /* Take pending Interrupt */\r
+\r
+ Align();\r
+ fprintf(fp, "procint:\n");\r
+ fprintf(fp, "\t\t and byte [%s],78h\t\t; remove interrupt & stop\n\n",REG_IRQ);\r
+\r
+ /* Get Interrupt Vector from callback */\r
+\r
+ fprintf(fp, "\t\t push eax\t\t; save level\n\n");\r
+\r
+ if (SavedRegs[EBX] == '-')\r
+ {\r
+ fprintf(fp, "\t\t push EBX\n");\r
+ }\r
+ else\r
+ {\r
+ fprintf(fp, "\t\t mov ebx,eax\n");\r
+ }\r
+\r
+ if (SavedRegs[ESI] == '-')\r
+ {\r
+ fprintf(fp, "\t\t mov [%s],ESI\n",REG_PC);\r
+ }\r
+\r
+ if (SavedRegs[EDX] == '-')\r
+ {\r
+ fprintf(fp, "\t\t mov [%s],edx\n",REG_CCR);\r
+ }\r
+\r
+/* ----- Win32 uses FASTCALL (By Kenjo)----- */\r
+\r
+#ifdef FASTCALL\r
+ fprintf(fp, "\t\t mov %s, eax\t\t; irq line #\n",FASTCALL_FIRST_REG);\r
+ fprintf(fp, "\t\t call dword [%s]\t; get the IRQ level\n", REG_IRQ_CALLBACK);\r
+#else\r
+ fprintf(fp, "\t\t push eax\t\t; irq line #\n");\r
+ fprintf(fp, "\t\t call dword [%s]\t; get the IRQ level\n", REG_IRQ_CALLBACK);\r
+ fprintf(fp, "\t\t lea esp,[esp+4]\n");\r
+#endif\r
+\r
+ if (SavedRegs[EDX] == '-')\r
+ {\r
+ fprintf(fp, "\t\t mov edx,[%s]\n",REG_CCR);\r
+ }\r
+\r
+ if (SavedRegs[ESI] == '-')\r
+ {\r
+ fprintf(fp, "\t\t mov esi,[%s]\n",REG_PC);\r
+ }\r
+\r
+ /* Do we want to use normal vector number ? */\r
+\r
+\r
+ fprintf(fp, "\t\t test eax,eax\n");\r
+ fprintf(fp, "\t\t jns short AUTOVECTOR\n");\r
+\r
+ /* Only need EBX restored if default vector to be used */\r
+\r
+ if (SavedRegs[EBX] == '-')\r
+ {\r
+ fprintf(fp, "\t\t pop EBX\n");\r
+ }\r
+\r
+ /* Just get default vector */\r
+\r
+ fprintf(fp, "\t\t mov eax,ebx\n");\r
+\r
+ fprintf(fp, "\t\t add eax,byte 24\t\t; Vector\n\n");\r
+\r
+ fprintf(fp, "AUTOVECTOR:\n\n");\r
+\r
+ Exception(-1,0xFFFF);\r
+\r
+ fprintf(fp, "\t\t pop eax\t\t; set Int mask\n");\r
+ fprintf(fp, "\t\t mov bl,byte [%s]\n",REG_SRH);\r
+ fprintf(fp, "\t\t and bl,0F8h\n");\r
+ fprintf(fp, "\t\t or bl,al\n");\r
+ fprintf(fp, "\t\t mov byte [%s],bl\n\n",REG_SRH);\r
+ fprintf(fp, "\t\t jmp IntCont\n\n");\r
+\r
+/* Exception Routine */\r
+\r
+ Align();\r
+ fprintf(fp, "Exception:\n");\r
+ fprintf(fp, "\t\t push edx\t\t; Save flags\n");\r
+ fprintf(fp, "\t\t and eax,0FFH\t\t; Zero Extend IRQ Vector\n");\r
+\r
+ fprintf(fp, "\t\t push eax\t\t; Save for Later\n");\r
+\r
+ /* Update Cycle Count */\r
+\r
+ fprintf(fp, "\t\t mov al,[exception_cycles+eax]\t\t; Get Cycles\n");\r
+ fprintf(fp, "\t\t sub [%s],eax\t\t; Decrement ICount\n",ICOUNT);\r
+\r
+ ReadCCR('W',ECX);\r
+\r
+ fprintf(fp, "\t\t mov edi,[%s]\t\t; Get A7\n",REG_A7);\r
+\r
+ fprintf(fp, "\t\t test ah,20H\t; Which Mode ?\n");\r
+ fprintf(fp, "\t\t jne short ExSuperMode\t\t; Supervisor\n");\r
+\r
+ fprintf(fp, "\t\t or byte [%s],20H\t; Set Supervisor Mode\n",REG_SRH);\r
+ fprintf(fp, "\t\t mov [%s],edi\t\t; Save in USP\n",REG_USP);\r
+ fprintf(fp, "\t\t mov edi,[%s]\t\t; Get ISP\n",REG_ISP);\r
+\r
+ /* Write SR first (since it's in a register) */\r
+\r
+ fprintf(fp, "ExSuperMode:\n");\r
+ fprintf(fp, "\t\t sub edi,byte 6\n");\r
+ fprintf(fp, "\t\t mov [%s],edi\t\t; Put in A7\n",REG_A7);\r
+ Memory_Write('W',EDI,EAX,"----S-B",2);\r
+\r
+ /* Then write PC */\r
+\r
+ fprintf(fp, "\t\t add edi,byte 2\n");\r
+ Memory_Write('L',EDI,ESI,"------B",0);\r
+\r
+ /* Get new PC */\r
+\r
+ fprintf(fp, "\t\t pop eax\t\t;Level\n");\r
+ fprintf(fp, "\t\t shl eax,2\n");\r
+ fprintf(fp, "\t\t add eax,[%s]\n",REG_VBR); /* 68010+ Vector Base */\r
+\r
+ /* Direct Read */\r
+\r
+ Memory_Read('L',EAX,"------B",0);\r
+\r
+ fprintf(fp, "\t\t mov esi,eax\t\t;Set PC\n");\r
+ fprintf(fp, "\t\t pop edx\t\t; Restore flags\n");\r
+\r
+ /* Sort out any bank changes */\r
+ MemoryBanking(1);\r
+\r
+ fprintf(fp, "\t\t ret\n");\r
+}\r
+\r
+void CodeSegmentEnd(void)\r
+{\r
+#ifdef OS2\r
+ fprintf(fp, "\t\t SECTION maindata USE32 FLAT CLASS=DATA\n\n");\r
+#else\r
+ fprintf(fp, "\t\t SECTION .data\n");\r
+#endif\r
+\r
+ fprintf(fp, "\n\t\t align 16\n");\r
+ fprintf(fp, "%s_ICount\n",CPUtype);\r
+ fprintf(fp, "asm_count\t DD 0\n\n");\r
+\r
+ /* Memory structure for 68000 registers */\r
+ /* Same layout as structure in CPUDEFS.H */\r
+\r
+ fprintf(fp, "\n\n; Register Structure\n\n");\r
+ fprintf(fp, "%s_regs\n",CPUtype);\r
+\r
+ fprintf(fp, "R_D0\t DD 0\t\t\t ; Data Registers\n");\r
+ fprintf(fp, "R_D1\t DD 0\n");\r
+ fprintf(fp, "R_D2\t DD 0\n");\r
+ fprintf(fp, "R_D3\t DD 0\n");\r
+ fprintf(fp, "R_D4\t DD 0\n");\r
+ fprintf(fp, "R_D5\t DD 0\n");\r
+ fprintf(fp, "R_D6\t DD 0\n");\r
+ fprintf(fp, "R_D7\t DD 0\n\n");\r
+\r
+ fprintf(fp, "R_A0\t DD 0\t\t\t ; Address Registers\n");\r
+ fprintf(fp, "R_A1\t DD 0\n");\r
+ fprintf(fp, "R_A2\t DD 0\n");\r
+ fprintf(fp, "R_A3\t DD 0\n");\r
+ fprintf(fp, "R_A4\t DD 0\n");\r
+ fprintf(fp, "R_A5\t DD 0\n");\r
+ fprintf(fp, "R_A6\t DD 0\n");\r
+ fprintf(fp, "R_A7\t DD 0\n\n");\r
+\r
+ fprintf(fp, "R_ISP\t DD 0\t\t\t ; Supervisor Stack\n");\r
+ fprintf(fp, "R_SR_H\t DD 0\t\t\t ; Status Register High TuSuuIII\n");\r
+ fprintf(fp, "R_CCR\t DD 0\t\t\t ; CCR Register in Intel Format\n");\r
+ fprintf(fp, "R_XC\t DD 0\t\t\t ; Extended Carry uuuuuuuX\n");\r
+\r
+ fprintf(fp, "R_PC\t DD 0\t\t\t ; Program Counter\n");\r
+ fprintf(fp, "R_IRQ\t DD 0\t\t\t ; IRQ Request Level\n\n");\r
+ fprintf(fp, "R_SR\t DD 0\t\t\t ; Motorola Format SR\n\n");\r
+\r
+ fprintf(fp, "R_IRQ_CALLBACK\t DD 0\t\t\t ; irq callback (get vector)\n\n");\r
+\r
+ fprintf(fp, "R_PPC\t DD 0\t\t\t ; Previous Program Counter\n");\r
+\r
+ fprintf(fp, "R_RESET_CALLBACK\t DD 0\t\t\t ; Reset Callback\n");\r
+\r
+ fprintf(fp, "R_SFC\t DD 0\t\t\t ; Source Function Call\n");\r
+ fprintf(fp, "R_DFC\t DD 0\t\t\t ; Destination Function Call\n");\r
+ fprintf(fp, "R_USP\t DD 0\t\t\t ; User Stack\n");\r
+ fprintf(fp, "R_VBR\t DD 0\t\t\t ; Vector Base\n");\r
+\r
+ fprintf(fp, "asmbank\t DD 0\n\n");\r
+ fprintf(fp, "CPUversion\t DD 0\n\n");\r
+ fprintf(fp, "FullPC\t DD 0\n\n");\r
+\r
+ /* Extra space for variables mame uses for debugger */\r
+\r
+ fprintf(fp, "\t\t DD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0\n");\r
+ fprintf(fp, "\t\t DD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0\n");\r
+ fprintf(fp, "\t\t DD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0\n");\r
+ fprintf(fp, "\t\t DD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0\n");\r
+ fprintf(fp, "\t\t DD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0\n");\r
+ fprintf(fp, "\t\t DD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0\n");\r
+ fprintf(fp, "\t\t DD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0\n");\r
+ fprintf(fp, "\t\t DD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0\n\n");\r
+\r
+ /* Safe Memory Locations */\r
+\r
+ fprintf(fp, "\t\t ALIGN 16\n");\r
+\r
+ fprintf(fp, "\n\nIntelFlag\t\t\t\t; Intel Flag Lookup Table\n");\r
+ fprintf(fp, "\t\t DD 0000h,0001h,0800h,0801h,0040h,0041h,0840h,0841h\n");\r
+ fprintf(fp, "\t\t DD 0080h,0081h,0880h,0881h,00C0h,00C1h,08C0h,08C1h\n");\r
+ fprintf(fp, "\t\t DD 0100h,0101h,0900h,0901h,0140h,0141h,0940h,0941h\n");\r
+ fprintf(fp, "\t\t DD 0180h,0181h,0980h,0981h,01C0h,01C1h,09C0h,09C1h\n");\r
+\r
+#if 0\r
+ fprintf(fp, "\n\nImmTable\n");\r
+ fprintf(fp, "\t\t DD 8,1,2,3,4,5,6,7\n\n");\r
+#endif\r
+\r
+\r
+\r
+ /* Exception Timing Table */\r
+\r
+ fprintf(fp, "exception_cycles\n");\r
+ fprintf(fp, "\t\t DB 0, 0, 0, 0, 38, 42, 44, 38, 38, 0, 38, 38, 0, 0, 0, 0\n");\r
+ fprintf(fp, "\t\t DB 0, 0, 0, 0, 0, 0, 0, 0, 46, 46, 46, 46, 46, 46, 46, 46\n");\r
+ fprintf(fp, "\t\t DB 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38\n\n");\r
+\r
+ fprintf(fp, "; RLE Compressed Jump Table\n\n");\r
+\r
+ fprintf(fp, "%s_COMPTABLE\n\n", CPUtype);\r
+\r
+ fprintf(fp, "%cinclude '%s'\n\n",'%', comptab);\r
+\r
+ fprintf(fp, "\t\tDW 0,0,0\n\n");\r
+\r
+\r
+/* If Win32, put the table area in .data section (Kenjo) */\r
+\r
+#ifdef WIN32\r
+\r
+ fprintf(fp, "%s_OPCODETABLE\tTIMES 65536 DD 0\n\n", CPUtype);\r
+\r
+#else\r
+\r
+#ifdef OS2\r
+ fprintf(fp, "\t\t SECTION tempdata USE32 FLAT CLASS=BSS\n\n");\r
+#else\r
+ fprintf(fp, "\t\t SECTION .bss\n");\r
+#endif\r
+\r
+ fprintf(fp, "%s_OPCODETABLE\tRESD 65536\n\n", CPUtype);\r
+\r
+#endif\r
+\r
+}\r
+\r
+void EmitCode(void)\r
+{\r
+ CodeSegmentBegin();\r
+\r
+ /* Instructions */\r
+\r
+ moveinstructions(); /* 1000 to 3FFF MOVE.X */\r
+ immediate(); /* 0### XXX.I */\r
+ bitdynamic(); /* 0### dynamic bit operations */\r
+ movep(); /* 0### Move Peripheral */\r
+ bitstatic(); /* 08## static bit operations */\r
+ LoadEffectiveAddress(); /* 4### */\r
+ PushEffectiveAddress(); /* ???? */\r
+ movesr(); /* 4#C# */\r
+ opcode5(); /* 5000 to 5FFF ADDQ,SUBQ,Scc and DBcc */\r
+ branchinstructions(); /* 6000 to 6FFF Bcc,BSR */\r
+ moveq(); /* 7000 to 7FFF MOVEQ */\r
+ abcd_sbcd(); /* 8### Decimal Add/Sub */\r
+ typelogicalmath(); /* Various ranges */\r
+ addx_subx();\r
+ divides();\r
+ swap();\r
+ not(); /* also neg negx clr */\r
+ moveusp();\r
+ chk();\r
+ exg();\r
+ cmpm();\r
+ mul();\r
+ ReturnandRestore();\r
+ rts();\r
+ jmp_jsr();\r
+ nbcd();\r
+ tas();\r
+ trap();\r
+ trapv();\r
+ reset();\r
+ nop();\r
+ stop();\r
+ ext();\r
+ ReturnFromException();\r
+ tst();\r
+ movem_reg_ea();\r
+ movem_ea_reg();\r
+ link();\r
+ unlinkasm();\r
+ asl_asr(); /* E### Shift Commands */\r
+ asl_asr_ea();\r
+ roxl_roxr();\r
+ roxl_roxr_ea();\r
+ lsl_lsr();\r
+ lsl_lsr_ea();\r
+ rol_ror();\r
+ rol_ror_ea();\r
+ LineA(); /* A000 to AFFF Line A */\r
+ LineF(); /* F000 to FFFF Line F */\r
+ illegal_opcode();\r
+\r
+ ReturnandDeallocate(); /* 68010 Commands */\r
+ MoveControlRegister();\r
+ MoveAddressSpace();\r
+\r
+ if(CPU==2) /* 68020 Commands */\r
+ {\r
+ divl();\r
+ mull();\r
+ bfext();\r
+ }\r
+\r
+ CodeSegmentEnd();\r
+}\r
+\r
+int main(int argc, char **argv)\r
+{\r
+ int dwLoop;\r
+\r
+ printf("\nMake68K - V%s - Copyright 1998, Mike Coates (mame@btinternet.com)\n", VERSION);\r
+ printf(" 1999, & Darren Olafson (deo@mail.island.net)\n");\r
+ printf(" 2000\n");\r
+\r
+ if (argc != 4 && argc != 5)\r
+ {\r
+ printf("Usage: %s outfile jumptable-outfile type [ppro]\n", argv[0]);\r
+ exit(1);\r
+ }\r
+\r
+ printf("Building 680%s 2001\n\n",argv[3]);\r
+\r
+ for (dwLoop=0;dwLoop<65536;) OpcodeArray[dwLoop++] = -2;\r
+\r
+ codebuf=malloc(64);\r
+ if (!codebuf)\r
+ {\r
+ printf ("Memory allocation error\n");\r
+ exit(3);\r
+ }\r
+\r
+ /* Emit the code */\r
+ fp = fopen(argv[1], "w");\r
+ if (!fp)\r
+ {\r
+ fprintf(stderr, "Can't open %s for writing\n", argv[1]);\r
+ exit(1);\r
+ }\r
+\r
+ comptab = argv[2];\r
+\r
+\r
+ CPUtype = malloc(64);\r
+#ifdef OS2\r
+ sprintf(CPUtype,"M680%s",argv[3]);\r
+#else\r
+ sprintf(CPUtype,"_M680%s",argv[3]);\r
+#endif\r
+\r
+ if(argv[3][0]=='2') CPU = 2;\r
+ if(argc > 4 && !stricmp(argv[4], "ppro"))\r
+ {\r
+ ppro = 1;\r
+ printf("Generating ppro opcodes\n");\r
+ }\r
+\r
+ EmitCode();\r
+\r
+ fclose(fp);\r
+\r
+ printf("\n%d Unique Opcodes\n",Opcount);\r
+\r
+ /* output Jump table to separate file */\r
+ fp = fopen(argv[2], "w");\r
+ if (!fp)\r
+ {\r
+ fprintf(stderr, "Can't open %s for writing\n", argv[2]);\r
+ exit(1);\r
+ }\r
+\r
+ JumpTable();\r
+\r
+ fclose(fp);\r
+\r
+ exit(0);\r
+}\r
notaz.gp2x.de / picodrive.git / blobdiff