32x and sms savestates. Core-independent z80 state. SS bugfixing/refactoring.

[picodrive.git] / cpu / cz80 / cz80.c

diff --git a/cpu/cz80/cz80.c b/cpu/cz80/cz80.c
index 1f3cae2..61ca5f8 100644 (file)
--- a/cpu/cz80/cz80.c
+++ b/cpu/cz80/cz80.c
@@ -394,8 +394,8 @@ void Cz80_Set_Reg(cz80_struc *CPU, INT32 regnum, UINT32 val)
        case CZ80_R:    zR = val; break;\r
        case CZ80_I:    zI = val; break;\r
        case CZ80_IM:   zIM = val; break;\r
-       case CZ80_IFF1: zIFF1 = val; break;\r
-       case CZ80_IFF2: zIFF2 = val; break;\r
+       case CZ80_IFF1: zIFF1 = val ? (1 << 2) : 0; break;\r
+       case CZ80_IFF2: zIFF2 = val ? (1 << 2) : 0; break;\r
        case CZ80_HALT: CPU->HaltState = val; break;\r
        case CZ80_IRQ:  CPU->IRQState = val; break;\r
        default: break;\r