--- /dev/null
+/******************************************************************************\r
+ *\r
+ * CZ80 (Z80 CPU emulator) version 0.9\r
+ * Compiled with Dev-C++\r
+ * Copyright 2004-2005 Stéphane Dallongeville\r
+ *\r
+ * (Modified by NJ)\r
+ *\r
+ *****************************************************************************/\r
+\r
+#ifndef CZ80_H\r
+#define CZ80_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/******************************/\r
+/* Compiler dependant defines */\r
+/******************************/\r
+\r
+#ifndef UINT8\r
+#define UINT8 unsigned char\r
+#endif\r
+\r
+#ifndef INT8\r
+#define INT8 char\r
+#endif\r
+\r
+#ifndef UINT16\r
+#define UINT16 unsigned short\r
+#endif\r
+\r
+#ifndef INT16\r
+#define INT16 short\r
+#endif\r
+\r
+#ifndef UINT32\r
+#define UINT32 unsigned int\r
+#endif\r
+\r
+#ifndef INT32\r
+#define INT32 int\r
+#endif\r
+\r
+/*************************************/\r
+/* Z80 core Structures & definitions */\r
+/*************************************/\r
+\r
+#define CZ80_FETCH_BITS 4 // [4-12] default = 8\r
+\r
+#define CZ80_FETCH_SFT (16 - CZ80_FETCH_BITS)\r
+#define CZ80_FETCH_BANK (1 << CZ80_FETCH_BITS)\r
+\r
+#define CZ80_LITTLE_ENDIAN 1\r
+#define CZ80_USE_JUMPTABLE 1\r
+#define CZ80_BIG_FLAGS_ARRAY 1\r
+//#ifdef BUILD_CPS1PSP\r
+//#define CZ80_ENCRYPTED_ROM 1\r
+//#else\r
+#define CZ80_ENCRYPTED_ROM 0\r
+//#endif\r
+#define CZ80_EMULATE_R_EXACTLY 0\r
+\r
+#define zR8(A) (*CPU->pzR8[A])\r
+#define zR16(A) (CPU->pzR16[A]->W)\r
+\r
+#define pzAF &(CPU->AF)\r
+#define zAF CPU->AF.W\r
+#define zlAF CPU->AF.B.L\r
+#define zhAF CPU->AF.B.H\r
+#define zA zhAF\r
+#define zF zlAF\r
+\r
+#define pzBC &(CPU->BC)\r
+#define zBC CPU->BC.W\r
+#define zlBC CPU->BC.B.L\r
+#define zhBC CPU->BC.B.H\r
+#define zB zhBC\r
+#define zC zlBC\r
+\r
+#define pzDE &(CPU->DE)\r
+#define zDE CPU->DE.W\r
+#define zlDE CPU->DE.B.L\r
+#define zhDE CPU->DE.B.H\r
+#define zD zhDE\r
+#define zE zlDE\r
+\r
+#define pzHL &(CPU->HL)\r
+#define zHL CPU->HL.W\r
+#define zlHL CPU->HL.B.L\r
+#define zhHL CPU->HL.B.H\r
+#define zH zhHL\r
+#define zL zlHL\r
+\r
+#define zAF2 CPU->AF2.W\r
+#define zlAF2 CPU->AF2.B.L\r
+#define zhAF2 CPU->AF2.B.H\r
+#define zA2 zhAF2\r
+#define zF2 zlAF2\r
+\r
+#define zBC2 CPU->BC2.W\r
+#define zDE2 CPU->DE2.W\r
+#define zHL2 CPU->HL2.W\r
+\r
+#define pzIX &(CPU->IX)\r
+#define zIX CPU->IX.W\r
+#define zlIX CPU->IX.B.L\r
+#define zhIX CPU->IX.B.H\r
+\r
+#define pzIY &(CPU->IY)\r
+#define zIY CPU->IY.W\r
+#define zlIY CPU->IY.B.L\r
+#define zhIY CPU->IY.B.H\r
+\r
+#define pzSP &(CPU->SP)\r
+#define zSP CPU->SP.W\r
+#define zlSP CPU->SP.B.L\r
+#define zhSP CPU->SP.B.H\r
+\r
+#define zRealPC (PC - CPU->BasePC)\r
+#define zPC PC\r
+\r
+#define zI CPU->I\r
+#define zIM CPU->IM\r
+\r
+#define zwR CPU->R.W\r
+#define zR1 CPU->R.B.L\r
+#define zR2 CPU->R.B.H\r
+#define zR zR1\r
+\r
+#define zIFF CPU->IFF.W\r
+#define zIFF1 CPU->IFF.B.L\r
+#define zIFF2 CPU->IFF.B.H\r
+\r
+#define CZ80_SF_SFT 7\r
+#define CZ80_ZF_SFT 6\r
+#define CZ80_YF_SFT 5\r
+#define CZ80_HF_SFT 4\r
+#define CZ80_XF_SFT 3\r
+#define CZ80_PF_SFT 2\r
+#define CZ80_VF_SFT 2\r
+#define CZ80_NF_SFT 1\r
+#define CZ80_CF_SFT 0\r
+\r
+#define CZ80_SF (1 << CZ80_SF_SFT)\r
+#define CZ80_ZF (1 << CZ80_ZF_SFT)\r
+#define CZ80_YF (1 << CZ80_YF_SFT)\r
+#define CZ80_HF (1 << CZ80_HF_SFT)\r
+#define CZ80_XF (1 << CZ80_XF_SFT)\r
+#define CZ80_PF (1 << CZ80_PF_SFT)\r
+#define CZ80_VF (1 << CZ80_VF_SFT)\r
+#define CZ80_NF (1 << CZ80_NF_SFT)\r
+#define CZ80_CF (1 << CZ80_CF_SFT)\r
+\r
+#define CZ80_IFF_SFT CZ80_PF_SFT\r
+#define CZ80_IFF CZ80_PF\r
+\r
+#ifndef IRQ_LINE_STATE\r
+#define IRQ_LINE_STATE\r
+#define CLEAR_LINE 0 /* clear (a fired, held or pulsed) line */\r
+#define ASSERT_LINE 1 /* assert an interrupt immediately */\r
+#define HOLD_LINE 2 /* hold interrupt line until acknowledged */\r
+#define PULSE_LINE 3 /* pulse interrupt line for one instruction */\r
+#define IRQ_LINE_NMI 127 /* IRQ line for NMIs */\r
+#endif\r
+\r
+enum\r
+{\r
+ CZ80_PC = 1,\r
+ CZ80_SP,\r
+ CZ80_AF,\r
+ CZ80_BC,\r
+ CZ80_DE,\r
+ CZ80_HL,\r
+ CZ80_IX,\r
+ CZ80_IY,\r
+ CZ80_AF2,\r
+ CZ80_BC2,\r
+ CZ80_DE2,\r
+ CZ80_HL2,\r
+ CZ80_R,\r
+ CZ80_I,\r
+ CZ80_IM,\r
+ CZ80_IFF1,\r
+ CZ80_IFF2,\r
+ CZ80_HALT,\r
+ CZ80_IRQ\r
+};\r
+\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if CZ80_LITTLE_ENDIAN\r
+ UINT8 L;\r
+ UINT8 H;\r
+#else\r
+ UINT8 H;\r
+ UINT8 L;\r
+#endif\r
+ } B;\r
+ UINT16 W;\r
+} union16;\r
+\r
+typedef struct cz80_t\r
+{\r
+ union\r
+ {\r
+ UINT8 r8[8];\r
+ union16 r16[4];\r
+ struct\r
+ {\r
+ union16 BC;\r
+ union16 DE;\r
+ union16 HL;\r
+ union16 AF;\r
+ };\r
+ };\r
+\r
+ union16 IX;\r
+ union16 IY;\r
+ union16 SP;\r
+ UINT32 PC;\r
+\r
+ union16 BC2;\r
+ union16 DE2;\r
+ union16 HL2;\r
+ union16 AF2;\r
+\r
+ union16 R;\r
+ union16 IFF;\r
+\r
+ UINT8 I;\r
+ UINT8 IM;\r
+ UINT8 HaltState;\r
+ UINT8 dummy;\r
+\r
+ INT32 IRQLine;\r
+ INT32 IRQState;\r
+ INT32 ICount;\r
+ INT32 ExtraCycles;\r
+\r
+ UINT32 BasePC;\r
+ UINT32 Fetch[CZ80_FETCH_BANK];\r
+#if CZ80_ENCRYPTED_ROM\r
+ INT32 OPBase;\r
+ INT32 OPFetch[CZ80_FETCH_BANK];\r
+#endif\r
+\r
+ UINT8 *pzR8[8];\r
+ union16 *pzR16[4];\r
+\r
+ UINT8 (*Read_Byte)(UINT32 address);\r
+ void (*Write_Byte)(UINT32 address, UINT8 data);\r
+\r
+ UINT8 (*IN_Port)(UINT16 port);\r
+ void (*OUT_Port)(UINT16 port, UINT8 value);\r
+\r
+ INT32 (*Interrupt_Callback)(INT32 irqline);\r
+\r
+} cz80_struc;\r
+\r
+\r
+/*************************/\r
+/* Publics Z80 variables */\r
+/*************************/\r
+\r
+extern cz80_struc CZ80;\r
+\r
+/*************************/\r
+/* Publics Z80 functions */\r
+/*************************/\r
+\r
+void Cz80_Init(cz80_struc *CPU);\r
+\r
+void Cz80_Reset(cz80_struc *CPU);\r
+\r
+INT32 Cz80_Exec(cz80_struc *CPU, INT32 cycles);\r
+\r
+void Cz80_Set_IRQ(cz80_struc *CPU, INT32 line, INT32 state);\r
+\r
+UINT32 Cz80_Get_Reg(cz80_struc *CPU, INT32 regnum);\r
+void Cz80_Set_Reg(cz80_struc *CPU, INT32 regnum, UINT32 value);\r
+\r
+void Cz80_Set_Fetch(cz80_struc *CPU, UINT32 low_adr, UINT32 high_adr, UINT32 fetch_adr);\r
+#if CZ80_ENCRYPTED_ROM\r
+void Cz80_Set_Encrypt_Range(cz80_struc *CPU, UINT32 low_adr, UINT32 high_adr, UINT32 decrypted_rom);\r
+#endif\r
+\r
+void Cz80_Set_ReadB(cz80_struc *CPU, UINT8 (*Func)(UINT32 address));\r
+void Cz80_Set_WriteB(cz80_struc *CPU, void (*Func)(UINT32 address, UINT8 data));\r
+\r
+void Cz80_Set_INPort(cz80_struc *CPU, UINT8 (*Func)(UINT16 port));\r
+void Cz80_Set_OUTPort(cz80_struc *CPU, void (*Func)(UINT16 port, UINT8 value));\r
+\r
+void Cz80_Set_IRQ_Callback(cz80_struc *CPU, INT32 (*Func)(INT32 irqline));\r
+\r
+#ifdef __cplusplus\r
+};\r
+#endif\r
+\r
+#endif /* CZ80_H */\r
notaz.gp2x.de / picodrive.git / blobdiff