-// Basic macros to emit ARM instructions and some utils
-
-// (c) Copyright 2008-2009, Grazvydas "notaz" Ignotas
-// Free for non-commercial use.
-
+/*
+ * Basic macros to emit ARM instructions and some utils
+ * Copyright (C) 2008,2009,2010 notaz
+ *
+ * This work is licensed under the terms of MAME license.
+ * See COPYING file in the top-level directory.
+ */
#define CONTEXT_REG 11
// XXX: tcache_ptr type for SVP and SH2 compilers differs..
#define EOP_MSR_REG(rm) EOP_C_MSR_REG(A_COND_AL,rm)
-// XXX: AND, RSB, *C, MVN will break if 1 insn is not enough
+// XXX: AND, RSB, *C, will break if 1 insn is not enough
static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int imm)
{
int ror2;
u32 v;
- if (op == A_OP_MOV) {
+ switch (op) {
+ case A_OP_MOV:
rn = 0;
- if (~imm < 0x100) {
+ if (~imm < 0x10000) {
imm = ~imm;
op = A_OP_MVN;
}
- } else if (imm == 0)
- return;
+ break;
+
+ case A_OP_EOR:
+ case A_OP_SUB:
+ case A_OP_ADD:
+ case A_OP_ORR:
+ case A_OP_BIC:
+ if (s == 0 && imm == 0)
+ return;
+ break;
+ }
- for (v = imm, ror2 = 0; v != 0 || op == A_OP_MOV; v >>= 8, ror2 -= 8/2) {
+ for (v = imm, ror2 = 0; ; ror2 -= 8/2) {
/* shift down to get 'best' rot2 */
for (; v && !(v & 3); v >>= 2)
ror2--;
EOP_C_DOP_IMM(cond, op, s, rn, rd, ror2 & 0x0f, v & 0xff);
+ v >>= 8;
+ if (v == 0)
+ break;
if (op == A_OP_MOV)
op = A_OP_ORR;
+ if (op == A_OP_MVN)
+ op = A_OP_BIC;
rn = rd;
}
}
tcache_ptr += sizeof(u32)
#define JMP_EMIT(cond, ptr) { \
- int val = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \
- EOP_C_B_PTR(ptr, cond, 0, val & 0xffffff); \
+ u32 val_ = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \
+ EOP_C_B_PTR(ptr, cond, 0, val_ & 0xffffff); \
}
#define EMITH_JMP_START(cond) { \
#define emith_add_r_imm(r, imm) \
emith_op_imm(A_COND_AL, 0, A_OP_ADD, r, imm)
+#define emith_adc_r_imm(r, imm) \
+ emith_op_imm(A_COND_AL, 0, A_OP_ADC, r, imm)
+
#define emith_sub_r_imm(r, imm) \
emith_op_imm(A_COND_AL, 0, A_OP_SUB, r, imm)
EOP_MOV_REG_ASR(d,d,32 - (bits)); \
}
-#define host_arg2reg(rd, arg) \
- rd = arg
-
// upto 4 args
#define emith_pass_arg_r(arg, reg) \
EOP_MOV_REG_SIMPLE(arg, reg)
#define emith_jump(target) \
emith_jump_cond(A_COND_AL, target)
+#define emith_jump_patchable(target) \
+ emith_jump(target)
+
#define emith_jump_cond(cond, target) \
emith_xbranch(cond, target, 0)
-#define emith_jump_patchable(cond) \
- emith_jump_cond(cond, 0)
+#define emith_jump_cond_patchable(cond, target) \
+ emith_jump_cond(cond, target)
#define emith_jump_patch(ptr, target) do { \
u32 *ptr_ = ptr; \
- u32 val = (u32 *)(target) - (u32 *)ptr_ - 2; \
- *ptr_ = (*ptr_ & 0xff000000) | (val & 0x00ffffff); \
+ u32 val_ = (u32 *)(target) - ptr_ - 2; \
+ *ptr_ = (*ptr_ & 0xff000000) | (val_ & 0x00ffffff); \
} while (0)
+#define emith_jump_at(ptr, target) { \
+ u32 val_ = (u32 *)(target) - (u32 *)(ptr) - 2; \
+ EOP_C_B_PTR(ptr, A_COND_AL, 0, val_ & 0xffffff); \
+}
+
#define emith_jump_reg_c(cond, r) \
EOP_C_BX(cond, r)
#define emith_ret_to_ctx(offs) \
emith_ctx_write(14, offs)
+#define emith_push_ret() \
+ EOP_STMFD_SP(A_R14M)
+
+#define emith_pop_and_ret() \
+ EOP_LDMFD_SP(A_R15M)
+
+#define host_instructions_updated(base, end) \
+ cache_flush_d_inval_i(base, end)
+
+#define host_arg2reg(rd, arg) \
+ rd = arg
+
/* SH2 drc specific */
#define emith_sh2_drc_entry() \
EOP_STMFD_SP(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R14M)