/*
- * note about silly things like emith_or_r_r_r_lsl:
- * these are here because the compiler was designed
- * for ARM as it's primary target.
+ * note:
+ * temp registers must be eax-edx due to use of SETcc.
+ * note about silly things like emith_eor_r_r_r:
+ * these are here because the compiler was designed
+ * for ARM as it's primary target.
*/
#include <stdarg.h>
#define CONTEXT_REG xBP
+#define IOP_JMP 0xeb
#define IOP_JO 0x70
#define IOP_JNO 0x71
#define IOP_JB 0x72
#define EMIT_MODRM(mod,r,rm) \
EMIT(((mod)<<6) | ((r)<<3) | (rm), u8)
+#define EMIT_SIB(scale,index,base) \
+ EMIT(((scale)<<6) | ((index)<<3) | (base), u8)
+
#define EMIT_OP_MODRM(op,mod,r,rm) { \
EMIT_OP(op); \
EMIT_MODRM(mod, r, rm); \
} \
}
-#define emith_or_r_r_r_lsl(d, s1, s2, lslimm) { \
+// _r_r_shift
+#define emith_or_r_r_lsl(d, s, lslimm) { \
int tmp_ = rcache_get_tmp(); \
- emith_lsl(tmp_, s2, lslimm); \
- emith_or_r_r(tmp_, s1); \
- emith_move_r_r(d, tmp_); \
+ emith_lsl(tmp_, s, lslimm); \
+ emith_or_r_r(d, tmp_); \
rcache_free_tmp(tmp_); \
}
+// d != s
+#define emith_eor_r_r_lsr(d, s, lsrimm) { \
+ emith_push(s); \
+ emith_lsr(s, s, lsrimm); \
+ emith_eor_r_r(d, s); \
+ emith_pop(s); \
+}
+
// _r_imm
#define emith_move_r_imm(r, imm) { \
EMIT_OP(0xb8 + (r)); \
emith_arith_r_imm(4, r, ~(imm))
// fake conditionals (using SJMP instead)
+#define emith_move_r_imm_c(cond, r, imm) { \
+ (void)(cond); \
+ emith_move_r_imm(r, imm); \
+}
+
#define emith_add_r_imm_c(cond, r, imm) { \
(void)(cond); \
emith_add_r_imm(r, imm); \
emith_or_r_imm(r, imm); \
}
+#define emith_eor_r_imm_c(cond, r, imm) { \
+ (void)(cond); \
+ emith_eor_r_imm(r, imm); \
+}
+
#define emith_sub_r_imm_c(cond, r, imm) { \
(void)(cond); \
emith_sub_r_imm(r, imm); \
emith_and_r_imm(d, t); \
}
+#define emith_clear_msb_c(cond, d, s, count) { \
+ (void)(cond); \
+ emith_clear_msb(d, s, count); \
+}
+
#define emith_sext(d, s, bits) { \
emith_lsl(d, s, 32 - (bits)); \
emith_asr(d, d, 32 - (bits)); \
}
-// put bit0 of r0 to carry
-#define emith_set_carry(r0) { \
- emith_tst_r_imm(r0, 1); /* clears C */ \
- EMITH_SJMP_START(DCOND_EQ); \
- EMIT_OP(0xf9); /* STC */ \
- EMITH_SJMP_END(DCOND_EQ); \
+#define emith_setc(r) { \
+ EMIT_OP(0x0f); \
+ EMIT_OP_MODRM(0x92, 3, 0, r); /* SETC r */ \
}
-// put bit0 of r0 to carry (for subtraction)
-#define emith_set_carry_sub emith_set_carry
-
// XXX: stupid mess
#define emith_mul_(op, dlo, dhi, s1, s2) { \
int rmr; \
#define emith_mul(d, s1, s2) \
emith_mul_(4, d, -1, s1, s2)
+// (dlo,dhi) += signed(s1) * signed(s2)
+#define emith_mula_s64(dlo, dhi, s1, s2) { \
+ emith_push(dhi); \
+ emith_push(dlo); \
+ emith_mul_(5, dlo, dhi, s1, s2); \
+ EMIT_OP_MODRM(0x03, 0, dlo, 4); \
+ EMIT_SIB(0, 4, 4); /* add dlo, [esp] */ \
+ EMIT_OP_MODRM(0x13, 1, dhi, 4); \
+ EMIT_SIB(0, 4, 4); \
+ EMIT(4, u8); /* adc dhi, [esp+4] */ \
+ emith_add_r_imm(xSP, 4*2); \
+}
+
// "flag" instructions are the same
#define emith_subf_r_imm emith_sub_r_imm
#define emith_addf_r_r emith_add_r_r
#define emith_subf_r_r emith_sub_r_r
#define emith_adcf_r_r emith_adc_r_r
#define emith_sbcf_r_r emith_sbc_r_r
+#define emith_eorf_r_r emith_eor_r_r
#define emith_negcf_r_r emith_negc_r_r
#define emith_lslf emith_lsl
#define emith_rorcf emith_rorc
// XXX: offs is 8bit only
-#define emith_ctx_read(r, offs) { \
+#define emith_ctx_read(r, offs) do { \
EMIT_OP_MODRM(0x8b, 1, r, xBP); \
EMIT(offs, u8); /* mov tmp, [ebp+#offs] */ \
-}
+} while (0)
+
+#define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
+ int r_ = r, offs_ = offs, cnt_ = cnt; \
+ for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
+ emith_ctx_read(r_, offs_); \
+} while (0)
-#define emith_ctx_write(r, offs) { \
+#define emith_ctx_write(r, offs) do { \
EMIT_OP_MODRM(0x89, 1, r, xBP); \
EMIT(offs, u8); /* mov [ebp+#offs], tmp */ \
-}
+} while (0)
+
+#define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
+ int r_ = r, offs_ = offs, cnt_ = cnt; \
+ for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
+ emith_ctx_write(r_, offs_); \
+} while (0)
#define emith_jump(ptr) { \
u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
EMIT(disp, u32); \
}
-// "simple" or "short" jump
-#define EMITH_SJMP_START(cond) { \
+#define emith_call_cond(cond, ptr) \
+ emith_call(ptr)
+
+#define emith_jump_reg(r) \
+ EMIT_OP_MODRM(0xff, 3, 4, r)
+
+#define EMITH_JMP_START(cond) { \
u8 *cond_ptr; \
JMP8_POS(cond_ptr)
-#define EMITH_SJMP_END(cond) \
+#define EMITH_JMP_END(cond) \
JMP8_EMIT(cond, cond_ptr); \
}
+// "simple" jump (no more then a few insns)
+#define EMITH_SJMP_START EMITH_JMP_START
+#define EMITH_SJMP_END EMITH_JMP_END
+
#define host_arg2reg(rd, arg) \
switch (arg) { \
case 0: rd = xAX; break; \
}
/* SH2 drc specific */
+#define emith_sh2_drc_entry() { \
+ emith_push(xBX); \
+ emith_push(xBP); \
+ emith_push(xSI); \
+ emith_push(xDI); \
+}
+
+#define emith_sh2_drc_exit() { \
+ emith_pop(xDI); \
+ emith_pop(xSI); \
+ emith_pop(xBP); \
+ emith_pop(xBX); \
+ EMIT_OP(0xc3); /* ret */\
+}
+
#define emith_sh2_test_t() { \
int t = rcache_get_reg(SHR_SR, RC_GR_READ); \
- EMIT_OP_MODRM(0xf6, 3, 0, t); \
- EMIT(0x01, u8); /* test <reg>, byte 1 */ \
+ EMIT(0x66, u8); \
+ EMIT_OP_MODRM(0xf7, 3, 0, t); \
+ EMIT(0x01, u16); /* test <reg>, word 1 */ \
}
#define emith_sh2_dtbf_loop() { \
rcache_free_tmp(tmp_); \
}
-#define emith_carry_to_t(srr, is_sub) { \
- int tmp_ = rcache_get_tmp(); \
- EMIT_OP(0x0f); \
- EMIT(0x92, u8); \
- EMIT_MODRM(3, 0, tmp_); /* SETC */ \
- emith_bic_r_imm(srr, 1); \
- EMIT_OP_MODRM(0x08, 3, tmp_, srr); /* OR srrl, tmpl */ \
- rcache_free_tmp(tmp_); \
+#define emith_tpop_carry(sr, is_sub) \
+ emith_lsr(sr, sr, 1)
+
+#define emith_tpush_carry(sr, is_sub) \
+ emith_adc_r_r(sr, sr)
+
+/*
+ * if Q
+ * t = carry(Rn += Rm)
+ * else
+ * t = carry(Rn -= Rm)
+ * T ^= t
+ */
+#define emith_sh2_div1_step(rn, rm, sr) { \
+ u8 *jmp0, *jmp1; \
+ int tmp_ = rcache_get_tmp(); \
+ emith_eor_r_r(tmp_, tmp_); \
+ emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
+ JMP8_POS(jmp0); /* je do_sub */ \
+ emith_add_r_r(rn, rm); \
+ JMP8_POS(jmp1); /* jmp done */ \
+ JMP8_EMIT(IOP_JE, jmp0); /* do_sub: */ \
+ emith_sub_r_r(rn, rm); \
+ JMP8_EMIT(IOP_JMP, jmp1);/* done: */ \
+ emith_setc(tmp_); \
+ EMIT_OP_MODRM(0x31, 3, tmp_, sr); /* T = Q1 ^ Q2 */ \
+ rcache_free_tmp(tmp_); \
}
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