32x: drc: enable and fix static reg alloc, carry flag tweaks

[picodrive.git] / cpu / drc / emit_x86.c

diff --git a/cpu/drc/emit_x86.c b/cpu/drc/emit_x86.c
index 6ef8ede..8f28612 100644 (file)
--- a/cpu/drc/emit_x86.c
+++ b/cpu/drc/emit_x86.c
@@ -1,7 +1,9 @@
 /*
+ * note:
+ *  temp registers must be eax-edx due to use of SETcc.
  * note about silly things like emith_eor_r_r_r:
- * these are here because the compiler was designed
- * for ARM as it's primary target.
+ *  these are here because the compiler was designed
+ *  for ARM as it's primary target.
  */
 #include <stdarg.h>
 
@@ -202,6 +204,11 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
        emith_arith_r_imm(4, r, ~(imm))
 
 // fake conditionals (using SJMP instead)
+#define emith_move_r_imm_c(cond, r, imm) { \
+       (void)(cond); \
+       emith_move_r_imm(r, imm); \
+}
+
 #define emith_add_r_imm_c(cond, r, imm) { \
        (void)(cond); \
        emith_add_r_imm(r, imm); \
@@ -293,21 +300,9 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 
 #define emith_setc(r) { \
        EMIT_OP(0x0f); \
-       EMIT(0x92, u8); \
-       EMIT_MODRM(3, 0, r); /* SETC r */ \
-}
-
-// put bit0 of r0 to carry
-#define emith_set_carry(r0) { \
-       emith_tst_r_imm(r0, 1); /* clears C */ \
-       EMITH_SJMP_START(DCOND_EQ); \
-       EMIT_OP(0xf9); /* STC */ \
-       EMITH_SJMP_END(DCOND_EQ); \
+       EMIT_OP_MODRM(0x92, 3, 0, r); /* SETC r */ \
 }
 
-// put bit0 of r0 to carry (for subtraction)
-#define emith_set_carry_sub emith_set_carry
-
 // XXX: stupid mess
 #define emith_mul_(op, dlo, dhi, s1, s2) { \
        int rmr; \
@@ -365,6 +360,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 #define emith_subf_r_r   emith_sub_r_r
 #define emith_adcf_r_r   emith_adc_r_r
 #define emith_sbcf_r_r   emith_sbc_r_r
+#define emith_eorf_r_r   emith_eor_r_r
 #define emith_negcf_r_r  emith_negc_r_r
 
 #define emith_lslf  emith_lsl
@@ -376,15 +372,27 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 #define emith_rorcf emith_rorc
 
 // XXX: offs is 8bit only
-#define emith_ctx_read(r, offs) { \
+#define emith_ctx_read(r, offs) do { \
        EMIT_OP_MODRM(0x8b, 1, r, xBP); \
        EMIT(offs, u8);         /* mov tmp, [ebp+#offs] */ \
-}
+} while (0)
+
+#define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
+       int r_ = r, offs_ = offs, cnt_ = cnt;     \
+       for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
+               emith_ctx_read(r_, offs_);        \
+} while (0)
 
-#define emith_ctx_write(r, offs) { \
+#define emith_ctx_write(r, offs) do { \
        EMIT_OP_MODRM(0x89, 1, r, xBP); \
        EMIT(offs, u8);         /* mov [ebp+#offs], tmp */ \
-}
+} while (0)
+
+#define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
+       int r_ = r, offs_ = offs, cnt_ = cnt;     \
+       for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
+               emith_ctx_write(r_, offs_);       \
+} while (0)
 
 #define emith_jump(ptr) { \
        u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
@@ -401,15 +409,21 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 #define emith_call_cond(cond, ptr) \
        emith_call(ptr)
 
-// "simple" or "short" jump
-#define EMITH_SJMP_START(cond) { \
+#define emith_jump_reg(r) \
+       EMIT_OP_MODRM(0xff, 3, 4, r)
+
+#define EMITH_JMP_START(cond) { \
        u8 *cond_ptr; \
        JMP8_POS(cond_ptr)
 
-#define EMITH_SJMP_END(cond) \
+#define EMITH_JMP_END(cond) \
        JMP8_EMIT(cond, cond_ptr); \
 }
 
+// "simple" jump (no more then a few insns)
+#define EMITH_SJMP_START EMITH_JMP_START
+#define EMITH_SJMP_END EMITH_JMP_END
+
 #define host_arg2reg(rd, arg) \
        switch (arg) { \
        case 0: rd = xAX; break; \
@@ -430,10 +444,26 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 }
 
 /* SH2 drc specific */
+#define emith_sh2_drc_entry() { \
+       emith_push(xBX);        \
+       emith_push(xBP);        \
+       emith_push(xSI);        \
+       emith_push(xDI);        \
+}
+
+#define emith_sh2_drc_exit() {  \
+       emith_pop(xDI);         \
+       emith_pop(xSI);         \
+       emith_pop(xBP);         \
+       emith_pop(xBX);         \
+       EMIT_OP(0xc3); /* ret */\
+}
+
 #define emith_sh2_test_t() { \
        int t = rcache_get_reg(SHR_SR, RC_GR_READ); \
-       EMIT_OP_MODRM(0xf6, 3, 0, t); \
-       EMIT(0x01, u8); /* test <reg>, byte 1 */ \
+       EMIT(0x66, u8); \
+       EMIT_OP_MODRM(0xf7, 3, 0, t); \
+       EMIT(0x01, u16); /* test <reg>, word 1 */ \
 }
 
 #define emith_sh2_dtbf_loop() { \
@@ -471,13 +501,11 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
        rcache_free_tmp(tmp_); \
 }
 
-#define emith_carry_to_t(srr, is_sub) { \
-       int tmp_ = rcache_get_tmp(); \
-       emith_setc(tmp_); \
-       emith_bic_r_imm(srr, 1); \
-       EMIT_OP_MODRM(0x08, 3, tmp_, srr); /* OR srrl, tmpl */ \
-       rcache_free_tmp(tmp_); \
-}
+#define emith_tpop_carry(sr, is_sub) \
+       emith_lsr(sr, sr, 1)
+
+#define emith_tpush_carry(sr, is_sub) \
+       emith_adc_r_r(sr, sr)
 
 /*
  * if Q
@@ -489,6 +517,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 #define emith_sh2_div1_step(rn, rm, sr) {         \
        u8 *jmp0, *jmp1;                          \
        int tmp_ = rcache_get_tmp();              \
+       emith_eor_r_r(tmp_, tmp_);                \
        emith_tst_r_imm(sr, Q);  /* if (Q ^ M) */ \
        JMP8_POS(jmp0);          /* je do_sub */  \
        emith_add_r_r(rn, rm);                    \
@@ -497,7 +526,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
        emith_sub_r_r(rn, rm);                    \
        JMP8_EMIT(IOP_JMP, jmp1);/* done: */      \
        emith_setc(tmp_);                         \
-       EMIT_OP_MODRM(0x30, 3, tmp_, sr); /* T = Q1 ^ Q2 (byte) */ \
+       EMIT_OP_MODRM(0x31, 3, tmp_, sr); /* T = Q1 ^ Q2 */ \
        rcache_free_tmp(tmp_);                    \
 }