adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
PRE_IO
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(12)
}
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
PRE_IO
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(12)
}
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(20)
}
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(20)
}
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(22)
}
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(24)
}
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(26)
}
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(24)
}
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(28)
}
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(24)
}
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(26)
}
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
PRE_IO
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(20)
}
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(20)
}
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(22)
}
{
execute_exception(M68K_ZERO_DIVIDE_EX);
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81C0;
#endif
RET(10)
}
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81C0;
#endif
RET(50)
}
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81C0;
#endif
RET(80)
}
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end: m68kcontext.io_cycle_counter -= 50;
+end81C0: m68kcontext.io_cycle_counter -= 50;
#endif
RET(108)
}
{
execute_exception(M68K_ZERO_DIVIDE_EX);
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81D0;
#endif
RET(14)
}
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81D0;
#endif
RET(54)
}
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81D0;
#endif
RET(84)
}
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end: m68kcontext.io_cycle_counter -= 50;
+end81D0: m68kcontext.io_cycle_counter -= 50;
#endif
RET(112)
}
{
execute_exception(M68K_ZERO_DIVIDE_EX);
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81D8;
#endif
RET(14)
}
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81D8;
#endif
RET(54)
}
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81D8;
#endif
RET(84)
}
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end: m68kcontext.io_cycle_counter -= 50;
+end81D8: m68kcontext.io_cycle_counter -= 50;
#endif
RET(112)
}
{
execute_exception(M68K_ZERO_DIVIDE_EX);
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81E0;
#endif
RET(16)
}
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81E0;
#endif
RET(56)
}
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81E0;
#endif
RET(86)
}
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end: m68kcontext.io_cycle_counter -= 50;
+end81E0: m68kcontext.io_cycle_counter -= 50;
#endif
RET(114)
}
{
execute_exception(M68K_ZERO_DIVIDE_EX);
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81E8;
#endif
RET(18)
}
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81E8;
#endif
RET(58)
}
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81E8;
#endif
RET(88)
}
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end: m68kcontext.io_cycle_counter -= 50;
+end81E8: m68kcontext.io_cycle_counter -= 50;
#endif
RET(116)
}
{
execute_exception(M68K_ZERO_DIVIDE_EX);
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81F0;
#endif
RET(20)
}
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81F0;
#endif
RET(60)
}
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81F0;
#endif
RET(90)
}
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end: m68kcontext.io_cycle_counter -= 50;
+end81F0: m68kcontext.io_cycle_counter -= 50;
#endif
RET(118)
}
{
execute_exception(M68K_ZERO_DIVIDE_EX);
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81F8;
#endif
RET(18)
}
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81F8;
#endif
RET(58)
}
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81F8;
#endif
RET(88)
}
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end: m68kcontext.io_cycle_counter -= 50;
+end81F8: m68kcontext.io_cycle_counter -= 50;
#endif
RET(116)
}
{
execute_exception(M68K_ZERO_DIVIDE_EX);
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81F9;
#endif
RET(22)
}
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81F9;
#endif
RET(62)
}
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81F9;
#endif
RET(92)
}
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end: m68kcontext.io_cycle_counter -= 50;
+end81F9: m68kcontext.io_cycle_counter -= 50;
#endif
RET(120)
}
{
execute_exception(M68K_ZERO_DIVIDE_EX);
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81FA;
#endif
RET(18)
}
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81FA;
#endif
RET(58)
}
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81FA;
#endif
RET(88)
}
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end: m68kcontext.io_cycle_counter -= 50;
+end81FA: m68kcontext.io_cycle_counter -= 50;
#endif
RET(116)
}
{
execute_exception(M68K_ZERO_DIVIDE_EX);
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81FB;
#endif
RET(20)
}
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81FB;
#endif
RET(60)
}
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81FB;
#endif
RET(90)
}
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end: m68kcontext.io_cycle_counter -= 50;
+end81FB: m68kcontext.io_cycle_counter -= 50;
#endif
RET(118)
}
{
execute_exception(M68K_ZERO_DIVIDE_EX);
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81FC;
#endif
RET(14)
}
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81FC;
#endif
RET(54)
}
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81FC;
#endif
RET(84)
}
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end: m68kcontext.io_cycle_counter -= 50;
+end81FC: m68kcontext.io_cycle_counter -= 50;
#endif
RET(112)
}
{
execute_exception(M68K_ZERO_DIVIDE_EX);
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81DF;
#endif
RET(14)
}
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81DF;
#endif
RET(54)
}
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81DF;
#endif
RET(84)
}
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end: m68kcontext.io_cycle_counter -= 50;
+end81DF: m68kcontext.io_cycle_counter -= 50;
#endif
RET(112)
}
{
execute_exception(M68K_ZERO_DIVIDE_EX);
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81E7;
#endif
RET(16)
}
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81E7;
#endif
RET(56)
}
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end81E7;
#endif
RET(86)
}
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end: m68kcontext.io_cycle_counter -= 50;
+end81E7: m68kcontext.io_cycle_counter -= 50;
#endif
RET(114)
}