--- /dev/null
+/*\r
+must fix:\r
+ callm\r
+ chk\r
+*/\r
+/* ======================================================================== */\r
+/* ========================= LICENSING & COPYRIGHT ======================== */\r
+/* ======================================================================== */\r
+/*\r
+ * MUSASHI\r
+ * Version 3.3\r
+ *\r
+ * A portable Motorola M680x0 processor emulation engine.\r
+ * Copyright 1998-2001 Karl Stenerud. All rights reserved.\r
+ *\r
+ * This code may be freely used for non-commercial purposes as long as this\r
+ * copyright notice remains unaltered in the source code and any binary files\r
+ * containing this code in compiled form.\r
+ *\r
+ * All other lisencing terms must be negotiated with the author\r
+ * (Karl Stenerud).\r
+ *\r
+ * The latest version of this code can be obtained at:\r
+ * http://kstenerud.cjb.net\r
+ */\r
+\r
+/* Special thanks to Bart Trzynadlowski for his insight into the\r
+ * undocumented features of this chip:\r
+ *\r
+ * http://dynarec.com/~bart/files/68knotes.txt\r
+ */\r
+\r
+\r
+/* Input file for m68kmake\r
+ * -----------------------\r
+ *\r
+ * All sections begin with 80 X's in a row followed by an end-of-line\r
+ * sequence.\r
+ * After this, m68kmake will expect to find one of the following section\r
+ * identifiers:\r
+ * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes\r
+ * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes\r
+ * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable\r
+ * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable\r
+ * M68KMAKE_TABLE_BODY - the table itself\r
+ * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation\r
+ * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation\r
+ * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation\r
+ *\r
+ * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and\r
+ * M68KMAKE_TABLE_BODY must be second last in the file.\r
+ *\r
+ * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler\r
+ * primitives themselves. Each opcode handler begins with:\r
+ * M68KMAKE_OP(A, B, C, D)\r
+ *\r
+ * where A is the opcode handler name, B is the size of the operation,\r
+ * C denotes any special processing mode, and D denotes a specific\r
+ * addressing mode.\r
+ * For C and D where nothing is specified, use "."\r
+ *\r
+ * Example:\r
+ * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA\r
+ * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7\r
+ * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing\r
+ *\r
+ * All opcode handler primitives end with a closing curly brace "}" at column 1\r
+ *\r
+ * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,\r
+ * and do not put a closing curly brace at column 1 unless it is\r
+ * marking the end of the handler!\r
+ *\r
+ * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,\r
+ * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple\r
+ * opcode handlers to handle variations in the opcode handler.\r
+ * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.\r
+ * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only\r
+ * be interpreted on instructions where the corresponding table entry\r
+ * specifies multiple effective addressing modes.\r
+ * Example:\r
+ * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4\r
+ *\r
+ * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).\r
+ * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for\r
+ * 68000, 6 cycles for 68010, and 4 cycles for 68020.\r
+ */\r
+\r
+XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
+M68KMAKE_PROTOTYPE_HEADER\r
+\r
+#ifndef M68KOPS__HEADER\r
+#define M68KOPS__HEADER\r
+\r
+/* ======================================================================== */\r
+/* ============================ OPCODE HANDLERS =========================== */\r
+/* ======================================================================== */\r
+\r
+\r
+\r
+XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
+M68KMAKE_PROTOTYPE_FOOTER\r
+\r
+\r
+/* Build the opcode handler table */\r
+void m68ki_build_opcode_table(void);\r
+\r
+extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */\r
+extern unsigned char m68ki_cycles[][0x10000];\r
+\r
+\r
+/* ======================================================================== */\r
+/* ============================== END OF FILE ============================= */\r
+/* ======================================================================== */\r
+\r
+#endif /* M68KOPS__HEADER */\r
+\r
+\r
+\r
+XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
+M68KMAKE_TABLE_HEADER\r
+\r
+/* ======================================================================== */\r
+/* ========================= OPCODE TABLE BUILDER ========================= */\r
+/* ======================================================================== */\r
+\r
+#include "m68kops.h"\r
+\r
+#define NUM_CPU_TYPES 4\r
+\r
+void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */\r
+unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */\r
+\r
+/* This is used to generate the opcode handler jump table */\r
+typedef struct\r
+{\r
+ void (*opcode_handler)(void); /* handler function */\r
+ unsigned int mask; /* mask on opcode */\r
+ unsigned int match; /* what to match after masking */\r
+ unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */\r
+} opcode_handler_struct;\r
+\r
+\r
+/* Opcode handler table */\r
+static opcode_handler_struct m68k_opcode_handler_table[] =\r
+{\r
+/* function mask match 000 010 020 040 */\r
+\r
+\r
+\r
+XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
+M68KMAKE_TABLE_FOOTER\r
+\r
+ {0, 0, 0, {0, 0, 0, 0}}\r
+};\r
+\r
+\r
+/* Build the opcode handler jump table */\r
+void m68ki_build_opcode_table(void)\r
+{\r
+ opcode_handler_struct *ostruct;\r
+ int instr;\r
+ int i;\r
+ int j;\r
+ int k;\r
+\r
+ for(i = 0; i < 0x10000; i++)\r
+ {\r
+ /* default to illegal */\r
+ m68ki_instruction_jump_table[i] = m68k_op_illegal;\r
+ for(k=0;k<NUM_CPU_TYPES;k++)\r
+ m68ki_cycles[k][i] = 0;\r
+ }\r
+\r
+ ostruct = m68k_opcode_handler_table;\r
+ while(ostruct->mask != 0xff00)\r
+ {\r
+ for(i = 0;i < 0x10000;i++)\r
+ {\r
+ if((i & ostruct->mask) == ostruct->match)\r
+ {\r
+ m68ki_instruction_jump_table[i] = ostruct->opcode_handler;\r
+ for(k=0;k<NUM_CPU_TYPES;k++)\r
+ m68ki_cycles[k][i] = ostruct->cycles[k];\r
+ }\r
+ }\r
+ ostruct++;\r
+ }\r
+ while(ostruct->mask == 0xff00)\r
+ {\r
+ for(i = 0;i <= 0xff;i++)\r
+ {\r
+ m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;\r
+ for(k=0;k<NUM_CPU_TYPES;k++)\r
+ m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];\r
+ }\r
+ ostruct++;\r
+ }\r
+ while(ostruct->mask == 0xf1f8)\r
+ {\r
+ for(i = 0;i < 8;i++)\r
+ {\r
+ for(j = 0;j < 8;j++)\r
+ {\r
+ instr = ostruct->match | (i << 9) | j;\r
+ m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;\r
+ for(k=0;k<NUM_CPU_TYPES;k++)\r
+ m68ki_cycles[k][instr] = ostruct->cycles[k];\r
+ }\r
+ }\r
+ ostruct++;\r
+ }\r
+ while(ostruct->mask == 0xfff0)\r
+ {\r
+ for(i = 0;i <= 0x0f;i++)\r
+ {\r
+ m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;\r
+ for(k=0;k<NUM_CPU_TYPES;k++)\r
+ m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];\r
+ }\r
+ ostruct++;\r
+ }\r
+ while(ostruct->mask == 0xf1ff)\r
+ {\r
+ for(i = 0;i <= 0x07;i++)\r
+ {\r
+ m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;\r
+ for(k=0;k<NUM_CPU_TYPES;k++)\r
+ m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];\r
+ }\r
+ ostruct++;\r
+ }\r
+ while(ostruct->mask == 0xfff8)\r
+ {\r
+ for(i = 0;i <= 0x07;i++)\r
+ {\r
+ m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;\r
+ for(k=0;k<NUM_CPU_TYPES;k++)\r
+ m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];\r
+ }\r
+ ostruct++;\r
+ }\r
+ while(ostruct->mask == 0xffff)\r
+ {\r
+ m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;\r
+ for(k=0;k<NUM_CPU_TYPES;k++)\r
+ m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];\r
+ ostruct++;\r
+ }\r
+}\r
+\r
+\r
+/* ======================================================================== */\r
+/* ============================== END OF FILE ============================= */\r
+/* ======================================================================== */\r
+\r
+\r
+\r
+XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
+M68KMAKE_OPCODE_HANDLER_HEADER\r
+\r
+#include "m68kcpu.h"\r
+\r
+/* ======================================================================== */\r
+/* ========================= INSTRUCTION HANDLERS ========================= */\r
+/* ======================================================================== */\r
+\r
+\r
+\r
+XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
+M68KMAKE_OPCODE_HANDLER_FOOTER\r
+\r
+/* ======================================================================== */\r
+/* ============================== END OF FILE ============================= */\r
+/* ======================================================================== */\r
+\r
+\r
+\r
+XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
+M68KMAKE_TABLE_BODY\r
+\r
+The following table is arranged as follows:\r
+\r
+name: Opcode mnemonic\r
+\r
+size: Operation size\r
+\r
+spec proc: Special processing mode:\r
+ .: normal\r
+ s: static operand\r
+ r: register operand\r
+ rr: register to register\r
+ mm: memory to memory\r
+ er: effective address to register\r
+ re: register to effective address\r
+ dd: data register to data register\r
+ da: data register to address register\r
+ aa: address register to address register\r
+ cr: control register to register\r
+ rc: register to control register\r
+ toc: to condition code register\r
+ tos: to status register\r
+ tou: to user stack pointer\r
+ frc: from condition code register\r
+ frs: from status register\r
+ fru: from user stack pointer\r
+ * for move.x, the special processing mode is a specific\r
+ destination effective addressing mode.\r
+\r
+spec ea: Specific effective addressing mode:\r
+ .: normal\r
+ i: immediate\r
+ d: data register\r
+ a: address register\r
+ ai: address register indirect\r
+ pi: address register indirect with postincrement\r
+ pd: address register indirect with predecrement\r
+ di: address register indirect with displacement\r
+ ix: address register indirect with index\r
+ aw: absolute word address\r
+ al: absolute long address\r
+ pcdi: program counter relative with displacement\r
+ pcix: program counter relative with index\r
+ a7: register specified in instruction is A7\r
+ ax7: register field X of instruction is A7\r
+ ay7: register field Y of instruction is A7\r
+ axy7: register fields X and Y of instruction are A7\r
+\r
+bit pattern: Pattern to recognize this opcode. "." means don't care.\r
+\r
+allowed ea: List of allowed addressing modes:\r
+ .: not present\r
+ A: address register indirect\r
+ +: ARI (address register indirect) with postincrement\r
+ -: ARI with predecrement\r
+ D: ARI with displacement\r
+ X: ARI with index\r
+ W: absolute word address\r
+ L: absolute long address\r
+ d: program counter indirect with displacement\r
+ x: program counter indirect with index\r
+ I: immediate\r
+mode: CPU operating mode for each cpu type. U = user or supervisor,\r
+ S = supervisor only, "." = opcode not present.\r
+\r
+cpu cycles: Base number of cycles required to execute this opcode on the\r
+ specified CPU type.\r
+ Use "." if CPU does not have this opcode.\r
+\r
+\r
+\r
+ spec spec allowed ea mode cpu cycles\r
+name size proc ea bit pattern A+-DXWLdxI 0 1 2 4 000 010 020 040 comments\r
+====== ==== ==== ==== ================ ========== = = = = === === === === =============\r
+M68KMAKE_TABLE_START\r
+1010 0 . . 1010............ .......... U U U U 4 4 4 4\r
+1111 0 . . 1111............ .......... U U U U 4 4 4 4\r
+abcd 8 rr . 1100...100000... .......... U U U U 6 6 4 4\r
+abcd 8 mm ax7 1100111100001... .......... U U U U 18 18 16 16\r
+abcd 8 mm ay7 1100...100001111 .......... U U U U 18 18 16 16\r
+abcd 8 mm axy7 1100111100001111 .......... U U U U 18 18 16 16\r
+abcd 8 mm . 1100...100001... .......... U U U U 18 18 16 16\r
+add 8 er d 1101...000000... .......... U U U U 4 4 2 2\r
+add 8 er . 1101...000...... A+-DXWLdxI U U U U 4 4 2 2\r
+add 16 er d 1101...001000... .......... U U U U 4 4 2 2\r
+add 16 er a 1101...001001... .......... U U U U 4 4 2 2\r
+add 16 er . 1101...001...... A+-DXWLdxI U U U U 4 4 2 2\r
+add 32 er d 1101...010000... .......... U U U U 6 6 2 2\r
+add 32 er a 1101...010001... .......... U U U U 6 6 2 2\r
+add 32 er . 1101...010...... A+-DXWLdxI U U U U 6 6 2 2\r
+add 8 re . 1101...100...... A+-DXWL... U U U U 8 8 4 4\r
+add 16 re . 1101...101...... A+-DXWL... U U U U 8 8 4 4\r
+add 32 re . 1101...110...... A+-DXWL... U U U U 12 12 4 4\r
+adda 16 . d 1101...011000... .......... U U U U 8 8 2 2\r
+adda 16 . a 1101...011001... .......... U U U U 8 8 2 2\r
+adda 16 . . 1101...011...... A+-DXWLdxI U U U U 8 8 2 2\r
+adda 32 . d 1101...111000... .......... U U U U 6 6 2 2\r
+adda 32 . a 1101...111001... .......... U U U U 6 6 2 2\r
+adda 32 . . 1101...111...... A+-DXWLdxI U U U U 6 6 2 2\r
+addi 8 . d 0000011000000... .......... U U U U 8 8 2 2\r
+addi 8 . . 0000011000...... A+-DXWL... U U U U 12 12 4 4\r
+addi 16 . d 0000011001000... .......... U U U U 8 8 2 2\r
+addi 16 . . 0000011001...... A+-DXWL... U U U U 12 12 4 4\r
+addi 32 . d 0000011010000... .......... U U U U 16 14 2 2\r
+addi 32 . . 0000011010...... A+-DXWL... U U U U 20 20 4 4\r
+addq 8 . d 0101...000000... .......... U U U U 4 4 2 2\r
+addq 8 . . 0101...000...... A+-DXWL... U U U U 8 8 4 4\r
+addq 16 . d 0101...001000... .......... U U U U 4 4 2 2\r
+addq 16 . a 0101...001001... .......... U U U U 4 4 2 2\r
+addq 16 . . 0101...001...... A+-DXWL... U U U U 8 8 4 4\r
+addq 32 . d 0101...010000... .......... U U U U 8 8 2 2\r
+addq 32 . a 0101...010001... .......... U U U U 8 8 2 2\r
+addq 32 . . 0101...010...... A+-DXWL... U U U U 12 12 4 4\r
+addx 8 rr . 1101...100000... .......... U U U U 4 4 2 2\r
+addx 16 rr . 1101...101000... .......... U U U U 4 4 2 2\r
+addx 32 rr . 1101...110000... .......... U U U U 8 6 2 2\r
+addx 8 mm ax7 1101111100001... .......... U U U U 18 18 12 12\r
+addx 8 mm ay7 1101...100001111 .......... U U U U 18 18 12 12\r
+addx 8 mm axy7 1101111100001111 .......... U U U U 18 18 12 12\r
+addx 8 mm . 1101...100001... .......... U U U U 18 18 12 12\r
+addx 16 mm . 1101...101001... .......... U U U U 18 18 12 12\r
+addx 32 mm . 1101...110001... .......... U U U U 30 30 12 12\r
+and 8 er d 1100...000000... .......... U U U U 4 4 2 2\r
+and 8 er . 1100...000...... A+-DXWLdxI U U U U 4 4 2 2\r
+and 16 er d 1100...001000... .......... U U U U 4 4 2 2\r
+and 16 er . 1100...001...... A+-DXWLdxI U U U U 4 4 2 2\r
+and 32 er d 1100...010000... .......... U U U U 6 6 2 2\r
+and 32 er . 1100...010...... A+-DXWLdxI U U U U 6 6 2 2\r
+and 8 re . 1100...100...... A+-DXWL... U U U U 8 8 4 4\r
+and 16 re . 1100...101...... A+-DXWL... U U U U 8 8 4 4\r
+and 32 re . 1100...110...... A+-DXWL... U U U U 12 12 4 4\r
+andi 16 toc . 0000001000111100 .......... U U U U 20 16 12 12\r
+andi 16 tos . 0000001001111100 .......... S S S S 20 16 12 12\r
+andi 8 . d 0000001000000... .......... U U U U 8 8 2 2\r
+andi 8 . . 0000001000...... A+-DXWL... U U U U 12 12 4 4\r
+andi 16 . d 0000001001000... .......... U U U U 8 8 2 2\r
+andi 16 . . 0000001001...... A+-DXWL... U U U U 12 12 4 4\r
+andi 32 . d 0000001010000... .......... U U U U 14 14 2 2\r
+andi 32 . . 0000001010...... A+-DXWL... U U U U 20 20 4 4\r
+asr 8 s . 1110...000000... .......... U U U U 6 6 6 6\r
+asr 16 s . 1110...001000... .......... U U U U 6 6 6 6\r
+asr 32 s . 1110...010000... .......... U U U U 8 8 6 6\r
+asr 8 r . 1110...000100... .......... U U U U 6 6 6 6\r
+asr 16 r . 1110...001100... .......... U U U U 6 6 6 6\r
+asr 32 r . 1110...010100... .......... U U U U 8 8 6 6\r
+asr 16 . . 1110000011...... A+-DXWL... U U U U 8 8 5 5\r
+asl 8 s . 1110...100000... .......... U U U U 6 6 8 8\r
+asl 16 s . 1110...101000... .......... U U U U 6 6 8 8\r
+asl 32 s . 1110...110000... .......... U U U U 8 8 8 8\r
+asl 8 r . 1110...100100... .......... U U U U 6 6 8 8\r
+asl 16 r . 1110...101100... .......... U U U U 6 6 8 8\r
+asl 32 r . 1110...110100... .......... U U U U 8 8 8 8\r
+asl 16 . . 1110000111...... A+-DXWL... U U U U 8 8 6 6\r
+bcc 8 . . 0110............ .......... U U U U 10 10 6 6\r
+bcc 16 . . 0110....00000000 .......... U U U U 10 10 6 6\r
+bcc 32 . . 0110....11111111 .......... U U U U 10 10 6 6\r
+bchg 8 r . 0000...101...... A+-DXWL... U U U U 8 8 4 4\r
+bchg 32 r d 0000...101000... .......... U U U U 8 8 4 4\r
+bchg 8 s . 0000100001...... A+-DXWL... U U U U 12 12 4 4\r
+bchg 32 s d 0000100001000... .......... U U U U 12 12 4 4\r
+bclr 8 r . 0000...110...... A+-DXWL... U U U U 8 10 4 4\r
+bclr 32 r d 0000...110000... .......... U U U U 10 10 4 4\r
+bclr 8 s . 0000100010...... A+-DXWL... U U U U 12 12 4 4\r
+bclr 32 s d 0000100010000... .......... U U U U 14 14 4 4\r
+bfchg 32 . d 1110101011000... .......... . . U U . . 12 12 timing not quite correct\r
+bfchg 32 . . 1110101011...... A..DXWL... . . U U . . 20 20\r
+bfclr 32 . d 1110110011000... .......... . . U U . . 12 12\r
+bfclr 32 . . 1110110011...... A..DXWL... . . U U . . 20 20\r
+bfexts 32 . d 1110101111000... .......... . . U U . . 8 8\r
+bfexts 32 . . 1110101111...... A..DXWLdx. . . U U . . 15 15\r
+bfextu 32 . d 1110100111000... .......... . . U U . . 8 8\r
+bfextu 32 . . 1110100111...... A..DXWLdx. . . U U . . 15 15\r
+bfffo 32 . d 1110110111000... .......... . . U U . . 18 18\r
+bfffo 32 . . 1110110111...... A..DXWLdx. . . U U . . 28 28\r
+bfins 32 . d 1110111111000... .......... . . U U . . 10 10\r
+bfins 32 . . 1110111111...... A..DXWL... . . U U . . 17 17\r
+bfset 32 . d 1110111011000... .......... . . U U . . 12 12\r
+bfset 32 . . 1110111011...... A..DXWL... . . U U . . 20 20\r
+bftst 32 . d 1110100011000... .......... . . U U . . 6 6\r
+bftst 32 . . 1110100011...... A..DXWLdx. . . U U . . 13 13\r
+bkpt 0 . . 0100100001001... .......... . U U U . 10 10 10\r
+bra 8 . . 01100000........ .......... U U U U 10 10 10 10\r
+bra 16 . . 0110000000000000 .......... U U U U 10 10 10 10\r
+bra 32 . . 0110000011111111 .......... U U U U 10 10 10 10\r
+bset 32 r d 0000...111000... .......... U U U U 8 8 4 4\r
+bset 8 r . 0000...111...... A+-DXWL... U U U U 8 8 4 4\r
+bset 8 s . 0000100011...... A+-DXWL... U U U U 12 12 4 4\r
+bset 32 s d 0000100011000... .......... U U U U 12 12 4 4\r
+bsr 8 . . 01100001........ .......... U U U U 18 18 7 7\r
+bsr 16 . . 0110000100000000 .......... U U U U 18 18 7 7\r
+bsr 32 . . 0110000111111111 .......... U U U U 18 18 7 7\r
+btst 8 r . 0000...100...... A+-DXWLdxI U U U U 4 4 4 4\r
+btst 32 r d 0000...100000... .......... U U U U 6 6 4 4\r
+btst 8 s . 0000100000...... A+-DXWLdx. U U U U 8 8 4 4\r
+btst 32 s d 0000100000000... .......... U U U U 10 10 4 4\r
+callm 32 . . 0000011011...... A..DXWLdx. . . U U . . 60 60 not properly emulated\r
+cas 8 . . 0000101011...... A+-DXWL... . . U U . . 12 12\r
+cas 16 . . 0000110011...... A+-DXWL... . . U U . . 12 12\r
+cas 32 . . 0000111011...... A+-DXWL... . . U U . . 12 12\r
+cas2 16 . . 0000110011111100 .......... . . U U . . 12 12\r
+cas2 32 . . 0000111011111100 .......... . . U U . . 12 12\r
+chk 16 . d 0100...110000... .......... U U U U 10 8 8 8\r
+chk 16 . . 0100...110...... A+-DXWLdxI U U U U 10 8 8 8\r
+chk 32 . d 0100...100000... .......... . . U U . . 8 8\r
+chk 32 . . 0100...100...... A+-DXWLdxI . . U U . . 8 8\r
+chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U . . 23 23\r
+chk2cmp2 8 . pcix 0000000011111011 .......... . . U U . . 23 23\r
+chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U . . 18 18\r
+chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U . . 23 23\r
+chk2cmp2 16 . pcix 0000001011111011 .......... . . U U . . 23 23\r
+chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U . . 18 18\r
+chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U . . 23 23\r
+chk2cmp2 32 . pcix 0000010011111011 .......... . . U U . . 23 23\r
+chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U . . 18 18\r
+clr 8 . d 0100001000000... .......... U U U U 4 4 2 2\r
+clr 8 . . 0100001000...... A+-DXWL... U U U U 6 4 4 4 notaz hack: changed 000 cycles 8 -> 6 like in starscream for Fatal Rewind\r
+clr 16 . d 0100001001000... .......... U U U U 4 4 2 2\r
+clr 16 . . 0100001001...... A+-DXWL... U U U U 6 4 4 4 ditto\r
+clr 32 . d 0100001010000... .......... U U U U 6 6 2 2\r
+clr 32 . . 0100001010...... A+-DXWL... U U U U 12 6 4 4\r
+cmp 8 . d 1011...000000... .......... U U U U 4 4 2 2\r
+cmp 8 . . 1011...000...... A+-DXWLdxI U U U U 4 4 2 2\r
+cmp 16 . d 1011...001000... .......... U U U U 4 4 2 2\r
+cmp 16 . a 1011...001001... .......... U U U U 4 4 2 2\r
+cmp 16 . . 1011...001...... A+-DXWLdxI U U U U 4 4 2 2\r
+cmp 32 . d 1011...010000... .......... U U U U 6 6 2 2\r
+cmp 32 . a 1011...010001... .......... U U U U 6 6 2 2\r
+cmp 32 . . 1011...010...... A+-DXWLdxI U U U U 6 6 2 2\r
+cmpa 16 . d 1011...011000... .......... U U U U 6 6 4 4\r
+cmpa 16 . a 1011...011001... .......... U U U U 6 6 4 4\r
+cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U 6 6 4 4\r
+cmpa 32 . d 1011...111000... .......... U U U U 6 6 4 4\r
+cmpa 32 . a 1011...111001... .......... U U U U 6 6 4 4\r
+cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U 6 6 4 4\r
+cmpi 8 . d 0000110000000... .......... U U U U 8 8 2 2\r
+cmpi 8 . . 0000110000...... A+-DXWL... U U U U 8 8 2 2\r
+cmpi 8 . pcdi 0000110000111010 .......... . . U U . . 7 7\r
+cmpi 8 . pcix 0000110000111011 .......... . . U U . . 9 9\r
+cmpi 16 . d 0000110001000... .......... U U U U 8 8 2 2\r
+cmpi 16 . . 0000110001...... A+-DXWL... U U U U 8 8 2 2\r
+cmpi 16 . pcdi 0000110001111010 .......... . . U U . . 7 7\r
+cmpi 16 . pcix 0000110001111011 .......... . . U U . . 9 9\r
+cmpi 32 . d 0000110010000... .......... U U U U 14 12 2 2\r
+cmpi 32 . . 0000110010...... A+-DXWL... U U U U 12 12 2 2\r
+cmpi 32 . pcdi 0000110010111010 .......... . . U U . . 7 7\r
+cmpi 32 . pcix 0000110010111011 .......... . . U U . . 9 9\r
+cmpm 8 . ax7 1011111100001... .......... U U U U 12 12 9 9\r
+cmpm 8 . ay7 1011...100001111 .......... U U U U 12 12 9 9\r
+cmpm 8 . axy7 1011111100001111 .......... U U U U 12 12 9 9\r
+cmpm 8 . . 1011...100001... .......... U U U U 12 12 9 9\r
+cmpm 16 . . 1011...101001... .......... U U U U 12 12 9 9\r
+cmpm 32 . . 1011...110001... .......... U U U U 20 20 9 9\r
+cpbcc 32 . . 1111...01....... .......... . . U . . . 4 . unemulated\r
+cpdbcc 32 . . 1111...001001... .......... . . U . . . 4 . unemulated\r
+cpgen 32 . . 1111...000...... .......... . . U . . . 4 . unemulated\r
+cpscc 32 . . 1111...001...... .......... . . U . . . 4 . unemulated\r
+cptrapcc 32 . . 1111...001111... .......... . . U . . . 4 . unemulated\r
+dbt 16 . . 0101000011001... .......... U U U U 12 12 6 6\r
+dbf 16 . . 0101000111001... .......... U U U U 12 12 6 6\r
+dbcc 16 . . 0101....11001... .......... U U U U 12 12 6 6\r
+divs 16 . d 1000...111000... .......... U U U U 158 122 56 56\r
+divs 16 . . 1000...111...... A+-DXWLdxI U U U U 158 122 56 56\r
+divu 16 . d 1000...011000... .......... U U U U 140 108 44 44\r
+divu 16 . . 1000...011...... A+-DXWLdxI U U U U 140 108 44 44\r
+divl 32 . d 0100110001000... .......... . . U U . . 84 84\r
+divl 32 . . 0100110001...... A+-DXWLdxI . . U U . . 84 84\r
+eor 8 . d 1011...100000... .......... U U U U 4 4 2 2\r
+eor 8 . . 1011...100...... A+-DXWL... U U U U 8 8 4 4\r
+eor 16 . d 1011...101000... .......... U U U U 4 4 2 2\r
+eor 16 . . 1011...101...... A+-DXWL... U U U U 8 8 4 4\r
+eor 32 . d 1011...110000... .......... U U U U 8 6 2 2\r
+eor 32 . . 1011...110...... A+-DXWL... U U U U 12 12 4 4\r
+eori 16 toc . 0000101000111100 .......... U U U U 20 16 12 12\r
+eori 16 tos . 0000101001111100 .......... S S S S 20 16 12 12\r
+eori 8 . d 0000101000000... .......... U U U U 8 8 2 2\r
+eori 8 . . 0000101000...... A+-DXWL... U U U U 12 12 4 4\r
+eori 16 . d 0000101001000... .......... U U U U 8 8 2 2\r
+eori 16 . . 0000101001...... A+-DXWL... U U U U 12 12 4 4\r
+eori 32 . d 0000101010000... .......... U U U U 16 14 2 2\r
+eori 32 . . 0000101010...... A+-DXWL... U U U U 20 20 4 4\r
+exg 32 dd . 1100...101000... .......... U U U U 6 6 2 2\r
+exg 32 aa . 1100...101001... .......... U U U U 6 6 2 2\r
+exg 32 da . 1100...110001... .......... U U U U 6 6 2 2\r
+ext 16 . . 0100100010000... .......... U U U U 4 4 4 4\r
+ext 32 . . 0100100011000... .......... U U U U 4 4 4 4\r
+extb 32 . . 0100100111000... .......... . . U U . . 4 4\r
+illegal 0 . . 0100101011111100 .......... U U U U 4 4 4 4\r
+jmp 32 . . 0100111011...... A..DXWLdx. U U U U 4 4 0 0\r
+jsr 32 . . 0100111010...... A..DXWLdx. U U U U 12 12 0 0\r
+lea 32 . . 0100...111...... A..DXWLdx. U U U U 0 0 2 2\r
+link 16 . a7 0100111001010111 .......... U U U U 16 16 5 5\r
+link 16 . . 0100111001010... .......... U U U U 16 16 5 5\r
+link 32 . a7 0100100000001111 .......... . . U U . . 6 6\r
+link 32 . . 0100100000001... .......... . . U U . . 6 6\r
+lsr 8 s . 1110...000001... .......... U U U U 6 6 4 4\r
+lsr 16 s . 1110...001001... .......... U U U U 6 6 4 4\r
+lsr 32 s . 1110...010001... .......... U U U U 8 8 4 4\r
+lsr 8 r . 1110...000101... .......... U U U U 6 6 6 6\r
+lsr 16 r . 1110...001101... .......... U U U U 6 6 6 6\r
+lsr 32 r . 1110...010101... .......... U U U U 8 8 6 6\r
+lsr 16 . . 1110001011...... A+-DXWL... U U U U 8 8 5 5\r
+lsl 8 s . 1110...100001... .......... U U U U 6 6 4 4\r
+lsl 16 s . 1110...101001... .......... U U U U 6 6 4 4\r
+lsl 32 s . 1110...110001... .......... U U U U 8 8 4 4\r
+lsl 8 r . 1110...100101... .......... U U U U 6 6 6 6\r
+lsl 16 r . 1110...101101... .......... U U U U 6 6 6 6\r
+lsl 32 r . 1110...110101... .......... U U U U 8 8 6 6\r
+lsl 16 . . 1110001111...... A+-DXWL... U U U U 8 8 5 5\r
+move 8 d d 0001...000000... .......... U U U U 4 4 2 2\r
+move 8 d . 0001...000...... A+-DXWLdxI U U U U 4 4 2 2\r
+move 8 ai d 0001...010000... .......... U U U U 8 8 4 4\r
+move 8 ai . 0001...010...... A+-DXWLdxI U U U U 8 8 4 4\r
+move 8 pi d 0001...011000... .......... U U U U 8 8 4 4\r
+move 8 pi . 0001...011...... A+-DXWLdxI U U U U 8 8 4 4\r
+move 8 pi7 d 0001111011000... .......... U U U U 8 8 4 4\r
+move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U 8 8 4 4\r
+move 8 pd d 0001...100000... .......... U U U U 8 8 5 5\r
+move 8 pd . 0001...100...... A+-DXWLdxI U U U U 8 8 5 5\r
+move 8 pd7 d 0001111100000... .......... U U U U 8 8 5 5\r
+move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U 8 8 5 5\r
+move 8 di d 0001...101000... .......... U U U U 12 12 5 5\r
+move 8 di . 0001...101...... A+-DXWLdxI U U U U 12 12 5 5\r
+move 8 ix d 0001...110000... .......... U U U U 14 14 7 7\r
+move 8 ix . 0001...110...... A+-DXWLdxI U U U U 14 14 7 7\r
+move 8 aw d 0001000111000... .......... U U U U 12 12 4 4\r
+move 8 aw . 0001000111...... A+-DXWLdxI U U U U 12 12 4 4\r
+move 8 al d 0001001111000... .......... U U U U 16 16 6 6\r
+move 8 al . 0001001111...... A+-DXWLdxI U U U U 16 16 6 6\r
+move 16 d d 0011...000000... .......... U U U U 4 4 2 2\r
+move 16 d a 0011...000001... .......... U U U U 4 4 2 2\r
+move 16 d . 0011...000...... A+-DXWLdxI U U U U 4 4 2 2\r
+move 16 ai d 0011...010000... .......... U U U U 8 8 4 4\r
+move 16 ai a 0011...010001... .......... U U U U 8 8 4 4\r
+move 16 ai . 0011...010...... A+-DXWLdxI U U U U 8 8 4 4\r
+move 16 pi d 0011...011000... .......... U U U U 8 8 4 4\r
+move 16 pi a 0011...011001... .......... U U U U 8 8 4 4\r
+move 16 pi . 0011...011...... A+-DXWLdxI U U U U 8 8 4 4\r
+move 16 pd d 0011...100000... .......... U U U U 8 8 5 5\r
+move 16 pd a 0011...100001... .......... U U U U 8 8 5 5\r
+move 16 pd . 0011...100...... A+-DXWLdxI U U U U 8 8 5 5\r
+move 16 di d 0011...101000... .......... U U U U 12 12 5 5\r
+move 16 di a 0011...101001... .......... U U U U 12 12 5 5\r
+move 16 di . 0011...101...... A+-DXWLdxI U U U U 12 12 5 5\r
+move 16 ix d 0011...110000... .......... U U U U 14 14 7 7\r
+move 16 ix a 0011...110001... .......... U U U U 14 14 7 7\r
+move 16 ix . 0011...110...... A+-DXWLdxI U U U U 14 14 7 7\r
+move 16 aw d 0011000111000... .......... U U U U 12 12 4 4\r
+move 16 aw a 0011000111001... .......... U U U U 12 12 4 4\r
+move 16 aw . 0011000111...... A+-DXWLdxI U U U U 12 12 4 4\r
+move 16 al d 0011001111000... .......... U U U U 16 16 6 6\r
+move 16 al a 0011001111001... .......... U U U U 16 16 6 6\r
+move 16 al . 0011001111...... A+-DXWLdxI U U U U 16 16 6 6\r
+move 32 d d 0010...000000... .......... U U U U 4 4 2 2\r
+move 32 d a 0010...000001... .......... U U U U 4 4 2 2\r
+move 32 d . 0010...000...... A+-DXWLdxI U U U U 4 4 2 2\r
+move 32 ai d 0010...010000... .......... U U U U 12 12 4 4\r
+move 32 ai a 0010...010001... .......... U U U U 12 12 4 4\r
+move 32 ai . 0010...010...... A+-DXWLdxI U U U U 12 12 4 4\r
+move 32 pi d 0010...011000... .......... U U U U 12 12 4 4\r
+move 32 pi a 0010...011001... .......... U U U U 12 12 4 4\r
+move 32 pi . 0010...011...... A+-DXWLdxI U U U U 12 12 4 4\r
+move 32 pd d 0010...100000... .......... U U U U 12 14 5 5\r
+move 32 pd a 0010...100001... .......... U U U U 12 14 5 5\r
+move 32 pd . 0010...100...... A+-DXWLdxI U U U U 12 14 5 5\r
+move 32 di d 0010...101000... .......... U U U U 16 16 5 5\r
+move 32 di a 0010...101001... .......... U U U U 16 16 5 5\r
+move 32 di . 0010...101...... A+-DXWLdxI U U U U 16 16 5 5\r
+move 32 ix d 0010...110000... .......... U U U U 18 18 7 7\r
+move 32 ix a 0010...110001... .......... U U U U 18 18 7 7\r
+move 32 ix . 0010...110...... A+-DXWLdxI U U U U 18 18 7 7\r
+move 32 aw d 0010000111000... .......... U U U U 16 16 4 4\r
+move 32 aw a 0010000111001... .......... U U U U 16 16 4 4\r
+move 32 aw . 0010000111...... A+-DXWLdxI U U U U 16 16 4 4\r
+move 32 al d 0010001111000... .......... U U U U 20 20 6 6\r
+move 32 al a 0010001111001... .......... U U U U 20 20 6 6\r
+move 32 al . 0010001111...... A+-DXWLdxI U U U U 20 20 6 6\r
+movea 16 . d 0011...001000... .......... U U U U 4 4 2 2\r
+movea 16 . a 0011...001001... .......... U U U U 4 4 2 2\r
+movea 16 . . 0011...001...... A+-DXWLdxI U U U U 4 4 2 2\r
+movea 32 . d 0010...001000... .......... U U U U 4 4 2 2\r
+movea 32 . a 0010...001001... .......... U U U U 4 4 2 2\r
+movea 32 . . 0010...001...... A+-DXWLdxI U U U U 4 4 2 2\r
+move 16 frc d 0100001011000... .......... . U U U . 4 4 4\r
+move 16 frc . 0100001011...... A+-DXWL... . U U U . 8 4 4\r
+move 16 toc d 0100010011000... .......... U U U U 12 12 4 4\r
+move 16 toc . 0100010011...... A+-DXWLdxI U U U U 12 12 4 4\r
+move 16 frs d 0100000011000... .......... U S S S 6 4 8 8 U only for 000\r
+move 16 frs . 0100000011...... A+-DXWL... U S S S 8 8 8 8 U only for 000\r
+move 16 tos d 0100011011000... .......... S S S S 12 12 8 8\r
+move 16 tos . 0100011011...... A+-DXWLdxI S S S S 12 12 8 8\r
+move 32 fru . 0100111001101... .......... S S S S 4 6 2 2\r
+move 32 tou . 0100111001100... .......... S S S S 4 6 2 2\r
+movec 32 cr . 0100111001111010 .......... . S S S . 12 6 6\r
+movec 32 rc . 0100111001111011 .......... . S S S . 10 12 12\r
+movem 16 re pd 0100100010100... .......... U U U U 8 8 4 4\r
+movem 16 re . 0100100010...... A..DXWL... U U U U 8 8 4 4\r
+movem 32 re pd 0100100011100... .......... U U U U 8 8 4 4\r
+movem 32 re . 0100100011...... A..DXWL... U U U U 8 8 4 4\r
+movem 16 er pi 0100110010011... .......... U U U U 12 12 8 8\r
+movem 16 er pcdi 0100110010111010 .......... U U U U 16 16 9 9\r
+movem 16 er pcix 0100110010111011 .......... U U U U 18 18 11 11\r
+movem 16 er . 0100110010...... A..DXWL... U U U U 12 12 8 8\r
+movem 32 er pi 0100110011011... .......... U U U U 12 12 8 8\r
+movem 32 er pcdi 0100110011111010 .......... U U U U 16 16 9 9\r
+movem 32 er pcix 0100110011111011 .......... U U U U 18 18 11 11\r
+movem 32 er . 0100110011...... A..DXWL... U U U U 12 12 8 8\r
+movep 16 er . 0000...100001... .......... U U U U 16 16 12 12\r
+movep 32 er . 0000...101001... .......... U U U U 24 24 18 18\r
+movep 16 re . 0000...110001... .......... U U U U 16 16 11 11\r
+movep 32 re . 0000...111001... .......... U U U U 24 24 17 17\r
+moveq 32 . . 0111...0........ .......... U U U U 4 4 2 2\r
+moves 8 . . 0000111000...... A+-DXWL... . S S S . 14 5 5\r
+moves 16 . . 0000111001...... A+-DXWL... . S S S . 14 5 5\r
+moves 32 . . 0000111010...... A+-DXWL... . S S S . 16 5 5\r
+move16 32 . . 1111011000100... .......... . . . U . . . 4 TODO: correct timing\r
+muls 16 . d 1100...111000... .......... U U U U 54 32 27 27\r
+muls 16 . . 1100...111...... A+-DXWLdxI U U U U 54 32 27 27\r
+mulu 16 . d 1100...011000... .......... U U U U 54 30 27 27\r
+mulu 16 . . 1100...011...... A+-DXWLdxI U U U U 54 30 27 27\r
+mull 32 . d 0100110000000... .......... . . U U . . 43 43\r
+mull 32 . . 0100110000...... A+-DXWLdxI . . U U . . 43 43\r
+nbcd 8 . d 0100100000000... .......... U U U U 6 6 6 6\r
+nbcd 8 . . 0100100000...... A+-DXWL... U U U U 8 8 6 6\r
+neg 8 . d 0100010000000... .......... U U U U 4 4 2 2\r
+neg 8 . . 0100010000...... A+-DXWL... U U U U 8 8 4 4\r
+neg 16 . d 0100010001000... .......... U U U U 4 4 2 2\r
+neg 16 . . 0100010001...... A+-DXWL... U U U U 8 8 4 4\r
+neg 32 . d 0100010010000... .......... U U U U 6 6 2 2\r
+neg 32 . . 0100010010...... A+-DXWL... U U U U 12 12 4 4\r
+negx 8 . d 0100000000000... .......... U U U U 4 4 2 2\r
+negx 8 . . 0100000000...... A+-DXWL... U U U U 8 8 4 4\r
+negx 16 . d 0100000001000... .......... U U U U 4 4 2 2\r
+negx 16 . . 0100000001...... A+-DXWL... U U U U 8 8 4 4\r
+negx 32 . d 0100000010000... .......... U U U U 6 6 2 2\r
+negx 32 . . 0100000010...... A+-DXWL... U U U U 12 12 4 4\r
+nop 0 . . 0100111001110001 .......... U U U U 4 4 2 2\r
+not 8 . d 0100011000000... .......... U U U U 4 4 2 2\r
+not 8 . . 0100011000...... A+-DXWL... U U U U 8 8 4 4\r
+not 16 . d 0100011001000... .......... U U U U 4 4 2 2\r
+not 16 . . 0100011001...... A+-DXWL... U U U U 8 8 4 4\r
+not 32 . d 0100011010000... .......... U U U U 6 6 2 2\r
+not 32 . . 0100011010...... A+-DXWL... U U U U 12 12 4 4\r
+or 8 er d 1000...000000... .......... U U U U 4 4 2 2\r
+or 8 er . 1000...000...... A+-DXWLdxI U U U U 4 4 2 2\r
+or 16 er d 1000...001000... .......... U U U U 4 4 2 2\r
+or 16 er . 1000...001...... A+-DXWLdxI U U U U 4 4 2 2\r
+or 32 er d 1000...010000... .......... U U U U 6 6 2 2\r
+or 32 er . 1000...010...... A+-DXWLdxI U U U U 6 6 2 2\r
+or 8 re . 1000...100...... A+-DXWL... U U U U 8 8 4 4\r
+or 16 re . 1000...101...... A+-DXWL... U U U U 8 8 4 4\r
+or 32 re . 1000...110...... A+-DXWL... U U U U 12 12 4 4\r
+ori 16 toc . 0000000000111100 .......... U U U U 20 16 12 12\r
+ori 16 tos . 0000000001111100 .......... S S S S 20 16 12 12\r
+ori 8 . d 0000000000000... .......... U U U U 8 8 2 2\r
+ori 8 . . 0000000000...... A+-DXWL... U U U U 12 12 4 4\r
+ori 16 . d 0000000001000... .......... U U U U 8 8 2 2\r
+ori 16 . . 0000000001...... A+-DXWL... U U U U 12 12 4 4\r
+ori 32 . d 0000000010000... .......... U U U U 16 14 2 2\r
+ori 32 . . 0000000010...... A+-DXWL... U U U U 20 20 4 4\r
+pack 16 rr . 1000...101000... .......... . . U U . . 6 6\r
+pack 16 mm ax7 1000111101001... .......... . . U U . . 13 13\r
+pack 16 mm ay7 1000...101001111 .......... . . U U . . 13 13\r
+pack 16 mm axy7 1000111101001111 .......... . . U U . . 13 13\r
+pack 16 mm . 1000...101001... .......... . . U U . . 13 13\r
+pea 32 . . 0100100001...... A..DXWLdx. U U U U 6 6 5 5\r
+pflush 32 . . 1111010100011000 .......... . . . S . . . 4 TODO: correct timing\r
+reset 0 . . 0100111001110000 .......... S S S S 0 0 0 0\r
+ror 8 s . 1110...000011... .......... U U U U 6 6 8 8\r
+ror 16 s . 1110...001011... .......... U U U U 6 6 8 8\r
+ror 32 s . 1110...010011... .......... U U U U 8 8 8 8\r
+ror 8 r . 1110...000111... .......... U U U U 6 6 8 8\r
+ror 16 r . 1110...001111... .......... U U U U 6 6 8 8\r
+ror 32 r . 1110...010111... .......... U U U U 8 8 8 8\r
+ror 16 . . 1110011011...... A+-DXWL... U U U U 8 8 7 7\r
+rol 8 s . 1110...100011... .......... U U U U 6 6 8 8\r
+rol 16 s . 1110...101011... .......... U U U U 6 6 8 8\r
+rol 32 s . 1110...110011... .......... U U U U 8 8 8 8\r
+rol 8 r . 1110...100111... .......... U U U U 6 6 8 8\r
+rol 16 r . 1110...101111... .......... U U U U 6 6 8 8\r
+rol 32 r . 1110...110111... .......... U U U U 8 8 8 8\r
+rol 16 . . 1110011111...... A+-DXWL... U U U U 8 8 7 7\r
+roxr 8 s . 1110...000010... .......... U U U U 6 6 12 12\r
+roxr 16 s . 1110...001010... .......... U U U U 6 6 12 12\r
+roxr 32 s . 1110...010010... .......... U U U U 8 8 12 12\r
+roxr 8 r . 1110...000110... .......... U U U U 6 6 12 12\r
+roxr 16 r . 1110...001110... .......... U U U U 6 6 12 12\r
+roxr 32 r . 1110...010110... .......... U U U U 8 8 12 12\r
+roxr 16 . . 1110010011...... A+-DXWL... U U U U 8 8 5 5\r
+roxl 8 s . 1110...100010... .......... U U U U 6 6 12 12\r
+roxl 16 s . 1110...101010... .......... U U U U 6 6 12 12\r
+roxl 32 s . 1110...110010... .......... U U U U 8 8 12 12\r
+roxl 8 r . 1110...100110... .......... U U U U 6 6 12 12\r
+roxl 16 r . 1110...101110... .......... U U U U 6 6 12 12\r
+roxl 32 r . 1110...110110... .......... U U U U 8 8 12 12\r
+roxl 16 . . 1110010111...... A+-DXWL... U U U U 8 8 5 5\r
+rtd 32 . . 0100111001110100 .......... . U U U . 16 10 10\r
+rte 32 . . 0100111001110011 .......... S S S S 20 24 20 20 bus fault not emulated\r
+rtm 32 . . 000001101100.... .......... . . U U . . 19 19 not properly emulated\r
+rtr 32 . . 0100111001110111 .......... U U U U 20 20 14 14\r
+rts 32 . . 0100111001110101 .......... U U U U 16 16 10 10\r
+sbcd 8 rr . 1000...100000... .......... U U U U 6 6 4 4\r
+sbcd 8 mm ax7 1000111100001... .......... U U U U 18 18 16 16\r
+sbcd 8 mm ay7 1000...100001111 .......... U U U U 18 18 16 16\r
+sbcd 8 mm axy7 1000111100001111 .......... U U U U 18 18 16 16\r
+sbcd 8 mm . 1000...100001... .......... U U U U 18 18 16 16\r
+st 8 . d 0101000011000... .......... U U U U 6 4 4 4\r
+st 8 . . 0101000011...... A+-DXWL... U U U U 8 8 6 6\r
+sf 8 . d 0101000111000... .......... U U U U 4 4 4 4\r
+sf 8 . . 0101000111...... A+-DXWL... U U U U 8 8 6 6\r
+scc 8 . d 0101....11000... .......... U U U U 4 4 4 4\r
+scc 8 . . 0101....11...... A+-DXWL... U U U U 8 8 6 6\r
+stop 0 . . 0100111001110010 .......... S S S S 4 4 8 8\r
+sub 8 er d 1001...000000... .......... U U U U 4 4 2 2\r
+sub 8 er . 1001...000...... A+-DXWLdxI U U U U 4 4 2 2\r
+sub 16 er d 1001...001000... .......... U U U U 4 4 2 2\r
+sub 16 er a 1001...001001... .......... U U U U 4 4 2 2\r
+sub 16 er . 1001...001...... A+-DXWLdxI U U U U 4 4 2 2\r
+sub 32 er d 1001...010000... .......... U U U U 6 6 2 2\r
+sub 32 er a 1001...010001... .......... U U U U 6 6 2 2\r
+sub 32 er . 1001...010...... A+-DXWLdxI U U U U 6 6 2 2\r
+sub 8 re . 1001...100...... A+-DXWL... U U U U 8 8 4 4\r
+sub 16 re . 1001...101...... A+-DXWL... U U U U 8 8 4 4\r
+sub 32 re . 1001...110...... A+-DXWL... U U U U 12 12 4 4\r
+suba 16 . d 1001...011000... .......... U U U U 8 8 2 2\r
+suba 16 . a 1001...011001... .......... U U U U 8 8 2 2\r
+suba 16 . . 1001...011...... A+-DXWLdxI U U U U 8 8 2 2\r
+suba 32 . d 1001...111000... .......... U U U U 6 6 2 2\r
+suba 32 . a 1001...111001... .......... U U U U 6 6 2 2\r
+suba 32 . . 1001...111...... A+-DXWLdxI U U U U 6 6 2 2\r
+subi 8 . d 0000010000000... .......... U U U U 8 8 2 2\r
+subi 8 . . 0000010000...... A+-DXWL... U U U U 12 12 4 4\r
+subi 16 . d 0000010001000... .......... U U U U 8 8 2 2\r
+subi 16 . . 0000010001...... A+-DXWL... U U U U 12 12 4 4\r
+subi 32 . d 0000010010000... .......... U U U U 16 14 2 2\r
+subi 32 . . 0000010010...... A+-DXWL... U U U U 20 20 4 4\r
+subq 8 . d 0101...100000... .......... U U U U 4 4 2 2\r
+subq 8 . . 0101...100...... A+-DXWL... U U U U 8 8 4 4\r
+subq 16 . d 0101...101000... .......... U U U U 4 4 2 2\r
+subq 16 . a 0101...101001... .......... U U U U 8 4 2 2\r
+subq 16 . . 0101...101...... A+-DXWL... U U U U 8 8 4 4\r
+subq 32 . d 0101...110000... .......... U U U U 8 8 2 2\r
+subq 32 . a 0101...110001... .......... U U U U 8 8 2 2\r
+subq 32 . . 0101...110...... A+-DXWL... U U U U 12 12 4 4\r
+subx 8 rr . 1001...100000... .......... U U U U 4 4 2 2\r
+subx 16 rr . 1001...101000... .......... U U U U 4 4 2 2\r
+subx 32 rr . 1001...110000... .......... U U U U 8 6 2 2\r
+subx 8 mm ax7 1001111100001... .......... U U U U 18 18 12 12\r
+subx 8 mm ay7 1001...100001111 .......... U U U U 18 18 12 12\r
+subx 8 mm axy7 1001111100001111 .......... U U U U 18 18 12 12\r
+subx 8 mm . 1001...100001... .......... U U U U 18 18 12 12\r
+subx 16 mm . 1001...101001... .......... U U U U 18 18 12 12\r
+subx 32 mm . 1001...110001... .......... U U U U 30 30 12 12\r
+swap 32 . . 0100100001000... .......... U U U U 4 4 4 4\r
+tas 8 . d 0100101011000... .......... U U U U 4 4 4 4\r
+tas 8 . . 0100101011...... A+-DXWL... U U U U 14 14 12 12\r
+trap 0 . . 010011100100.... .......... U U U U 4 4 4 4\r
+trapt 0 . . 0101000011111100 .......... . . U U . . 4 4\r
+trapt 16 . . 0101000011111010 .......... . . U U . . 6 6\r
+trapt 32 . . 0101000011111011 .......... . . U U . . 8 8\r
+trapf 0 . . 0101000111111100 .......... . . U U . . 4 4\r
+trapf 16 . . 0101000111111010 .......... . . U U . . 6 6\r
+trapf 32 . . 0101000111111011 .......... . . U U . . 8 8\r
+trapcc 0 . . 0101....11111100 .......... . . U U . . 4 4\r
+trapcc 16 . . 0101....11111010 .......... . . U U . . 6 6\r
+trapcc 32 . . 0101....11111011 .......... . . U U . . 8 8\r
+trapv 0 . . 0100111001110110 .......... U U U U 4 4 4 4\r
+tst 8 . d 0100101000000... .......... U U U U 4 4 2 2\r
+tst 8 . . 0100101000...... A+-DXWL... U U U U 4 4 2 2\r
+tst 8 . pcdi 0100101000111010 .......... . . U U . . 7 7\r
+tst 8 . pcix 0100101000111011 .......... . . U U . . 9 9\r
+tst 8 . i 0100101000111100 .......... . . U U . . 6 6\r
+tst 16 . d 0100101001000... .......... U U U U 4 4 2 2\r
+tst 16 . a 0100101001001... .......... . . U U . . 2 2\r
+tst 16 . . 0100101001...... A+-DXWL... U U U U 4 4 2 2\r
+tst 16 . pcdi 0100101001111010 .......... . . U U . . 7 7\r
+tst 16 . pcix 0100101001111011 .......... . . U U . . 9 9\r
+tst 16 . i 0100101001111100 .......... . . U U . . 6 6\r
+tst 32 . d 0100101010000... .......... U U U U 4 4 2 2\r
+tst 32 . a 0100101010001... .......... . . U U . . 2 2\r
+tst 32 . . 0100101010...... A+-DXWL... U U U U 4 4 2 2\r
+tst 32 . pcdi 0100101010111010 .......... . . U U . . 7 7\r
+tst 32 . pcix 0100101010111011 .......... . . U U . . 9 9\r
+tst 32 . i 0100101010111100 .......... . . U U . . 6 6\r
+unlk 32 . a7 0100111001011111 .......... U U U U 12 12 6 6\r
+unlk 32 . . 0100111001011... .......... U U U U 12 12 6 6\r
+unpk 16 rr . 1000...110000... .......... . . U U . . 8 8\r
+unpk 16 mm ax7 1000111110001... .......... . . U U . . 13 13\r
+unpk 16 mm ay7 1000...110001111 .......... . . U U . . 13 13\r
+unpk 16 mm axy7 1000111110001111 .......... . . U U . . 13 13\r
+unpk 16 mm . 1000...110001... .......... . . U U . . 13 13\r
+\r
+\r
+\r
+XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
+M68KMAKE_OPCODE_HANDLER_BODY\r
+\r
+M68KMAKE_OP(1010, 0, ., .)\r
+{\r
+ m68ki_exception_1010();\r
+}\r
+\r
+\r
+M68KMAKE_OP(1111, 0, ., .)\r
+{\r
+ m68ki_exception_1111();\r
+}\r
+\r
+\r
+M68KMAKE_OP(abcd, 8, rr, .)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = DY;\r
+ uint dst = *r_dst;\r
+ uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
+\r
+ FLAG_V = ~res; /* Undefined V behavior */\r
+\r
+ if(res > 9)\r
+ res += 6;\r
+ res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
+ FLAG_X = FLAG_C = (res > 0x99) << 8;\r
+ if(FLAG_C)\r
+ res -= 0xa0;\r
+\r
+ FLAG_V &= res; /* Undefined V behavior part II */\r
+ FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+ FLAG_Z |= res;\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+}\r
+\r
+\r
+M68KMAKE_OP(abcd, 8, mm, ax7)\r
+{\r
+ uint src = OPER_AY_PD_8();\r
+ uint ea = EA_A7_PD_8();\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
+\r
+ FLAG_V = ~res; /* Undefined V behavior */\r
+\r
+ if(res > 9)\r
+ res += 6;\r
+ res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
+ FLAG_X = FLAG_C = (res > 0x99) << 8;\r
+ if(FLAG_C)\r
+ res -= 0xa0;\r
+\r
+ FLAG_V &= res; /* Undefined V behavior part II */\r
+ FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_8(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(abcd, 8, mm, ay7)\r
+{\r
+ uint src = OPER_A7_PD_8();\r
+ uint ea = EA_AX_PD_8();\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
+\r
+ FLAG_V = ~res; /* Undefined V behavior */\r
+\r
+ if(res > 9)\r
+ res += 6;\r
+ res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
+ FLAG_X = FLAG_C = (res > 0x99) << 8;\r
+ if(FLAG_C)\r
+ res -= 0xa0;\r
+\r
+ FLAG_V &= res; /* Undefined V behavior part II */\r
+ FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_8(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(abcd, 8, mm, axy7)\r
+{\r
+ uint src = OPER_A7_PD_8();\r
+ uint ea = EA_A7_PD_8();\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
+\r
+ FLAG_V = ~res; /* Undefined V behavior */\r
+\r
+ if(res > 9)\r
+ res += 6;\r
+ res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
+ FLAG_X = FLAG_C = (res > 0x99) << 8;\r
+ if(FLAG_C)\r
+ res -= 0xa0;\r
+\r
+ FLAG_V &= res; /* Undefined V behavior part II */\r
+ FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_8(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(abcd, 8, mm, .)\r
+{\r
+ uint src = OPER_AY_PD_8();\r
+ uint ea = EA_AX_PD_8();\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
+\r
+ FLAG_V = ~res; /* Undefined V behavior */\r
+\r
+ if(res > 9)\r
+ res += 6;\r
+ res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
+ FLAG_X = FLAG_C = (res > 0x99) << 8;\r
+ if(FLAG_C)\r
+ res -= 0xa0;\r
+\r
+ FLAG_V &= res; /* Undefined V behavior part II */\r
+ FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_8(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(add, 8, er, d)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = MASK_OUT_ABOVE_8(DY);\r
+ uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_V = VFLAG_ADD_8(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(add, 8, er, .)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = M68KMAKE_GET_OPER_AY_8;\r
+ uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_V = VFLAG_ADD_8(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(add, 16, er, d)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = MASK_OUT_ABOVE_16(DY);\r
+ uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_V = VFLAG_ADD_16(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(add, 16, er, a)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = MASK_OUT_ABOVE_16(AY);\r
+ uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_V = VFLAG_ADD_16(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(add, 16, er, .)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = M68KMAKE_GET_OPER_AY_16;\r
+ uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_V = VFLAG_ADD_16(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(add, 32, er, d)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = DY;\r
+ uint dst = *r_dst;\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_V = VFLAG_ADD_32(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+\r
+ *r_dst = FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(add, 32, er, a)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = AY;\r
+ uint dst = *r_dst;\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_V = VFLAG_ADD_32(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+\r
+ *r_dst = FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(add, 32, er, .)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = M68KMAKE_GET_OPER_AY_32;\r
+ uint dst = *r_dst;\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_V = VFLAG_ADD_32(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+\r
+ *r_dst = FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(add, 8, re, .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint src = MASK_OUT_ABOVE_8(DX);\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_V = VFLAG_ADD_8(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+\r
+ m68ki_write_8(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(add, 16, re, .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint src = MASK_OUT_ABOVE_16(DX);\r
+ uint dst = m68ki_read_16(ea);\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_V = VFLAG_ADD_16(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+\r
+ m68ki_write_16(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(add, 32, re, .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint src = DX;\r
+ uint dst = m68ki_read_32(ea);\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_V = VFLAG_ADD_32(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+\r
+ m68ki_write_32(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(adda, 16, ., d)\r
+{\r
+ uint* r_dst = &AX;\r
+\r
+ *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));\r
+}\r
+\r
+\r
+M68KMAKE_OP(adda, 16, ., a)\r
+{\r
+ uint* r_dst = &AX;\r
+\r
+ *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));\r
+}\r
+\r
+\r
+M68KMAKE_OP(adda, 16, ., .)\r
+{\r
+ uint* r_dst = &AX;\r
+\r
+ *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(M68KMAKE_GET_OPER_AY_16));\r
+}\r
+\r
+\r
+M68KMAKE_OP(adda, 32, ., d)\r
+{\r
+ uint* r_dst = &AX;\r
+\r
+ *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);\r
+}\r
+\r
+\r
+M68KMAKE_OP(adda, 32, ., a)\r
+{\r
+ uint* r_dst = &AX;\r
+\r
+ *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);\r
+}\r
+\r
+\r
+M68KMAKE_OP(adda, 32, ., .)\r
+{\r
+ uint* r_dst = &AX;\r
+\r
+ *r_dst = MASK_OUT_ABOVE_32(*r_dst + M68KMAKE_GET_OPER_AY_32);\r
+}\r
+\r
+\r
+M68KMAKE_OP(addi, 8, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint src = OPER_I_8();\r
+ uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_V = VFLAG_ADD_8(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(addi, 8, ., .)\r
+{\r
+ uint src = OPER_I_8();\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_V = VFLAG_ADD_8(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+\r
+ m68ki_write_8(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(addi, 16, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint src = OPER_I_16();\r
+ uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_V = VFLAG_ADD_16(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(addi, 16, ., .)\r
+{\r
+ uint src = OPER_I_16();\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint dst = m68ki_read_16(ea);\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_V = VFLAG_ADD_16(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+\r
+ m68ki_write_16(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(addi, 32, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint src = OPER_I_32();\r
+ uint dst = *r_dst;\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_V = VFLAG_ADD_32(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+\r
+ *r_dst = FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(addi, 32, ., .)\r
+{\r
+ uint src = OPER_I_32();\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint dst = m68ki_read_32(ea);\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_V = VFLAG_ADD_32(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+\r
+ m68ki_write_32(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(addq, 8, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_V = VFLAG_ADD_8(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(addq, 8, ., .)\r
+{\r
+ uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_V = VFLAG_ADD_8(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+\r
+ m68ki_write_8(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(addq, 16, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_V = VFLAG_ADD_16(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(addq, 16, ., a)\r
+{\r
+ uint* r_dst = &AY;\r
+\r
+ *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);\r
+}\r
+\r
+\r
+M68KMAKE_OP(addq, 16, ., .)\r
+{\r
+ uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint dst = m68ki_read_16(ea);\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_V = VFLAG_ADD_16(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+\r
+ m68ki_write_16(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(addq, 32, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint dst = *r_dst;\r
+ uint res = src + dst;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_V = VFLAG_ADD_32(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+\r
+ *r_dst = FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(addq, 32, ., a)\r
+{\r
+ uint* r_dst = &AY;\r
+\r
+ *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);\r
+}\r
+\r
+\r
+M68KMAKE_OP(addq, 32, ., .)\r
+{\r
+ uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint dst = m68ki_read_32(ea);\r
+ uint res = src + dst;\r
+\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_V = VFLAG_ADD_32(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+\r
+ m68ki_write_32(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(addx, 8, rr, .)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = MASK_OUT_ABOVE_8(DY);\r
+ uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = src + dst + XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_V = VFLAG_ADD_8(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+ FLAG_Z |= res;\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+}\r
+\r
+\r
+M68KMAKE_OP(addx, 16, rr, .)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = MASK_OUT_ABOVE_16(DY);\r
+ uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = src + dst + XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_V = VFLAG_ADD_16(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+\r
+ res = MASK_OUT_ABOVE_16(res);\r
+ FLAG_Z |= res;\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+}\r
+\r
+\r
+M68KMAKE_OP(addx, 32, rr, .)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = DY;\r
+ uint dst = *r_dst;\r
+ uint res = src + dst + XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_V = VFLAG_ADD_32(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
+\r
+ res = MASK_OUT_ABOVE_32(res);\r
+ FLAG_Z |= res;\r
+\r
+ *r_dst = res;\r
+}\r
+\r
+\r
+M68KMAKE_OP(addx, 8, mm, ax7)\r
+{\r
+ uint src = OPER_AY_PD_8();\r
+ uint ea = EA_A7_PD_8();\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = src + dst + XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_V = VFLAG_ADD_8(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_8(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(addx, 8, mm, ay7)\r
+{\r
+ uint src = OPER_A7_PD_8();\r
+ uint ea = EA_AX_PD_8();\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = src + dst + XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_V = VFLAG_ADD_8(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_8(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(addx, 8, mm, axy7)\r
+{\r
+ uint src = OPER_A7_PD_8();\r
+ uint ea = EA_A7_PD_8();\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = src + dst + XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_V = VFLAG_ADD_8(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_8(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(addx, 8, mm, .)\r
+{\r
+ uint src = OPER_AY_PD_8();\r
+ uint ea = EA_AX_PD_8();\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = src + dst + XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_V = VFLAG_ADD_8(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_8(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(addx, 16, mm, .)\r
+{\r
+ uint src = OPER_AY_PD_16();\r
+ uint ea = EA_AX_PD_16();\r
+ uint dst = m68ki_read_16(ea);\r
+ uint res = src + dst + XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_V = VFLAG_ADD_16(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+\r
+ res = MASK_OUT_ABOVE_16(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_16(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(addx, 32, mm, .)\r
+{\r
+ uint src = OPER_AY_PD_32();\r
+ uint ea = EA_AX_PD_32();\r
+ uint dst = m68ki_read_32(ea);\r
+ uint res = src + dst + XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_V = VFLAG_ADD_32(src, dst, res);\r
+ FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
+\r
+ res = MASK_OUT_ABOVE_32(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_32(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(and, 8, er, d)\r
+{\r
+ FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));\r
+\r
+ FLAG_N = NFLAG_8(FLAG_Z);\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(and, 8, er, .)\r
+{\r
+ FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));\r
+\r
+ FLAG_N = NFLAG_8(FLAG_Z);\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(and, 16, er, d)\r
+{\r
+ FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));\r
+\r
+ FLAG_N = NFLAG_16(FLAG_Z);\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(and, 16, er, .)\r
+{\r
+ FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));\r
+\r
+ FLAG_N = NFLAG_16(FLAG_Z);\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(and, 32, er, d)\r
+{\r
+ FLAG_Z = DX &= DY;\r
+\r
+ FLAG_N = NFLAG_32(FLAG_Z);\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(and, 32, er, .)\r
+{\r
+ FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;\r
+\r
+ FLAG_N = NFLAG_32(FLAG_Z);\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(and, 8, re, .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint res = DX & m68ki_read_8(ea);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+\r
+ m68ki_write_8(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(and, 16, re, .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint res = DX & m68ki_read_16(ea);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+\r
+ m68ki_write_16(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(and, 32, re, .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint res = DX & m68ki_read_32(ea);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+\r
+ m68ki_write_32(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(andi, 8, ., d)\r
+{\r
+ FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));\r
+\r
+ FLAG_N = NFLAG_8(FLAG_Z);\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(andi, 8, ., .)\r
+{\r
+ uint src = OPER_I_8();\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint res = src & m68ki_read_8(ea);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+\r
+ m68ki_write_8(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(andi, 16, ., d)\r
+{\r
+ FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));\r
+\r
+ FLAG_N = NFLAG_16(FLAG_Z);\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(andi, 16, ., .)\r
+{\r
+ uint src = OPER_I_16();\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint res = src & m68ki_read_16(ea);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+\r
+ m68ki_write_16(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(andi, 32, ., d)\r
+{\r
+ FLAG_Z = DY &= (OPER_I_32());\r
+\r
+ FLAG_N = NFLAG_32(FLAG_Z);\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(andi, 32, ., .)\r
+{\r
+ uint src = OPER_I_32();\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint res = src & m68ki_read_32(ea);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+\r
+ m68ki_write_32(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(andi, 16, toc, .)\r
+{\r
+ m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());\r
+}\r
+\r
+\r
+M68KMAKE_OP(andi, 16, tos, .)\r
+{\r
+ if(FLAG_S)\r
+ {\r
+ uint src = OPER_I_16();\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_set_sr(m68ki_get_sr() & src);\r
+ return;\r
+ }\r
+ m68ki_exception_privilege_violation();\r
+}\r
+\r
+\r
+M68KMAKE_OP(asr, 8, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = src >> shift;\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ if(GET_MSB_8(src))\r
+ res |= m68ki_shift_8_table[shift];\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_X = FLAG_C = src << (9-shift);\r
+}\r
+\r
+\r
+M68KMAKE_OP(asr, 16, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = src >> shift;\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ if(GET_MSB_16(src))\r
+ res |= m68ki_shift_16_table[shift];\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_X = FLAG_C = src << (9-shift);\r
+}\r
+\r
+\r
+M68KMAKE_OP(asr, 32, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = *r_dst;\r
+ uint res = src >> shift;\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ if(GET_MSB_32(src))\r
+ res |= m68ki_shift_32_table[shift];\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_X = FLAG_C = src << (9-shift);\r
+}\r
+\r
+\r
+M68KMAKE_OP(asr, 8, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = DX & 0x3f;\r
+ uint src = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = src >> shift;\r
+\r
+ if(shift != 0)\r
+ {\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ if(shift < 8)\r
+ {\r
+ if(GET_MSB_8(src))\r
+ res |= m68ki_shift_8_table[shift];\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+\r
+ FLAG_X = FLAG_C = src << (9-shift);\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ if(GET_MSB_8(src))\r
+ {\r
+ *r_dst |= 0xff;\r
+ FLAG_C = CFLAG_SET;\r
+ FLAG_X = XFLAG_SET;\r
+ FLAG_N = NFLAG_SET;\r
+ FLAG_Z = ZFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ *r_dst &= 0xffffff00;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_X = XFLAG_CLEAR;\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = ZFLAG_SET;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_8(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(asr, 16, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = DX & 0x3f;\r
+ uint src = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = src >> shift;\r
+\r
+ if(shift != 0)\r
+ {\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ if(shift < 16)\r
+ {\r
+ if(GET_MSB_16(src))\r
+ res |= m68ki_shift_16_table[shift];\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+\r
+ FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ if(GET_MSB_16(src))\r
+ {\r
+ *r_dst |= 0xffff;\r
+ FLAG_C = CFLAG_SET;\r
+ FLAG_X = XFLAG_SET;\r
+ FLAG_N = NFLAG_SET;\r
+ FLAG_Z = ZFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ *r_dst &= 0xffff0000;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_X = XFLAG_CLEAR;\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = ZFLAG_SET;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_16(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(asr, 32, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = DX & 0x3f;\r
+ uint src = *r_dst;\r
+ uint res = src >> shift;\r
+\r
+ if(shift != 0)\r
+ {\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ if(shift < 32)\r
+ {\r
+ if(GET_MSB_32(src))\r
+ res |= m68ki_shift_32_table[shift];\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ if(GET_MSB_32(src))\r
+ {\r
+ *r_dst = 0xffffffff;\r
+ FLAG_C = CFLAG_SET;\r
+ FLAG_X = XFLAG_SET;\r
+ FLAG_N = NFLAG_SET;\r
+ FLAG_Z = ZFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ *r_dst = 0;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_X = XFLAG_CLEAR;\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = ZFLAG_SET;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_32(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(asr, 16, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint src = m68ki_read_16(ea);\r
+ uint res = src >> 1;\r
+\r
+ if(GET_MSB_16(src))\r
+ res |= 0x8000;\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = FLAG_X = src << 8;\r
+}\r
+\r
+\r
+M68KMAKE_OP(asl, 8, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = MASK_OUT_ABOVE_8(src << shift);\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+\r
+ FLAG_X = FLAG_C = src << shift;\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ src &= m68ki_shift_8_table[shift + 1];\r
+ FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;\r
+}\r
+\r
+\r
+M68KMAKE_OP(asl, 16, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = MASK_OUT_ABOVE_16(src << shift);\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_X = FLAG_C = src >> (8-shift);\r
+ src &= m68ki_shift_16_table[shift + 1];\r
+ FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;\r
+}\r
+\r
+\r
+M68KMAKE_OP(asl, 32, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = *r_dst;\r
+ uint res = MASK_OUT_ABOVE_32(src << shift);\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_X = FLAG_C = src >> (24-shift);\r
+ src &= m68ki_shift_32_table[shift + 1];\r
+ FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;\r
+}\r
+\r
+\r
+M68KMAKE_OP(asl, 8, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = DX & 0x3f;\r
+ uint src = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = MASK_OUT_ABOVE_8(src << shift);\r
+\r
+ if(shift != 0)\r
+ {\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ if(shift < 8)\r
+ {\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+ FLAG_X = FLAG_C = src << shift;\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ src &= m68ki_shift_8_table[shift + 1];\r
+ FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;\r
+ return;\r
+ }\r
+\r
+ *r_dst &= 0xffffff00;\r
+ FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = ZFLAG_SET;\r
+ FLAG_V = (!(src == 0))<<7;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_8(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(asl, 16, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = DX & 0x3f;\r
+ uint src = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = MASK_OUT_ABOVE_16(src << shift);\r
+\r
+ if(shift != 0)\r
+ {\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ if(shift < 16)\r
+ {\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+ FLAG_X = FLAG_C = (src << shift) >> 8;\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ src &= m68ki_shift_16_table[shift + 1];\r
+ FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;\r
+ return;\r
+ }\r
+\r
+ *r_dst &= 0xffff0000;\r
+ FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = ZFLAG_SET;\r
+ FLAG_V = (!(src == 0))<<7;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_16(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(asl, 32, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = DX & 0x3f;\r
+ uint src = *r_dst;\r
+ uint res = MASK_OUT_ABOVE_32(src << shift);\r
+\r
+ if(shift != 0)\r
+ {\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ if(shift < 32)\r
+ {\r
+ *r_dst = res;\r
+ FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ src &= m68ki_shift_32_table[shift + 1];\r
+ FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;\r
+ return;\r
+ }\r
+\r
+ *r_dst = 0;\r
+ FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = ZFLAG_SET;\r
+ FLAG_V = (!(src == 0))<<7;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_32(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(asl, 16, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint src = m68ki_read_16(ea);\r
+ uint res = MASK_OUT_ABOVE_16(src << 1);\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_X = FLAG_C = src >> 7;\r
+ src &= 0xc000;\r
+ FLAG_V = (!(src == 0 || src == 0xc000))<<7;\r
+}\r
+\r
+\r
+M68KMAKE_OP(bcc, 8, ., .)\r
+{\r
+ if(M68KMAKE_CC)\r
+ {\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
+ return;\r
+ }\r
+ USE_CYCLES(CYC_BCC_NOTAKE_B);\r
+}\r
+\r
+\r
+M68KMAKE_OP(bcc, 16, ., .)\r
+{\r
+ if(M68KMAKE_CC)\r
+ {\r
+ uint offset = OPER_I_16();\r
+ REG_PC -= 2;\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_branch_16(offset);\r
+ return;\r
+ }\r
+ REG_PC += 2;\r
+ USE_CYCLES(CYC_BCC_NOTAKE_W);\r
+}\r
+\r
+\r
+M68KMAKE_OP(bcc, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ if(M68KMAKE_CC)\r
+ {\r
+ uint offset = OPER_I_32();\r
+ REG_PC -= 4;\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_branch_32(offset);\r
+ return;\r
+ }\r
+ REG_PC += 4;\r
+ return;\r
+ }\r
+ else\r
+ {\r
+ if(M68KMAKE_CC)\r
+ {\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
+ return;\r
+ }\r
+ USE_CYCLES(CYC_BCC_NOTAKE_B);\r
+ }\r
+}\r
+\r
+\r
+M68KMAKE_OP(bchg, 32, r, d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint mask = 1 << (DX & 0x1f);\r
+\r
+ FLAG_Z = *r_dst & mask;\r
+ *r_dst ^= mask;\r
+}\r
+\r
+\r
+M68KMAKE_OP(bchg, 8, r, .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint src = m68ki_read_8(ea);\r
+ uint mask = 1 << (DX & 7);\r
+\r
+ FLAG_Z = src & mask;\r
+ m68ki_write_8(ea, src ^ mask);\r
+}\r
+\r
+\r
+M68KMAKE_OP(bchg, 32, s, d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint mask = 1 << (OPER_I_8() & 0x1f);\r
+\r
+ FLAG_Z = *r_dst & mask;\r
+ *r_dst ^= mask;\r
+}\r
+\r
+\r
+M68KMAKE_OP(bchg, 8, s, .)\r
+{\r
+ uint mask = 1 << (OPER_I_8() & 7);\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint src = m68ki_read_8(ea);\r
+\r
+ FLAG_Z = src & mask;\r
+ m68ki_write_8(ea, src ^ mask);\r
+}\r
+\r
+\r
+M68KMAKE_OP(bclr, 32, r, d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint mask = 1 << (DX & 0x1f);\r
+\r
+ FLAG_Z = *r_dst & mask;\r
+ *r_dst &= ~mask;\r
+}\r
+\r
+\r
+M68KMAKE_OP(bclr, 8, r, .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint src = m68ki_read_8(ea);\r
+ uint mask = 1 << (DX & 7);\r
+\r
+ FLAG_Z = src & mask;\r
+ m68ki_write_8(ea, src & ~mask);\r
+}\r
+\r
+\r
+M68KMAKE_OP(bclr, 32, s, d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint mask = 1 << (OPER_I_8() & 0x1f);\r
+\r
+ FLAG_Z = *r_dst & mask;\r
+ *r_dst &= ~mask;\r
+}\r
+\r
+\r
+M68KMAKE_OP(bclr, 8, s, .)\r
+{\r
+ uint mask = 1 << (OPER_I_8() & 7);\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint src = m68ki_read_8(ea);\r
+\r
+ FLAG_Z = src & mask;\r
+ m68ki_write_8(ea, src & ~mask);\r
+}\r
+\r
+\r
+M68KMAKE_OP(bfchg, 32, ., d)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint offset = (word2>>6)&31;\r
+ uint width = word2;\r
+ uint* data = &DY;\r
+ uint64 mask;\r
+\r
+\r
+ if(BIT_B(word2))\r
+ offset = REG_D[offset&7];\r
+ if(BIT_5(word2))\r
+ width = REG_D[width&7];\r
+\r
+ offset &= 31;\r
+ width = ((width-1) & 31) + 1;\r
+\r
+ mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
+ mask = ROR_32(mask, offset);\r
+\r
+ FLAG_N = NFLAG_32(*data<<offset);\r
+ FLAG_Z = *data & mask;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ *data ^= mask;\r
+\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bfchg, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ sint offset = (word2>>6)&31;\r
+ uint width = word2;\r
+ uint mask_base;\r
+ uint data_long;\r
+ uint mask_long;\r
+ uint data_byte = 0;\r
+ uint mask_byte = 0;\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+\r
+\r
+ if(BIT_B(word2))\r
+ offset = MAKE_INT_32(REG_D[offset&7]);\r
+ if(BIT_5(word2))\r
+ width = REG_D[width&7];\r
+\r
+ /* Offset is signed so we have to use ugly math =( */\r
+ ea += offset / 8;\r
+ offset %= 8;\r
+ if(offset < 0)\r
+ {\r
+ offset += 8;\r
+ ea--;\r
+ }\r
+ width = ((width-1) & 31) + 1;\r
+\r
+ mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
+ mask_long = mask_base >> offset;\r
+\r
+ data_long = m68ki_read_32(ea);\r
+ FLAG_N = NFLAG_32(data_long << offset);\r
+ FLAG_Z = data_long & mask_long;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ m68ki_write_32(ea, data_long ^ mask_long);\r
+\r
+ if((width + offset) > 32)\r
+ {\r
+ mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
+ data_byte = m68ki_read_8(ea+4);\r
+ FLAG_Z |= (data_byte & mask_byte);\r
+ m68ki_write_8(ea+4, data_byte ^ mask_byte);\r
+ }\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bfclr, 32, ., d)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint offset = (word2>>6)&31;\r
+ uint width = word2;\r
+ uint* data = &DY;\r
+ uint64 mask;\r
+\r
+\r
+ if(BIT_B(word2))\r
+ offset = REG_D[offset&7];\r
+ if(BIT_5(word2))\r
+ width = REG_D[width&7];\r
+\r
+\r
+ offset &= 31;\r
+ width = ((width-1) & 31) + 1;\r
+\r
+\r
+ mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
+ mask = ROR_32(mask, offset);\r
+\r
+ FLAG_N = NFLAG_32(*data<<offset);\r
+ FLAG_Z = *data & mask;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ *data &= ~mask;\r
+\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bfclr, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ sint offset = (word2>>6)&31;\r
+ uint width = word2;\r
+ uint mask_base;\r
+ uint data_long;\r
+ uint mask_long;\r
+ uint data_byte = 0;\r
+ uint mask_byte = 0;\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+\r
+\r
+ if(BIT_B(word2))\r
+ offset = MAKE_INT_32(REG_D[offset&7]);\r
+ if(BIT_5(word2))\r
+ width = REG_D[width&7];\r
+\r
+ /* Offset is signed so we have to use ugly math =( */\r
+ ea += offset / 8;\r
+ offset %= 8;\r
+ if(offset < 0)\r
+ {\r
+ offset += 8;\r
+ ea--;\r
+ }\r
+ width = ((width-1) & 31) + 1;\r
+\r
+ mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
+ mask_long = mask_base >> offset;\r
+\r
+ data_long = m68ki_read_32(ea);\r
+ FLAG_N = NFLAG_32(data_long << offset);\r
+ FLAG_Z = data_long & mask_long;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ m68ki_write_32(ea, data_long & ~mask_long);\r
+\r
+ if((width + offset) > 32)\r
+ {\r
+ mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
+ data_byte = m68ki_read_8(ea+4);\r
+ FLAG_Z |= (data_byte & mask_byte);\r
+ m68ki_write_8(ea+4, data_byte & ~mask_byte);\r
+ }\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bfexts, 32, ., d)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint offset = (word2>>6)&31;\r
+ uint width = word2;\r
+ uint64 data = DY;\r
+\r
+\r
+ if(BIT_B(word2))\r
+ offset = REG_D[offset&7];\r
+ if(BIT_5(word2))\r
+ width = REG_D[width&7];\r
+\r
+ offset &= 31;\r
+ width = ((width-1) & 31) + 1;\r
+\r
+ data = ROL_32(data, offset);\r
+ FLAG_N = NFLAG_32(data);\r
+ data = MAKE_INT_32(data) >> (32 - width);\r
+\r
+ FLAG_Z = data;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ REG_D[(word2>>12)&7] = data;\r
+\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bfexts, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ sint offset = (word2>>6)&31;\r
+ uint width = word2;\r
+ uint data;\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+\r
+\r
+ if(BIT_B(word2))\r
+ offset = MAKE_INT_32(REG_D[offset&7]);\r
+ if(BIT_5(word2))\r
+ width = REG_D[width&7];\r
+\r
+ /* Offset is signed so we have to use ugly math =( */\r
+ ea += offset / 8;\r
+ offset %= 8;\r
+ if(offset < 0)\r
+ {\r
+ offset += 8;\r
+ ea--;\r
+ }\r
+ width = ((width-1) & 31) + 1;\r
+\r
+ data = m68ki_read_32(ea);\r
+\r
+ data = MASK_OUT_ABOVE_32(data<<offset);\r
+\r
+ if((offset+width) > 32)\r
+ data |= (m68ki_read_8(ea+4) << offset) >> 8;\r
+\r
+ FLAG_N = NFLAG_32(data);\r
+ data = MAKE_INT_32(data) >> (32 - width);\r
+\r
+ FLAG_Z = data;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ REG_D[(word2 >> 12) & 7] = data;\r
+\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bfextu, 32, ., d)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint offset = (word2>>6)&31;\r
+ uint width = word2;\r
+ uint64 data = DY;\r
+\r
+\r
+ if(BIT_B(word2))\r
+ offset = REG_D[offset&7];\r
+ if(BIT_5(word2))\r
+ width = REG_D[width&7];\r
+\r
+ offset &= 31;\r
+ width = ((width-1) & 31) + 1;\r
+\r
+ data = ROL_32(data, offset);\r
+ FLAG_N = NFLAG_32(data);\r
+ data >>= 32 - width;\r
+\r
+ FLAG_Z = data;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ REG_D[(word2>>12)&7] = data;\r
+\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bfextu, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ sint offset = (word2>>6)&31;\r
+ uint width = word2;\r
+ uint data;\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+\r
+\r
+ if(BIT_B(word2))\r
+ offset = MAKE_INT_32(REG_D[offset&7]);\r
+ if(BIT_5(word2))\r
+ width = REG_D[width&7];\r
+\r
+ /* Offset is signed so we have to use ugly math =( */\r
+ ea += offset / 8;\r
+ offset %= 8;\r
+ if(offset < 0)\r
+ {\r
+ offset += 8;\r
+ ea--;\r
+ }\r
+ width = ((width-1) & 31) + 1;\r
+\r
+ data = m68ki_read_32(ea);\r
+ data = MASK_OUT_ABOVE_32(data<<offset);\r
+\r
+ if((offset+width) > 32)\r
+ data |= (m68ki_read_8(ea+4) << offset) >> 8;\r
+\r
+ FLAG_N = NFLAG_32(data);\r
+ data >>= (32 - width);\r
+\r
+ FLAG_Z = data;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ REG_D[(word2 >> 12) & 7] = data;\r
+\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bfffo, 32, ., d)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint offset = (word2>>6)&31;\r
+ uint width = word2;\r
+ uint64 data = DY;\r
+ uint bit;\r
+\r
+\r
+ if(BIT_B(word2))\r
+ offset = REG_D[offset&7];\r
+ if(BIT_5(word2))\r
+ width = REG_D[width&7];\r
+\r
+ offset &= 31;\r
+ width = ((width-1) & 31) + 1;\r
+\r
+ data = ROL_32(data, offset);\r
+ FLAG_N = NFLAG_32(data);\r
+ data >>= 32 - width;\r
+\r
+ FLAG_Z = data;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)\r
+ offset++;\r
+\r
+ REG_D[(word2>>12)&7] = offset;\r
+\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bfffo, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ sint offset = (word2>>6)&31;\r
+ sint local_offset;\r
+ uint width = word2;\r
+ uint data;\r
+ uint bit;\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+\r
+\r
+ if(BIT_B(word2))\r
+ offset = MAKE_INT_32(REG_D[offset&7]);\r
+ if(BIT_5(word2))\r
+ width = REG_D[width&7];\r
+\r
+ /* Offset is signed so we have to use ugly math =( */\r
+ ea += offset / 8;\r
+ local_offset = offset % 8;\r
+ if(local_offset < 0)\r
+ {\r
+ local_offset += 8;\r
+ ea--;\r
+ }\r
+ width = ((width-1) & 31) + 1;\r
+\r
+ data = m68ki_read_32(ea);\r
+ data = MASK_OUT_ABOVE_32(data<<local_offset);\r
+\r
+ if((local_offset+width) > 32)\r
+ data |= (m68ki_read_8(ea+4) << local_offset) >> 8;\r
+\r
+ FLAG_N = NFLAG_32(data);\r
+ data >>= (32 - width);\r
+\r
+ FLAG_Z = data;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)\r
+ offset++;\r
+\r
+ REG_D[(word2>>12)&7] = offset;\r
+\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bfins, 32, ., d)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint offset = (word2>>6)&31;\r
+ uint width = word2;\r
+ uint* data = &DY;\r
+ uint64 mask;\r
+ uint64 insert = REG_D[(word2>>12)&7];\r
+\r
+\r
+ if(BIT_B(word2))\r
+ offset = REG_D[offset&7];\r
+ if(BIT_5(word2))\r
+ width = REG_D[width&7];\r
+\r
+\r
+ offset &= 31;\r
+ width = ((width-1) & 31) + 1;\r
+\r
+\r
+ mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
+ mask = ROR_32(mask, offset);\r
+\r
+ insert = MASK_OUT_ABOVE_32(insert << (32 - width));\r
+ FLAG_N = NFLAG_32(insert);\r
+ FLAG_Z = insert;\r
+ insert = ROR_32(insert, offset);\r
+\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ *data &= ~mask;\r
+ *data |= insert;\r
+\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bfins, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ sint offset = (word2>>6)&31;\r
+ uint width = word2;\r
+ uint insert_base = REG_D[(word2>>12)&7];\r
+ uint insert_long;\r
+ uint insert_byte;\r
+ uint mask_base;\r
+ uint data_long;\r
+ uint mask_long;\r
+ uint data_byte = 0;\r
+ uint mask_byte = 0;\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+\r
+\r
+ if(BIT_B(word2))\r
+ offset = MAKE_INT_32(REG_D[offset&7]);\r
+ if(BIT_5(word2))\r
+ width = REG_D[width&7];\r
+\r
+ /* Offset is signed so we have to use ugly math =( */\r
+ ea += offset / 8;\r
+ offset %= 8;\r
+ if(offset < 0)\r
+ {\r
+ offset += 8;\r
+ ea--;\r
+ }\r
+ width = ((width-1) & 31) + 1;\r
+\r
+ mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
+ mask_long = mask_base >> offset;\r
+\r
+ insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));\r
+ FLAG_N = NFLAG_32(insert_base);\r
+ FLAG_Z = insert_base;\r
+ insert_long = insert_base >> offset;\r
+\r
+ data_long = m68ki_read_32(ea);\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);\r
+\r
+ if((width + offset) > 32)\r
+ {\r
+ mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
+ insert_byte = MASK_OUT_ABOVE_8(insert_base);\r
+ data_byte = m68ki_read_8(ea+4);\r
+ FLAG_Z |= (data_byte & mask_byte);\r
+ m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);\r
+ }\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bfset, 32, ., d)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint offset = (word2>>6)&31;\r
+ uint width = word2;\r
+ uint* data = &DY;\r
+ uint64 mask;\r
+\r
+\r
+ if(BIT_B(word2))\r
+ offset = REG_D[offset&7];\r
+ if(BIT_5(word2))\r
+ width = REG_D[width&7];\r
+\r
+\r
+ offset &= 31;\r
+ width = ((width-1) & 31) + 1;\r
+\r
+\r
+ mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
+ mask = ROR_32(mask, offset);\r
+\r
+ FLAG_N = NFLAG_32(*data<<offset);\r
+ FLAG_Z = *data & mask;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ *data |= mask;\r
+\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bfset, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ sint offset = (word2>>6)&31;\r
+ uint width = word2;\r
+ uint mask_base;\r
+ uint data_long;\r
+ uint mask_long;\r
+ uint data_byte = 0;\r
+ uint mask_byte = 0;\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+\r
+\r
+ if(BIT_B(word2))\r
+ offset = MAKE_INT_32(REG_D[offset&7]);\r
+ if(BIT_5(word2))\r
+ width = REG_D[width&7];\r
+\r
+ /* Offset is signed so we have to use ugly math =( */\r
+ ea += offset / 8;\r
+ offset %= 8;\r
+ if(offset < 0)\r
+ {\r
+ offset += 8;\r
+ ea--;\r
+ }\r
+ width = ((width-1) & 31) + 1;\r
+\r
+\r
+ mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
+ mask_long = mask_base >> offset;\r
+\r
+ data_long = m68ki_read_32(ea);\r
+ FLAG_N = NFLAG_32(data_long << offset);\r
+ FLAG_Z = data_long & mask_long;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ m68ki_write_32(ea, data_long | mask_long);\r
+\r
+ if((width + offset) > 32)\r
+ {\r
+ mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
+ data_byte = m68ki_read_8(ea+4);\r
+ FLAG_Z |= (data_byte & mask_byte);\r
+ m68ki_write_8(ea+4, data_byte | mask_byte);\r
+ }\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bftst, 32, ., d)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint offset = (word2>>6)&31;\r
+ uint width = word2;\r
+ uint* data = &DY;\r
+ uint64 mask;\r
+\r
+\r
+ if(BIT_B(word2))\r
+ offset = REG_D[offset&7];\r
+ if(BIT_5(word2))\r
+ width = REG_D[width&7];\r
+\r
+\r
+ offset &= 31;\r
+ width = ((width-1) & 31) + 1;\r
+\r
+\r
+ mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
+ mask = ROR_32(mask, offset);\r
+\r
+ FLAG_N = NFLAG_32(*data<<offset);\r
+ FLAG_Z = *data & mask;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bftst, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ sint offset = (word2>>6)&31;\r
+ uint width = word2;\r
+ uint mask_base;\r
+ uint data_long;\r
+ uint mask_long;\r
+ uint data_byte = 0;\r
+ uint mask_byte = 0;\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+\r
+ if(BIT_B(word2))\r
+ offset = MAKE_INT_32(REG_D[offset&7]);\r
+ if(BIT_5(word2))\r
+ width = REG_D[width&7];\r
+\r
+ /* Offset is signed so we have to use ugly math =( */\r
+ ea += offset / 8;\r
+ offset %= 8;\r
+ if(offset < 0)\r
+ {\r
+ offset += 8;\r
+ ea--;\r
+ }\r
+ width = ((width-1) & 31) + 1;\r
+\r
+\r
+ mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
+ mask_long = mask_base >> offset;\r
+\r
+ data_long = m68ki_read_32(ea);\r
+ FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;\r
+ FLAG_Z = data_long & mask_long;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ if((width + offset) > 32)\r
+ {\r
+ mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
+ data_byte = m68ki_read_8(ea+4);\r
+ FLAG_Z |= (data_byte & mask_byte);\r
+ }\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bkpt, 0, ., .)\r
+{\r
+ if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
+ {\r
+ m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bra, 8, ., .)\r
+{\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
+// if(REG_PC == REG_PPC)\r
+// USE_ALL_CYCLES();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bra, 16, ., .)\r
+{\r
+ uint offset = OPER_I_16();\r
+ REG_PC -= 2;\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_branch_16(offset);\r
+// if(REG_PC == REG_PPC)\r
+// USE_ALL_CYCLES();\r
+}\r
+\r
+\r
+M68KMAKE_OP(bra, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint offset = OPER_I_32();\r
+ REG_PC -= 4;\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_branch_32(offset);\r
+ if(REG_PC == REG_PPC)\r
+ USE_ALL_CYCLES();\r
+ return;\r
+ }\r
+ else\r
+ {\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
+// if(REG_PC == REG_PPC)\r
+// USE_ALL_CYCLES();\r
+ }\r
+}\r
+\r
+\r
+M68KMAKE_OP(bset, 32, r, d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint mask = 1 << (DX & 0x1f);\r
+\r
+ FLAG_Z = *r_dst & mask;\r
+ *r_dst |= mask;\r
+}\r
+\r
+\r
+M68KMAKE_OP(bset, 8, r, .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint src = m68ki_read_8(ea);\r
+ uint mask = 1 << (DX & 7);\r
+\r
+ FLAG_Z = src & mask;\r
+ m68ki_write_8(ea, src | mask);\r
+}\r
+\r
+\r
+M68KMAKE_OP(bset, 32, s, d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint mask = 1 << (OPER_I_8() & 0x1f);\r
+\r
+ FLAG_Z = *r_dst & mask;\r
+ *r_dst |= mask;\r
+}\r
+\r
+\r
+M68KMAKE_OP(bset, 8, s, .)\r
+{\r
+ uint mask = 1 << (OPER_I_8() & 7);\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint src = m68ki_read_8(ea);\r
+\r
+ FLAG_Z = src & mask;\r
+ m68ki_write_8(ea, src | mask);\r
+}\r
+\r
+\r
+M68KMAKE_OP(bsr, 8, ., .)\r
+{\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_push_32(REG_PC);\r
+ m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
+}\r
+\r
+\r
+M68KMAKE_OP(bsr, 16, ., .)\r
+{\r
+ uint offset = OPER_I_16();\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_push_32(REG_PC);\r
+ REG_PC -= 2;\r
+ m68ki_branch_16(offset);\r
+}\r
+\r
+\r
+M68KMAKE_OP(bsr, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint offset = OPER_I_32();\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_push_32(REG_PC);\r
+ REG_PC -= 4;\r
+ m68ki_branch_32(offset);\r
+ return;\r
+ }\r
+ else\r
+ {\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_push_32(REG_PC);\r
+ m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
+ }\r
+}\r
+\r
+\r
+M68KMAKE_OP(btst, 32, r, d)\r
+{\r
+ FLAG_Z = DY & (1 << (DX & 0x1f));\r
+}\r
+\r
+\r
+M68KMAKE_OP(btst, 8, r, .)\r
+{\r
+ FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));\r
+}\r
+\r
+\r
+M68KMAKE_OP(btst, 32, s, d)\r
+{\r
+ FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));\r
+}\r
+\r
+\r
+M68KMAKE_OP(btst, 8, s, .)\r
+{\r
+ uint bit = OPER_I_8() & 7;\r
+\r
+ FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);\r
+}\r
+\r
+\r
+M68KMAKE_OP(callm, 32, ., .)\r
+{\r
+ /* note: watch out for pcrelative modes */\r
+ if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
+ {\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ REG_PC += 2;\r
+(void)ea; /* just to avoid an 'unused variable' warning */\r
+ M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
+ m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
+ m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(cas, 8, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint dest = m68ki_read_8(ea);\r
+ uint* compare = ®_D[word2 & 7];\r
+ uint res = dest - MASK_OUT_ABOVE_8(*compare);\r
+\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+ FLAG_V = VFLAG_SUB_8(*compare, dest, res);\r
+ FLAG_C = CFLAG_8(res);\r
+\r
+ if(COND_NE())\r
+ *compare = MASK_OUT_BELOW_8(*compare) | dest;\r
+ else\r
+ {\r
+ USE_CYCLES(3);\r
+ m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));\r
+ }\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(cas, 16, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint dest = m68ki_read_16(ea);\r
+ uint* compare = ®_D[word2 & 7];\r
+ uint res = dest - MASK_OUT_ABOVE_16(*compare);\r
+\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+ FLAG_V = VFLAG_SUB_16(*compare, dest, res);\r
+ FLAG_C = CFLAG_16(res);\r
+\r
+ if(COND_NE())\r
+ *compare = MASK_OUT_BELOW_16(*compare) | dest;\r
+ else\r
+ {\r
+ USE_CYCLES(3);\r
+ m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));\r
+ }\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(cas, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint dest = m68ki_read_32(ea);\r
+ uint* compare = ®_D[word2 & 7];\r
+ uint res = dest - *compare;\r
+\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_V = VFLAG_SUB_32(*compare, dest, res);\r
+ FLAG_C = CFLAG_SUB_32(*compare, dest, res);\r
+\r
+ if(COND_NE())\r
+ *compare = dest;\r
+ else\r
+ {\r
+ USE_CYCLES(3);\r
+ m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);\r
+ }\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(cas2, 16, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_32();\r
+ uint* compare1 = ®_D[(word2 >> 16) & 7];\r
+ uint ea1 = REG_DA[(word2 >> 28) & 15];\r
+ uint dest1 = m68ki_read_16(ea1);\r
+ uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);\r
+ uint* compare2 = ®_D[word2 & 7];\r
+ uint ea2 = REG_DA[(word2 >> 12) & 15];\r
+ uint dest2 = m68ki_read_16(ea2);\r
+ uint res2;\r
+\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ FLAG_N = NFLAG_16(res1);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res1);\r
+ FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);\r
+ FLAG_C = CFLAG_16(res1);\r
+\r
+ if(COND_EQ())\r
+ {\r
+ res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);\r
+\r
+ FLAG_N = NFLAG_16(res2);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res2);\r
+ FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);\r
+ FLAG_C = CFLAG_16(res2);\r
+\r
+ if(COND_EQ())\r
+ {\r
+ USE_CYCLES(3);\r
+ m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);\r
+ m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);\r
+ return;\r
+ }\r
+ }\r
+ *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;\r
+ *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(cas2, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_32();\r
+ uint* compare1 = ®_D[(word2 >> 16) & 7];\r
+ uint ea1 = REG_DA[(word2 >> 28) & 15];\r
+ uint dest1 = m68ki_read_32(ea1);\r
+ uint res1 = dest1 - *compare1;\r
+ uint* compare2 = ®_D[word2 & 7];\r
+ uint ea2 = REG_DA[(word2 >> 12) & 15];\r
+ uint dest2 = m68ki_read_32(ea2);\r
+ uint res2;\r
+\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ FLAG_N = NFLAG_32(res1);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res1);\r
+ FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);\r
+ FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);\r
+\r
+ if(COND_EQ())\r
+ {\r
+ res2 = dest2 - *compare2;\r
+\r
+ FLAG_N = NFLAG_32(res2);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res2);\r
+ FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);\r
+ FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);\r
+\r
+ if(COND_EQ())\r
+ {\r
+ USE_CYCLES(3);\r
+ m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);\r
+ m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);\r
+ return;\r
+ }\r
+ }\r
+ *compare1 = dest1;\r
+ *compare2 = dest2;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(chk, 16, ., d)\r
+{\r
+ sint src = MAKE_INT_16(DX);\r
+ sint bound = MAKE_INT_16(DY);\r
+\r
+ FLAG_Z = ZFLAG_16(src); /* Undocumented */\r
+ FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
+ FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
+\r
+ if(src >= 0 && src <= bound)\r
+ {\r
+ return;\r
+ }\r
+ FLAG_N = (src < 0)<<7;\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+}\r
+\r
+\r
+M68KMAKE_OP(chk, 16, ., .)\r
+{\r
+ sint src = MAKE_INT_16(DX);\r
+ sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
+\r
+ FLAG_Z = ZFLAG_16(src); /* Undocumented */\r
+ FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
+ FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
+\r
+ if(src >= 0 && src <= bound)\r
+ {\r
+ return;\r
+ }\r
+ FLAG_N = (src < 0)<<7;\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+}\r
+\r
+\r
+M68KMAKE_OP(chk, 32, ., d)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ sint src = MAKE_INT_32(DX);\r
+ sint bound = MAKE_INT_32(DY);\r
+\r
+ FLAG_Z = ZFLAG_32(src); /* Undocumented */\r
+ FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
+ FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
+\r
+ if(src >= 0 && src <= bound)\r
+ {\r
+ return;\r
+ }\r
+ FLAG_N = (src < 0)<<7;\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(chk, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ sint src = MAKE_INT_32(DX);\r
+ sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);\r
+\r
+ FLAG_Z = ZFLAG_32(src); /* Undocumented */\r
+ FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
+ FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
+\r
+ if(src >= 0 && src <= bound)\r
+ {\r
+ return;\r
+ }\r
+ FLAG_N = (src < 0)<<7;\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(chk2cmp2, 8, ., pcdi)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint compare = REG_DA[(word2 >> 12) & 15]&0xff;\r
+ uint ea = EA_PCDI_8();\r
+ uint lower_bound = m68ki_read_pcrel_8(ea);\r
+ uint upper_bound = m68ki_read_pcrel_8(ea + 1);\r
+\r
+ if(!BIT_F(word2))\r
+ FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);\r
+ else\r
+ FLAG_C = compare - lower_bound;\r
+ FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
+ if(COND_CS())\r
+ {\r
+ if(BIT_B(word2))\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+\r
+ FLAG_C = upper_bound - compare;\r
+ if(COND_CS() && BIT_B(word2))\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(chk2cmp2, 8, ., pcix)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint compare = REG_DA[(word2 >> 12) & 15]&0xff;\r
+ uint ea = EA_PCIX_8();\r
+ uint lower_bound = m68ki_read_pcrel_8(ea);\r
+ uint upper_bound = m68ki_read_pcrel_8(ea + 1);\r
+\r
+ if(!BIT_F(word2))\r
+ FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);\r
+ else\r
+ FLAG_C = compare - lower_bound;\r
+ FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
+ if(COND_CS())\r
+ {\r
+ if(BIT_B(word2))\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+\r
+ FLAG_C = upper_bound - compare;\r
+ if(COND_CS() && BIT_B(word2))\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(chk2cmp2, 8, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint compare = REG_DA[(word2 >> 12) & 15]&0xff;\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint lower_bound = m68ki_read_8(ea);\r
+ uint upper_bound = m68ki_read_8(ea + 1);\r
+\r
+ if(!BIT_F(word2))\r
+ FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);\r
+ else\r
+ FLAG_C = compare - lower_bound;\r
+ FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
+ if(COND_CS())\r
+ {\r
+ if(BIT_B(word2))\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+\r
+ FLAG_C = upper_bound - compare;\r
+ if(COND_CS() && BIT_B(word2))\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(chk2cmp2, 16, ., pcdi)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;\r
+ uint ea = EA_PCDI_16();\r
+ uint lower_bound = m68ki_read_pcrel_16(ea);\r
+ uint upper_bound = m68ki_read_pcrel_16(ea + 2);\r
+\r
+ if(!BIT_F(word2))\r
+ FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);\r
+ else\r
+ FLAG_C = compare - lower_bound;\r
+ FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
+ FLAG_C = CFLAG_16(FLAG_C);\r
+ if(COND_CS())\r
+ {\r
+ if(BIT_B(word2))\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+\r
+ if(!BIT_F(word2))\r
+ FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);\r
+ else\r
+ FLAG_C = upper_bound - compare;\r
+ FLAG_C = CFLAG_16(FLAG_C);\r
+ if(COND_CS() && BIT_B(word2))\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(chk2cmp2, 16, ., pcix)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;\r
+ uint ea = EA_PCIX_16();\r
+ uint lower_bound = m68ki_read_pcrel_16(ea);\r
+ uint upper_bound = m68ki_read_pcrel_16(ea + 2);\r
+\r
+ if(!BIT_F(word2))\r
+ FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);\r
+ else\r
+ FLAG_C = compare - lower_bound;\r
+ FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
+ FLAG_C = CFLAG_16(FLAG_C);\r
+ if(COND_CS())\r
+ {\r
+ if(BIT_B(word2))\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+\r
+ if(!BIT_F(word2))\r
+ FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);\r
+ else\r
+ FLAG_C = upper_bound - compare;\r
+ FLAG_C = CFLAG_16(FLAG_C);\r
+ if(COND_CS() && BIT_B(word2))\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(chk2cmp2, 16, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint lower_bound = m68ki_read_16(ea);\r
+ uint upper_bound = m68ki_read_16(ea + 2);\r
+\r
+ if(!BIT_F(word2))\r
+ FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);\r
+ else\r
+ FLAG_C = compare - lower_bound;\r
+\r
+ FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
+ FLAG_C = CFLAG_16(FLAG_C);\r
+ if(COND_CS())\r
+ {\r
+ if(BIT_B(word2))\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+ if(!BIT_F(word2))\r
+ FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);\r
+ else\r
+ FLAG_C = upper_bound - compare;\r
+\r
+ FLAG_C = CFLAG_16(FLAG_C);\r
+ if(COND_CS() && BIT_B(word2))\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(chk2cmp2, 32, ., pcdi)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint compare = REG_DA[(word2 >> 12) & 15];\r
+ uint ea = EA_PCDI_32();\r
+ uint lower_bound = m68ki_read_pcrel_32(ea);\r
+ uint upper_bound = m68ki_read_pcrel_32(ea + 4);\r
+\r
+ FLAG_C = compare - lower_bound;\r
+ FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
+ FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);\r
+ if(COND_CS())\r
+ {\r
+ if(BIT_B(word2))\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+\r
+ FLAG_C = upper_bound - compare;\r
+ FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);\r
+ if(COND_CS() && BIT_B(word2))\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(chk2cmp2, 32, ., pcix)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint compare = REG_DA[(word2 >> 12) & 15];\r
+ uint ea = EA_PCIX_32();\r
+ uint lower_bound = m68ki_read_pcrel_32(ea);\r
+ uint upper_bound = m68ki_read_pcrel_32(ea + 4);\r
+\r
+ FLAG_C = compare - lower_bound;\r
+ FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
+ FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);\r
+ if(COND_CS())\r
+ {\r
+ if(BIT_B(word2))\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+\r
+ FLAG_C = upper_bound - compare;\r
+ FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);\r
+ if(COND_CS() && BIT_B(word2))\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(chk2cmp2, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint compare = REG_DA[(word2 >> 12) & 15];\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint lower_bound = m68ki_read_32(ea);\r
+ uint upper_bound = m68ki_read_32(ea + 4);\r
+\r
+ FLAG_C = compare - lower_bound;\r
+ FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
+ FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);\r
+ if(COND_CS())\r
+ {\r
+ if(BIT_B(word2))\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+\r
+ FLAG_C = upper_bound - compare;\r
+ FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);\r
+ if(COND_CS() && BIT_B(word2))\r
+ m68ki_exception_trap(EXCEPTION_CHK);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(clr, 8, ., d)\r
+{\r
+ DY &= 0xffffff00;\r
+\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_Z = ZFLAG_SET;\r
+}\r
+\r
+\r
+M68KMAKE_OP(clr, 8, ., .)\r
+{\r
+ m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);\r
+\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_Z = ZFLAG_SET;\r
+}\r
+\r
+\r
+M68KMAKE_OP(clr, 16, ., d)\r
+{\r
+ DY &= 0xffff0000;\r
+\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_Z = ZFLAG_SET;\r
+}\r
+\r
+\r
+M68KMAKE_OP(clr, 16, ., .)\r
+{\r
+ m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);\r
+\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_Z = ZFLAG_SET;\r
+}\r
+\r
+\r
+M68KMAKE_OP(clr, 32, ., d)\r
+{\r
+ DY = 0;\r
+\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_Z = ZFLAG_SET;\r
+}\r
+\r
+\r
+M68KMAKE_OP(clr, 32, ., .)\r
+{\r
+ m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);\r
+\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_Z = ZFLAG_SET;\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmp, 8, ., d)\r
+{\r
+ uint src = MASK_OUT_ABOVE_8(DY);\r
+ uint dst = MASK_OUT_ABOVE_8(DX);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+ FLAG_C = CFLAG_8(res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmp, 8, ., .)\r
+{\r
+ uint src = M68KMAKE_GET_OPER_AY_8;\r
+ uint dst = MASK_OUT_ABOVE_8(DX);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+ FLAG_C = CFLAG_8(res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmp, 16, ., d)\r
+{\r
+ uint src = MASK_OUT_ABOVE_16(DY);\r
+ uint dst = MASK_OUT_ABOVE_16(DX);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+ FLAG_V = VFLAG_SUB_16(src, dst, res);\r
+ FLAG_C = CFLAG_16(res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmp, 16, ., a)\r
+{\r
+ uint src = MASK_OUT_ABOVE_16(AY);\r
+ uint dst = MASK_OUT_ABOVE_16(DX);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+ FLAG_V = VFLAG_SUB_16(src, dst, res);\r
+ FLAG_C = CFLAG_16(res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmp, 16, ., .)\r
+{\r
+ uint src = M68KMAKE_GET_OPER_AY_16;\r
+ uint dst = MASK_OUT_ABOVE_16(DX);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+ FLAG_V = VFLAG_SUB_16(src, dst, res);\r
+ FLAG_C = CFLAG_16(res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmp, 32, ., d)\r
+{\r
+ uint src = DY;\r
+ uint dst = DX;\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+ FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmp, 32, ., a)\r
+{\r
+ uint src = AY;\r
+ uint dst = DX;\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+ FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmp, 32, ., .)\r
+{\r
+ uint src = M68KMAKE_GET_OPER_AY_32;\r
+ uint dst = DX;\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+ FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpa, 16, ., d)\r
+{\r
+ uint src = MAKE_INT_16(DY);\r
+ uint dst = AX;\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+ FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpa, 16, ., a)\r
+{\r
+ uint src = MAKE_INT_16(AY);\r
+ uint dst = AX;\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+ FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpa, 16, ., .)\r
+{\r
+ uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
+ uint dst = AX;\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+ FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpa, 32, ., d)\r
+{\r
+ uint src = DY;\r
+ uint dst = AX;\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+ FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpa, 32, ., a)\r
+{\r
+ uint src = AY;\r
+ uint dst = AX;\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+ FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpa, 32, ., .)\r
+{\r
+ uint src = M68KMAKE_GET_OPER_AY_32;\r
+ uint dst = AX;\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+ FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpi, 8, ., d)\r
+{\r
+ uint src = OPER_I_8();\r
+ uint dst = MASK_OUT_ABOVE_8(DY);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+ FLAG_C = CFLAG_8(res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpi, 8, ., .)\r
+{\r
+ uint src = OPER_I_8();\r
+ uint dst = M68KMAKE_GET_OPER_AY_8;\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+ FLAG_C = CFLAG_8(res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpi, 8, ., pcdi)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint src = OPER_I_8();\r
+ uint dst = OPER_PCDI_8();\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+ FLAG_C = CFLAG_8(res);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpi, 8, ., pcix)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint src = OPER_I_8();\r
+ uint dst = OPER_PCIX_8();\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+ FLAG_C = CFLAG_8(res);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpi, 16, ., d)\r
+{\r
+ uint src = OPER_I_16();\r
+ uint dst = MASK_OUT_ABOVE_16(DY);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+ FLAG_V = VFLAG_SUB_16(src, dst, res);\r
+ FLAG_C = CFLAG_16(res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpi, 16, ., .)\r
+{\r
+ uint src = OPER_I_16();\r
+ uint dst = M68KMAKE_GET_OPER_AY_16;\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+ FLAG_V = VFLAG_SUB_16(src, dst, res);\r
+ FLAG_C = CFLAG_16(res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpi, 16, ., pcdi)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint src = OPER_I_16();\r
+ uint dst = OPER_PCDI_16();\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+ FLAG_V = VFLAG_SUB_16(src, dst, res);\r
+ FLAG_C = CFLAG_16(res);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpi, 16, ., pcix)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint src = OPER_I_16();\r
+ uint dst = OPER_PCIX_16();\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+ FLAG_V = VFLAG_SUB_16(src, dst, res);\r
+ FLAG_C = CFLAG_16(res);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpi, 32, ., d)\r
+{\r
+ uint src = OPER_I_32();\r
+ uint dst = DY;\r
+ uint res = dst - src;\r
+\r
+ m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+ FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpi, 32, ., .)\r
+{\r
+ uint src = OPER_I_32();\r
+ uint dst = M68KMAKE_GET_OPER_AY_32;\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+ FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpi, 32, ., pcdi)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint src = OPER_I_32();\r
+ uint dst = OPER_PCDI_32();\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+ FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpi, 32, ., pcix)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint src = OPER_I_32();\r
+ uint dst = OPER_PCIX_32();\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+ FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpm, 8, ., ax7)\r
+{\r
+ uint src = OPER_AY_PI_8();\r
+ uint dst = OPER_A7_PI_8();\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+ FLAG_C = CFLAG_8(res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpm, 8, ., ay7)\r
+{\r
+ uint src = OPER_A7_PI_8();\r
+ uint dst = OPER_AX_PI_8();\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+ FLAG_C = CFLAG_8(res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpm, 8, ., axy7)\r
+{\r
+ uint src = OPER_A7_PI_8();\r
+ uint dst = OPER_A7_PI_8();\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+ FLAG_C = CFLAG_8(res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpm, 8, ., .)\r
+{\r
+ uint src = OPER_AY_PI_8();\r
+ uint dst = OPER_AX_PI_8();\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+ FLAG_C = CFLAG_8(res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpm, 16, ., .)\r
+{\r
+ uint src = OPER_AY_PI_16();\r
+ uint dst = OPER_AX_PI_16();\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+ FLAG_V = VFLAG_SUB_16(src, dst, res);\r
+ FLAG_C = CFLAG_16(res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cmpm, 32, ., .)\r
+{\r
+ uint src = OPER_AY_PI_32();\r
+ uint dst = OPER_AX_PI_32();\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+ FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(cpbcc, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
+ m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
+ m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
+ return;\r
+ }\r
+ m68ki_exception_1111();\r
+}\r
+\r
+\r
+M68KMAKE_OP(cpdbcc, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
+ m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
+ m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
+ return;\r
+ }\r
+ m68ki_exception_1111();\r
+}\r
+\r
+\r
+M68KMAKE_OP(cpgen, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
+ m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
+ m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
+ return;\r
+ }\r
+ m68ki_exception_1111();\r
+}\r
+\r
+\r
+M68KMAKE_OP(cpscc, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
+ m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
+ m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
+ return;\r
+ }\r
+ m68ki_exception_1111();\r
+}\r
+\r
+\r
+M68KMAKE_OP(cptrapcc, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
+ m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
+ m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
+ return;\r
+ }\r
+ m68ki_exception_1111();\r
+}\r
+\r
+\r
+M68KMAKE_OP(dbt, 16, ., .)\r
+{\r
+ REG_PC += 2;\r
+}\r
+\r
+\r
+M68KMAKE_OP(dbf, 16, ., .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint res = MASK_OUT_ABOVE_16(*r_dst - 1);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+ if(res != 0xffff)\r
+ {\r
+ uint offset = OPER_I_16();\r
+ REG_PC -= 2;\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_branch_16(offset);\r
+ USE_CYCLES(CYC_DBCC_F_NOEXP);\r
+ return;\r
+ }\r
+ REG_PC += 2;\r
+ USE_CYCLES(CYC_DBCC_F_EXP);\r
+}\r
+\r
+\r
+M68KMAKE_OP(dbcc, 16, ., .)\r
+{\r
+ if(M68KMAKE_NOT_CC)\r
+ {\r
+ uint* r_dst = &DY;\r
+ uint res = MASK_OUT_ABOVE_16(*r_dst - 1);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+ if(res != 0xffff)\r
+ {\r
+ uint offset = OPER_I_16();\r
+ REG_PC -= 2;\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_branch_16(offset);\r
+ USE_CYCLES(CYC_DBCC_F_NOEXP);\r
+ return;\r
+ }\r
+ REG_PC += 2;\r
+ USE_CYCLES(CYC_DBCC_F_EXP);\r
+ return;\r
+ }\r
+ REG_PC += 2;\r
+}\r
+\r
+\r
+M68KMAKE_OP(divs, 16, ., d)\r
+{\r
+ uint* r_dst = &DX;\r
+ sint src = MAKE_INT_16(DY);\r
+ sint quotient;\r
+ sint remainder;\r
+\r
+ if(src != 0)\r
+ {\r
+ if((uint32)*r_dst == 0x80000000 && src == -1)\r
+ {\r
+ FLAG_Z = 0;\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ *r_dst = 0;\r
+ return;\r
+ }\r
+\r
+ quotient = MAKE_INT_32(*r_dst) / src;\r
+ remainder = MAKE_INT_32(*r_dst) % src;\r
+\r
+ if(quotient == MAKE_INT_16(quotient))\r
+ {\r
+ FLAG_Z = quotient;\r
+ FLAG_N = NFLAG_16(quotient);\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
+ return;\r
+ }\r
+ FLAG_V = VFLAG_SET;\r
+ return;\r
+ }\r
+ m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
+}\r
+\r
+\r
+M68KMAKE_OP(divs, 16, ., .)\r
+{\r
+ uint* r_dst = &DX;\r
+ sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
+ sint quotient;\r
+ sint remainder;\r
+\r
+ if(src != 0)\r
+ {\r
+ if((uint32)*r_dst == 0x80000000 && src == -1)\r
+ {\r
+ FLAG_Z = 0;\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ *r_dst = 0;\r
+ return;\r
+ }\r
+\r
+ quotient = MAKE_INT_32(*r_dst) / src;\r
+ remainder = MAKE_INT_32(*r_dst) % src;\r
+\r
+ if(quotient == MAKE_INT_16(quotient))\r
+ {\r
+ FLAG_Z = quotient;\r
+ FLAG_N = NFLAG_16(quotient);\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
+ return;\r
+ }\r
+ FLAG_V = VFLAG_SET;\r
+ return;\r
+ }\r
+ m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
+}\r
+\r
+\r
+M68KMAKE_OP(divu, 16, ., d)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = MASK_OUT_ABOVE_16(DY);\r
+\r
+ if(src != 0)\r
+ {\r
+ uint quotient = *r_dst / src;\r
+ uint remainder = *r_dst % src;\r
+\r
+ if(quotient < 0x10000)\r
+ {\r
+ FLAG_Z = quotient;\r
+ FLAG_N = NFLAG_16(quotient);\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
+ return;\r
+ }\r
+ FLAG_V = VFLAG_SET;\r
+ return;\r
+ }\r
+ m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
+}\r
+\r
+\r
+M68KMAKE_OP(divu, 16, ., .)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = M68KMAKE_GET_OPER_AY_16;\r
+\r
+ if(src != 0)\r
+ {\r
+ uint quotient = *r_dst / src;\r
+ uint remainder = *r_dst % src;\r
+\r
+ if(quotient < 0x10000)\r
+ {\r
+ FLAG_Z = quotient;\r
+ FLAG_N = NFLAG_16(quotient);\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
+ return;\r
+ }\r
+ FLAG_V = VFLAG_SET;\r
+ return;\r
+ }\r
+ m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
+}\r
+\r
+\r
+M68KMAKE_OP(divl, 32, ., d)\r
+{\r
+#if M68K_USE_64_BIT\r
+\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint64 divisor = DY;\r
+ uint64 dividend = 0;\r
+ uint64 quotient = 0;\r
+ uint64 remainder = 0;\r
+\r
+ if(divisor != 0)\r
+ {\r
+ if(BIT_A(word2)) /* 64 bit */\r
+ {\r
+ dividend = REG_D[word2 & 7];\r
+ dividend <<= 32;\r
+ dividend |= REG_D[(word2 >> 12) & 7];\r
+\r
+ if(BIT_B(word2)) /* signed */\r
+ {\r
+ quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));\r
+ remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));\r
+ if((sint64)quotient != (sint64)((sint32)quotient))\r
+ {\r
+ FLAG_V = VFLAG_SET;\r
+ return;\r
+ }\r
+ }\r
+ else /* unsigned */\r
+ {\r
+ quotient = dividend / divisor;\r
+ if(quotient > 0xffffffff)\r
+ {\r
+ FLAG_V = VFLAG_SET;\r
+ return;\r
+ }\r
+ remainder = dividend % divisor;\r
+ }\r
+ }\r
+ else /* 32 bit */\r
+ {\r
+ dividend = REG_D[(word2 >> 12) & 7];\r
+ if(BIT_B(word2)) /* signed */\r
+ {\r
+ quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));\r
+ remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));\r
+ }\r
+ else /* unsigned */\r
+ {\r
+ quotient = dividend / divisor;\r
+ remainder = dividend % divisor;\r
+ }\r
+ }\r
+\r
+ REG_D[word2 & 7] = remainder;\r
+ REG_D[(word2 >> 12) & 7] = quotient;\r
+\r
+ FLAG_N = NFLAG_32(quotient);\r
+ FLAG_Z = quotient;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+ m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+\r
+#else\r
+\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint divisor = DY;\r
+ uint dividend_hi = REG_D[word2 & 7];\r
+ uint dividend_lo = REG_D[(word2 >> 12) & 7];\r
+ uint quotient = 0;\r
+ uint remainder = 0;\r
+ uint dividend_neg = 0;\r
+ uint divisor_neg = 0;\r
+ sint i;\r
+ uint overflow;\r
+\r
+ if(divisor != 0)\r
+ {\r
+ /* quad / long : long quotient, long remainder */\r
+ if(BIT_A(word2))\r
+ {\r
+ if(BIT_B(word2)) /* signed */\r
+ {\r
+ /* special case in signed divide */\r
+ if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
+ {\r
+ REG_D[word2 & 7] = 0;\r
+ REG_D[(word2 >> 12) & 7] = 0x80000000;\r
+\r
+ FLAG_N = NFLAG_SET;\r
+ FLAG_Z = ZFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+ if(GET_MSB_32(dividend_hi))\r
+ {\r
+ dividend_neg = 1;\r
+ dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));\r
+ dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);\r
+ }\r
+ if(GET_MSB_32(divisor))\r
+ {\r
+ divisor_neg = 1;\r
+ divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);\r
+\r
+ }\r
+ }\r
+\r
+ /* if the upper long is greater than the divisor, we're overflowing. */\r
+ if(dividend_hi >= divisor)\r
+ {\r
+ FLAG_V = VFLAG_SET;\r
+ return;\r
+ }\r
+\r
+ for(i = 31; i >= 0; i--)\r
+ {\r
+ quotient <<= 1;\r
+ remainder = (remainder << 1) + ((dividend_hi >> i) & 1);\r
+ if(remainder >= divisor)\r
+ {\r
+ remainder -= divisor;\r
+ quotient++;\r
+ }\r
+ }\r
+ for(i = 31; i >= 0; i--)\r
+ {\r
+ quotient <<= 1;\r
+ overflow = GET_MSB_32(remainder);\r
+ remainder = (remainder << 1) + ((dividend_lo >> i) & 1);\r
+ if(remainder >= divisor || overflow)\r
+ {\r
+ remainder -= divisor;\r
+ quotient++;\r
+ }\r
+ }\r
+\r
+ if(BIT_B(word2)) /* signed */\r
+ {\r
+ if(quotient > 0x7fffffff)\r
+ {\r
+ FLAG_V = VFLAG_SET;\r
+ return;\r
+ }\r
+ if(dividend_neg)\r
+ {\r
+ remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);\r
+ quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
+ }\r
+ if(divisor_neg)\r
+ quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
+ }\r
+\r
+ REG_D[word2 & 7] = remainder;\r
+ REG_D[(word2 >> 12) & 7] = quotient;\r
+\r
+ FLAG_N = NFLAG_32(quotient);\r
+ FLAG_Z = quotient;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ /* long / long: long quotient, maybe long remainder */\r
+ if(BIT_B(word2)) /* signed */\r
+ {\r
+ /* Special case in divide */\r
+ if(dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
+ {\r
+ FLAG_N = NFLAG_SET;\r
+ FLAG_Z = ZFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ REG_D[(word2 >> 12) & 7] = 0x80000000;\r
+ REG_D[word2 & 7] = 0;\r
+ return;\r
+ }\r
+ REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);\r
+ quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);\r
+ }\r
+ else\r
+ {\r
+ REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);\r
+ quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);\r
+ }\r
+\r
+ FLAG_N = NFLAG_32(quotient);\r
+ FLAG_Z = quotient;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+ m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+\r
+#endif\r
+}\r
+\r
+\r
+M68KMAKE_OP(divl, 32, ., .)\r
+{\r
+#if M68K_USE_64_BIT\r
+\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint64 divisor = M68KMAKE_GET_OPER_AY_32;\r
+ uint64 dividend = 0;\r
+ uint64 quotient = 0;\r
+ uint64 remainder = 0;\r
+\r
+ if(divisor != 0)\r
+ {\r
+ if(BIT_A(word2)) /* 64 bit */\r
+ {\r
+ dividend = REG_D[word2 & 7];\r
+ dividend <<= 32;\r
+ dividend |= REG_D[(word2 >> 12) & 7];\r
+\r
+ if(BIT_B(word2)) /* signed */\r
+ {\r
+ quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));\r
+ remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));\r
+ if((sint64)quotient != (sint64)((sint32)quotient))\r
+ {\r
+ FLAG_V = VFLAG_SET;\r
+ return;\r
+ }\r
+ }\r
+ else /* unsigned */\r
+ {\r
+ quotient = dividend / divisor;\r
+ if(quotient > 0xffffffff)\r
+ {\r
+ FLAG_V = VFLAG_SET;\r
+ return;\r
+ }\r
+ remainder = dividend % divisor;\r
+ }\r
+ }\r
+ else /* 32 bit */\r
+ {\r
+ dividend = REG_D[(word2 >> 12) & 7];\r
+ if(BIT_B(word2)) /* signed */\r
+ {\r
+ quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));\r
+ remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));\r
+ }\r
+ else /* unsigned */\r
+ {\r
+ quotient = dividend / divisor;\r
+ remainder = dividend % divisor;\r
+ }\r
+ }\r
+\r
+ REG_D[word2 & 7] = remainder;\r
+ REG_D[(word2 >> 12) & 7] = quotient;\r
+\r
+ FLAG_N = NFLAG_32(quotient);\r
+ FLAG_Z = quotient;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+ m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+\r
+#else\r
+\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint divisor = M68KMAKE_GET_OPER_AY_32;\r
+ uint dividend_hi = REG_D[word2 & 7];\r
+ uint dividend_lo = REG_D[(word2 >> 12) & 7];\r
+ uint quotient = 0;\r
+ uint remainder = 0;\r
+ uint dividend_neg = 0;\r
+ uint divisor_neg = 0;\r
+ sint i;\r
+ uint overflow;\r
+\r
+ if(divisor != 0)\r
+ {\r
+ /* quad / long : long quotient, long remainder */\r
+ if(BIT_A(word2))\r
+ {\r
+ if(BIT_B(word2)) /* signed */\r
+ {\r
+ /* special case in signed divide */\r
+ if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
+ {\r
+ REG_D[word2 & 7] = 0;\r
+ REG_D[(word2 >> 12) & 7] = 0x80000000;\r
+\r
+ FLAG_N = NFLAG_SET;\r
+ FLAG_Z = ZFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+ if(GET_MSB_32(dividend_hi))\r
+ {\r
+ dividend_neg = 1;\r
+ dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));\r
+ dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);\r
+ }\r
+ if(GET_MSB_32(divisor))\r
+ {\r
+ divisor_neg = 1;\r
+ divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);\r
+\r
+ }\r
+ }\r
+\r
+ /* if the upper long is greater than the divisor, we're overflowing. */\r
+ if(dividend_hi >= divisor)\r
+ {\r
+ FLAG_V = VFLAG_SET;\r
+ return;\r
+ }\r
+\r
+ for(i = 31; i >= 0; i--)\r
+ {\r
+ quotient <<= 1;\r
+ remainder = (remainder << 1) + ((dividend_hi >> i) & 1);\r
+ if(remainder >= divisor)\r
+ {\r
+ remainder -= divisor;\r
+ quotient++;\r
+ }\r
+ }\r
+ for(i = 31; i >= 0; i--)\r
+ {\r
+ quotient <<= 1;\r
+ overflow = GET_MSB_32(remainder);\r
+ remainder = (remainder << 1) + ((dividend_lo >> i) & 1);\r
+ if(remainder >= divisor || overflow)\r
+ {\r
+ remainder -= divisor;\r
+ quotient++;\r
+ }\r
+ }\r
+\r
+ if(BIT_B(word2)) /* signed */\r
+ {\r
+ if(quotient > 0x7fffffff)\r
+ {\r
+ FLAG_V = VFLAG_SET;\r
+ return;\r
+ }\r
+ if(dividend_neg)\r
+ {\r
+ remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);\r
+ quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
+ }\r
+ if(divisor_neg)\r
+ quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
+ }\r
+\r
+ REG_D[word2 & 7] = remainder;\r
+ REG_D[(word2 >> 12) & 7] = quotient;\r
+\r
+ FLAG_N = NFLAG_32(quotient);\r
+ FLAG_Z = quotient;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ /* long / long: long quotient, maybe long remainder */\r
+ if(BIT_B(word2)) /* signed */\r
+ {\r
+ /* Special case in divide */\r
+ if(dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
+ {\r
+ FLAG_N = NFLAG_SET;\r
+ FLAG_Z = ZFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ REG_D[(word2 >> 12) & 7] = 0x80000000;\r
+ REG_D[word2 & 7] = 0;\r
+ return;\r
+ }\r
+ REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);\r
+ quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);\r
+ }\r
+ else\r
+ {\r
+ REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);\r
+ quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);\r
+ }\r
+\r
+ FLAG_N = NFLAG_32(quotient);\r
+ FLAG_Z = quotient;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+ m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+\r
+#endif\r
+}\r
+\r
+\r
+M68KMAKE_OP(eor, 8, ., d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(eor, 8, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(eor, 16, ., d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(eor, 16, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(eor, 32, ., d)\r
+{\r
+ uint res = DY ^= DX;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(eor, 32, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint res = DX ^ m68ki_read_32(ea);\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(eori, 8, ., d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(eori, 8, ., .)\r
+{\r
+ uint src = OPER_I_8();\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint res = src ^ m68ki_read_8(ea);\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(eori, 16, ., d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(eori, 16, ., .)\r
+{\r
+ uint src = OPER_I_16();\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint res = src ^ m68ki_read_16(ea);\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(eori, 32, ., d)\r
+{\r
+ uint res = DY ^= OPER_I_32();\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(eori, 32, ., .)\r
+{\r
+ uint src = OPER_I_32();\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint res = src ^ m68ki_read_32(ea);\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(eori, 16, toc, .)\r
+{\r
+ m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());\r
+}\r
+\r
+\r
+M68KMAKE_OP(eori, 16, tos, .)\r
+{\r
+ if(FLAG_S)\r
+ {\r
+ uint src = OPER_I_16();\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_set_sr(m68ki_get_sr() ^ src);\r
+ return;\r
+ }\r
+ m68ki_exception_privilege_violation();\r
+}\r
+\r
+\r
+M68KMAKE_OP(exg, 32, dd, .)\r
+{\r
+ uint* reg_a = &DX;\r
+ uint* reg_b = &DY;\r
+ uint tmp = *reg_a;\r
+ *reg_a = *reg_b;\r
+ *reg_b = tmp;\r
+}\r
+\r
+\r
+M68KMAKE_OP(exg, 32, aa, .)\r
+{\r
+ uint* reg_a = &AX;\r
+ uint* reg_b = &AY;\r
+ uint tmp = *reg_a;\r
+ *reg_a = *reg_b;\r
+ *reg_b = tmp;\r
+}\r
+\r
+\r
+M68KMAKE_OP(exg, 32, da, .)\r
+{\r
+ uint* reg_a = &DX;\r
+ uint* reg_b = &AY;\r
+ uint tmp = *reg_a;\r
+ *reg_a = *reg_b;\r
+ *reg_b = tmp;\r
+}\r
+\r
+\r
+M68KMAKE_OP(ext, 16, ., .)\r
+{\r
+ uint* r_dst = &DY;\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);\r
+\r
+ FLAG_N = NFLAG_16(*r_dst);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(ext, 32, ., .)\r
+{\r
+ uint* r_dst = &DY;\r
+\r
+ *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);\r
+\r
+ FLAG_N = NFLAG_32(*r_dst);\r
+ FLAG_Z = *r_dst;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(extb, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint* r_dst = &DY;\r
+\r
+ *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);\r
+\r
+ FLAG_N = NFLAG_32(*r_dst);\r
+ FLAG_Z = *r_dst;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(illegal, 0, ., .)\r
+{\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+M68KMAKE_OP(jmp, 32, ., .)\r
+{\r
+ m68ki_jump(M68KMAKE_GET_EA_AY_32);\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ if(REG_PC == REG_PPC)\r
+ USE_ALL_CYCLES();\r
+}\r
+\r
+\r
+M68KMAKE_OP(jsr, 32, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_push_32(MAKE_INT_24(REG_PC)); // notaz: Cyclone can't handle 32bit PC and I neet to debug it\r
+ m68ki_jump(ea);\r
+}\r
+\r
+\r
+M68KMAKE_OP(lea, 32, ., .)\r
+{\r
+ AX = M68KMAKE_GET_EA_AY_32;\r
+}\r
+\r
+\r
+M68KMAKE_OP(link, 16, ., a7)\r
+{\r
+ REG_A[7] -= 4;\r
+ m68ki_write_32(REG_A[7], REG_A[7]);\r
+ REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));\r
+}\r
+\r
+\r
+M68KMAKE_OP(link, 16, ., .)\r
+{\r
+ uint* r_dst = &AY;\r
+\r
+ m68ki_push_32(*r_dst);\r
+ *r_dst = REG_A[7];\r
+ REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));\r
+}\r
+\r
+\r
+M68KMAKE_OP(link, 32, ., a7)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ REG_A[7] -= 4;\r
+ m68ki_write_32(REG_A[7], REG_A[7]);\r
+ REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(link, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint* r_dst = &AY;\r
+\r
+ m68ki_push_32(*r_dst);\r
+ *r_dst = REG_A[7];\r
+ REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(lsr, 8, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = src >> shift;\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = res;\r
+ FLAG_X = FLAG_C = src << (9-shift);\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(lsr, 16, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = src >> shift;\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = res;\r
+ FLAG_X = FLAG_C = src << (9-shift);\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(lsr, 32, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = *r_dst;\r
+ uint res = src >> shift;\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = res;\r
+ FLAG_X = FLAG_C = src << (9-shift);\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(lsr, 8, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = DX & 0x3f;\r
+ uint src = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = src >> shift;\r
+\r
+ if(shift != 0)\r
+ {\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ if(shift <= 8)\r
+ {\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+ FLAG_X = FLAG_C = src << (9-shift);\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ *r_dst &= 0xffffff00;\r
+ FLAG_X = XFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = ZFLAG_SET;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_8(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(lsr, 16, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = DX & 0x3f;\r
+ uint src = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = src >> shift;\r
+\r
+ if(shift != 0)\r
+ {\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ if(shift <= 16)\r
+ {\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+ FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ *r_dst &= 0xffff0000;\r
+ FLAG_X = XFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = ZFLAG_SET;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_16(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(lsr, 32, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = DX & 0x3f;\r
+ uint src = *r_dst;\r
+ uint res = src >> shift;\r
+\r
+ if(shift != 0)\r
+ {\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ if(shift < 32)\r
+ {\r
+ *r_dst = res;\r
+ FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ *r_dst = 0;\r
+ FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = ZFLAG_SET;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_32(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(lsr, 16, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint src = m68ki_read_16(ea);\r
+ uint res = src >> 1;\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = res;\r
+ FLAG_C = FLAG_X = src << 8;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(lsl, 8, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = MASK_OUT_ABOVE_8(src << shift);\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_X = FLAG_C = src << shift;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(lsl, 16, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = MASK_OUT_ABOVE_16(src << shift);\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_X = FLAG_C = src >> (8-shift);\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(lsl, 32, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = *r_dst;\r
+ uint res = MASK_OUT_ABOVE_32(src << shift);\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_X = FLAG_C = src >> (24-shift);\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(lsl, 8, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = DX & 0x3f;\r
+ uint src = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = MASK_OUT_ABOVE_8(src << shift);\r
+\r
+ if(shift != 0)\r
+ {\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ if(shift <= 8)\r
+ {\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+ FLAG_X = FLAG_C = src << shift;\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ *r_dst &= 0xffffff00;\r
+ FLAG_X = XFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = ZFLAG_SET;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_8(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(lsl, 16, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = DX & 0x3f;\r
+ uint src = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = MASK_OUT_ABOVE_16(src << shift);\r
+\r
+ if(shift != 0)\r
+ {\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ if(shift <= 16)\r
+ {\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+ FLAG_X = FLAG_C = (src << shift) >> 8;\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ *r_dst &= 0xffff0000;\r
+ FLAG_X = XFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = ZFLAG_SET;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_16(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(lsl, 32, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = DX & 0x3f;\r
+ uint src = *r_dst;\r
+ uint res = MASK_OUT_ABOVE_32(src << shift);\r
+\r
+ if(shift != 0)\r
+ {\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ if(shift < 32)\r
+ {\r
+ *r_dst = res;\r
+ FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ *r_dst = 0;\r
+ FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;\r
+ FLAG_N = NFLAG_CLEAR;\r
+ FLAG_Z = ZFLAG_SET;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_32(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(lsl, 16, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint src = m68ki_read_16(ea);\r
+ uint res = MASK_OUT_ABOVE_16(src << 1);\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_X = FLAG_C = src >> 7;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, d, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_8(DY);\r
+ uint* r_dst = &DX;\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, d, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_8;\r
+ uint* r_dst = &DX;\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, ai, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_8(DY);\r
+ uint ea = EA_AX_AI_8();\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, ai, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_8;\r
+ uint ea = EA_AX_AI_8();\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, pi7, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_8(DY);\r
+ uint ea = EA_A7_PI_8();\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, pi, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_8(DY);\r
+ uint ea = EA_AX_PI_8();\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, pi7, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_8;\r
+ uint ea = EA_A7_PI_8();\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, pi, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_8;\r
+ uint ea = EA_AX_PI_8();\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, pd7, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_8(DY);\r
+ uint ea = EA_A7_PD_8();\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, pd, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_8(DY);\r
+ uint ea = EA_AX_PD_8();\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, pd7, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_8;\r
+ uint ea = EA_A7_PD_8();\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, pd, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_8;\r
+ uint ea = EA_AX_PD_8();\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, di, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_8(DY);\r
+ uint ea = EA_AX_DI_8();\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, di, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_8;\r
+ uint ea = EA_AX_DI_8();\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, ix, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_8(DY);\r
+ uint ea = EA_AX_IX_8();\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, ix, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_8;\r
+ uint ea = EA_AX_IX_8();\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, aw, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_8(DY);\r
+ uint ea = EA_AW_8();\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, aw, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_8;\r
+ uint ea = EA_AW_8();\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, al, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_8(DY);\r
+ uint ea = EA_AL_8();\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 8, al, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_8;\r
+ uint ea = EA_AL_8();\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, d, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(DY);\r
+ uint* r_dst = &DX;\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, d, a)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(AY);\r
+ uint* r_dst = &DX;\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, d, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_16;\r
+ uint* r_dst = &DX;\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, ai, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(DY);\r
+ uint ea = EA_AX_AI_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, ai, a)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(AY);\r
+ uint ea = EA_AX_AI_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, ai, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_16;\r
+ uint ea = EA_AX_AI_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, pi, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(DY);\r
+ uint ea = EA_AX_PI_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, pi, a)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(AY);\r
+ uint ea = EA_AX_PI_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, pi, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_16;\r
+ uint ea = EA_AX_PI_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, pd, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(DY);\r
+ uint ea = EA_AX_PD_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, pd, a)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(AY);\r
+ uint ea = EA_AX_PD_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, pd, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_16;\r
+ uint ea = EA_AX_PD_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, di, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(DY);\r
+ uint ea = EA_AX_DI_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, di, a)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(AY);\r
+ uint ea = EA_AX_DI_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, di, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_16;\r
+ uint ea = EA_AX_DI_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, ix, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(DY);\r
+ uint ea = EA_AX_IX_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, ix, a)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(AY);\r
+ uint ea = EA_AX_IX_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, ix, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_16;\r
+ uint ea = EA_AX_IX_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, aw, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(DY);\r
+ uint ea = EA_AW_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, aw, a)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(AY);\r
+ uint ea = EA_AW_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, aw, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_16;\r
+ uint ea = EA_AW_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, al, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(DY);\r
+ uint ea = EA_AL_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, al, a)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(AY);\r
+ uint ea = EA_AL_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, al, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_16;\r
+ uint ea = EA_AL_16();\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, d, d)\r
+{\r
+ uint res = DY;\r
+ uint* r_dst = &DX;\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, d, a)\r
+{\r
+ uint res = AY;\r
+ uint* r_dst = &DX;\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, d, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_32;\r
+ uint* r_dst = &DX;\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, ai, d)\r
+{\r
+ uint res = DY;\r
+ uint ea = EA_AX_AI_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, ai, a)\r
+{\r
+ uint res = AY;\r
+ uint ea = EA_AX_AI_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, ai, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_32;\r
+ uint ea = EA_AX_AI_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, pi, d)\r
+{\r
+ uint res = DY;\r
+ uint ea = EA_AX_PI_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, pi, a)\r
+{\r
+ uint res = AY;\r
+ uint ea = EA_AX_PI_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, pi, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_32;\r
+ uint ea = EA_AX_PI_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, pd, d)\r
+{\r
+ uint res = DY;\r
+ uint ea = EA_AX_PD_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, pd, a)\r
+{\r
+ uint res = AY;\r
+ uint ea = EA_AX_PD_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, pd, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_32;\r
+ uint ea = EA_AX_PD_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, di, d)\r
+{\r
+ uint res = DY;\r
+ uint ea = EA_AX_DI_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, di, a)\r
+{\r
+ uint res = AY;\r
+ uint ea = EA_AX_DI_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, di, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_32;\r
+ uint ea = EA_AX_DI_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, ix, d)\r
+{\r
+ uint res = DY;\r
+ uint ea = EA_AX_IX_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, ix, a)\r
+{\r
+ uint res = AY;\r
+ uint ea = EA_AX_IX_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, ix, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_32;\r
+ uint ea = EA_AX_IX_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, aw, d)\r
+{\r
+ uint res = DY;\r
+ uint ea = EA_AW_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, aw, a)\r
+{\r
+ uint res = AY;\r
+ uint ea = EA_AW_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, aw, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_32;\r
+ uint ea = EA_AW_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, al, d)\r
+{\r
+ uint res = DY;\r
+ uint ea = EA_AL_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, al, a)\r
+{\r
+ uint res = AY;\r
+ uint ea = EA_AL_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, al, .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_32;\r
+ uint ea = EA_AL_32();\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(movea, 16, ., d)\r
+{\r
+ AX = MAKE_INT_16(DY);\r
+}\r
+\r
+\r
+M68KMAKE_OP(movea, 16, ., a)\r
+{\r
+ AX = MAKE_INT_16(AY);\r
+}\r
+\r
+\r
+M68KMAKE_OP(movea, 16, ., .)\r
+{\r
+ AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
+}\r
+\r
+\r
+M68KMAKE_OP(movea, 32, ., d)\r
+{\r
+ AX = DY;\r
+}\r
+\r
+\r
+M68KMAKE_OP(movea, 32, ., a)\r
+{\r
+ AX = AY;\r
+}\r
+\r
+\r
+M68KMAKE_OP(movea, 32, ., .)\r
+{\r
+ AX = M68KMAKE_GET_OPER_AY_32;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, frc, d)\r
+{\r
+ if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
+ {\r
+ DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, frc, .)\r
+{\r
+ if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
+ {\r
+ m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, toc, d)\r
+{\r
+ m68ki_set_ccr(DY);\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, toc, .)\r
+{\r
+ m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, frs, d)\r
+{\r
+ if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */\r
+ {\r
+ DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();\r
+ return;\r
+ }\r
+ m68ki_exception_privilege_violation();\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, frs, .)\r
+{\r
+ if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */\r
+ {\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ m68ki_write_16(ea, m68ki_get_sr());\r
+ return;\r
+ }\r
+ m68ki_exception_privilege_violation();\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, tos, d)\r
+{\r
+ if(FLAG_S)\r
+ {\r
+ m68ki_set_sr(DY);\r
+ return;\r
+ }\r
+ m68ki_exception_privilege_violation();\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 16, tos, .)\r
+{\r
+ if(FLAG_S)\r
+ {\r
+ uint new_sr = M68KMAKE_GET_OPER_AY_16;\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_set_sr(new_sr);\r
+ return;\r
+ }\r
+ m68ki_exception_privilege_violation();\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, fru, .)\r
+{\r
+ if(FLAG_S)\r
+ {\r
+ AY = REG_USP;\r
+ return;\r
+ }\r
+ m68ki_exception_privilege_violation();\r
+}\r
+\r
+\r
+M68KMAKE_OP(move, 32, tou, .)\r
+{\r
+ if(FLAG_S)\r
+ {\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ REG_USP = AY;\r
+ return;\r
+ }\r
+ m68ki_exception_privilege_violation();\r
+}\r
+\r
+\r
+M68KMAKE_OP(movec, 32, cr, .)\r
+{\r
+ if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
+ {\r
+ if(FLAG_S)\r
+ {\r
+ uint word2 = OPER_I_16();\r
+\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ switch (word2 & 0xfff)\r
+ {\r
+ case 0x000: /* SFC */\r
+ REG_DA[(word2 >> 12) & 15] = REG_SFC;\r
+ return;\r
+ case 0x001: /* DFC */\r
+ REG_DA[(word2 >> 12) & 15] = REG_DFC;\r
+ return;\r
+ case 0x002: /* CACR */\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ REG_DA[(word2 >> 12) & 15] = REG_CACR;\r
+ return;\r
+ }\r
+ return;\r
+ case 0x800: /* USP */\r
+ REG_DA[(word2 >> 12) & 15] = REG_USP;\r
+ return;\r
+ case 0x801: /* VBR */\r
+ REG_DA[(word2 >> 12) & 15] = REG_VBR;\r
+ return;\r
+ case 0x802: /* CAAR */\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ REG_DA[(word2 >> 12) & 15] = REG_CAAR;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ break;\r
+ case 0x803: /* MSP */\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x804: /* ISP */\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x003: /* TC */\r
+ if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
+ {\r
+ /* TODO */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x004: /* ITT0 */\r
+ if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
+ {\r
+ /* TODO */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x005: /* ITT1 */\r
+ if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
+ {\r
+ /* TODO */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x006: /* DTT0 */\r
+ if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
+ {\r
+ /* TODO */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x007: /* DTT1 */\r
+ if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
+ {\r
+ /* TODO */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x805: /* MMUSR */\r
+ if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
+ {\r
+ /* TODO */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x806: /* URP */\r
+ if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
+ {\r
+ /* TODO */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x807: /* SRP */\r
+ if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
+ {\r
+ /* TODO */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ default:\r
+ m68ki_exception_illegal();\r
+ return;\r
+ }\r
+ }\r
+ m68ki_exception_privilege_violation();\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(movec, 32, rc, .)\r
+{\r
+ if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
+ {\r
+ if(FLAG_S)\r
+ {\r
+ uint word2 = OPER_I_16();\r
+\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ switch (word2 & 0xfff)\r
+ {\r
+ case 0x000: /* SFC */\r
+ REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;\r
+ return;\r
+ case 0x001: /* DFC */\r
+ REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;\r
+ return;\r
+ case 0x002: /* CACR */\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ REG_CACR = REG_DA[(word2 >> 12) & 15];\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x800: /* USP */\r
+ REG_USP = REG_DA[(word2 >> 12) & 15];\r
+ return;\r
+ case 0x801: /* VBR */\r
+ REG_VBR = REG_DA[(word2 >> 12) & 15];\r
+ return;\r
+ case 0x802: /* CAAR */\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ REG_CAAR = REG_DA[(word2 >> 12) & 15];\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x803: /* MSP */\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ /* we are in supervisor mode so just check for M flag */\r
+ if(!FLAG_M)\r
+ {\r
+ REG_MSP = REG_DA[(word2 >> 12) & 15];\r
+ return;\r
+ }\r
+ REG_SP = REG_DA[(word2 >> 12) & 15];\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x804: /* ISP */\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ if(!FLAG_M)\r
+ {\r
+ REG_SP = REG_DA[(word2 >> 12) & 15];\r
+ return;\r
+ }\r
+ REG_ISP = REG_DA[(word2 >> 12) & 15];\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x003: /* TC */\r
+ if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
+ {\r
+ /* TODO */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x004: /* ITT0 */\r
+ if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
+ {\r
+ /* TODO */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x005: /* ITT1 */\r
+ if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
+ {\r
+ /* TODO */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x006: /* DTT0 */\r
+ if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
+ {\r
+ /* TODO */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x007: /* DTT1 */\r
+ if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
+ {\r
+ /* TODO */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x805: /* MMUSR */\r
+ if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
+ {\r
+ /* TODO */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x806: /* URP */\r
+ if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
+ {\r
+ /* TODO */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ case 0x807: /* SRP */\r
+ if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
+ {\r
+ /* TODO */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+ return;\r
+ default:\r
+ m68ki_exception_illegal();\r
+ return;\r
+ }\r
+ }\r
+ m68ki_exception_privilege_violation();\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(movem, 16, re, pd)\r
+{\r
+ uint i = 0;\r
+ uint register_list = OPER_I_16();\r
+ uint ea = AY;\r
+ uint count = 0;\r
+\r
+ for(; i < 16; i++)\r
+ if(register_list & (1 << i))\r
+ {\r
+ ea -= 2;\r
+ m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));\r
+ count++;\r
+ }\r
+ AY = ea;\r
+\r
+ USE_CYCLES(count<<CYC_MOVEM_W);\r
+}\r
+\r
+\r
+M68KMAKE_OP(movem, 16, re, .)\r
+{\r
+ uint i = 0;\r
+ uint register_list = OPER_I_16();\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint count = 0;\r
+\r
+ for(; i < 16; i++)\r
+ if(register_list & (1 << i))\r
+ {\r
+ m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));\r
+ ea += 2;\r
+ count++;\r
+ }\r
+\r
+ USE_CYCLES(count<<CYC_MOVEM_W);\r
+}\r
+\r
+\r
+M68KMAKE_OP(movem, 32, re, pd)\r
+{\r
+ uint i = 0;\r
+ uint register_list = OPER_I_16();\r
+ uint ea = AY;\r
+ uint count = 0;\r
+\r
+ for(; i < 16; i++)\r
+ if(register_list & (1 << i))\r
+ {\r
+ ea -= 4;\r
+ m68ki_write_32(ea, REG_DA[15-i]);\r
+ count++;\r
+ }\r
+ AY = ea;\r
+\r
+ USE_CYCLES(count<<CYC_MOVEM_L);\r
+}\r
+\r
+\r
+M68KMAKE_OP(movem, 32, re, .)\r
+{\r
+ uint i = 0;\r
+ uint register_list = OPER_I_16();\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint count = 0;\r
+\r
+ for(; i < 16; i++)\r
+ if(register_list & (1 << i))\r
+ {\r
+ m68ki_write_32(ea, REG_DA[i]);\r
+ ea += 4;\r
+ count++;\r
+ }\r
+\r
+ USE_CYCLES(count<<CYC_MOVEM_L);\r
+}\r
+\r
+\r
+M68KMAKE_OP(movem, 16, er, pi)\r
+{\r
+ uint i = 0;\r
+ uint register_list = OPER_I_16();\r
+ uint ea = AY;\r
+ uint count = 0;\r
+\r
+ for(; i < 16; i++)\r
+ if(register_list & (1 << i))\r
+ {\r
+ REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));\r
+ ea += 2;\r
+ count++;\r
+ }\r
+ AY = ea;\r
+\r
+ USE_CYCLES(count<<CYC_MOVEM_W);\r
+}\r
+\r
+\r
+M68KMAKE_OP(movem, 16, er, pcdi)\r
+{\r
+ uint i = 0;\r
+ uint register_list = OPER_I_16();\r
+ uint ea = EA_PCDI_16();\r
+ uint count = 0;\r
+\r
+ for(; i < 16; i++)\r
+ if(register_list & (1 << i))\r
+ {\r
+ REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));\r
+ ea += 2;\r
+ count++;\r
+ }\r
+\r
+ USE_CYCLES(count<<CYC_MOVEM_W);\r
+}\r
+\r
+\r
+M68KMAKE_OP(movem, 16, er, pcix)\r
+{\r
+ uint i = 0;\r
+ uint register_list = OPER_I_16();\r
+ uint ea = EA_PCIX_16();\r
+ uint count = 0;\r
+\r
+ for(; i < 16; i++)\r
+ if(register_list & (1 << i))\r
+ {\r
+ REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));\r
+ ea += 2;\r
+ count++;\r
+ }\r
+\r
+ USE_CYCLES(count<<CYC_MOVEM_W);\r
+}\r
+\r
+\r
+M68KMAKE_OP(movem, 16, er, .)\r
+{\r
+ uint i = 0;\r
+ uint register_list = OPER_I_16();\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint count = 0;\r
+\r
+ for(; i < 16; i++)\r
+ if(register_list & (1 << i))\r
+ {\r
+ REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));\r
+ ea += 2;\r
+ count++;\r
+ }\r
+\r
+ USE_CYCLES(count<<CYC_MOVEM_W);\r
+}\r
+\r
+\r
+M68KMAKE_OP(movem, 32, er, pi)\r
+{\r
+ uint i = 0;\r
+ uint register_list = OPER_I_16();\r
+ uint ea = AY;\r
+ uint count = 0;\r
+\r
+ for(; i < 16; i++)\r
+ if(register_list & (1 << i))\r
+ {\r
+ REG_DA[i] = m68ki_read_32(ea);\r
+ ea += 4;\r
+ count++;\r
+ }\r
+ AY = ea;\r
+\r
+ USE_CYCLES(count<<CYC_MOVEM_L);\r
+}\r
+\r
+\r
+M68KMAKE_OP(movem, 32, er, pcdi)\r
+{\r
+ uint i = 0;\r
+ uint register_list = OPER_I_16();\r
+ uint ea = EA_PCDI_32();\r
+ uint count = 0;\r
+\r
+ for(; i < 16; i++)\r
+ if(register_list & (1 << i))\r
+ {\r
+ REG_DA[i] = m68ki_read_pcrel_32(ea);\r
+ ea += 4;\r
+ count++;\r
+ }\r
+\r
+ USE_CYCLES(count<<CYC_MOVEM_L);\r
+}\r
+\r
+\r
+M68KMAKE_OP(movem, 32, er, pcix)\r
+{\r
+ uint i = 0;\r
+ uint register_list = OPER_I_16();\r
+ uint ea = EA_PCIX_32();\r
+ uint count = 0;\r
+\r
+ for(; i < 16; i++)\r
+ if(register_list & (1 << i))\r
+ {\r
+ REG_DA[i] = m68ki_read_pcrel_32(ea);\r
+ ea += 4;\r
+ count++;\r
+ }\r
+\r
+ USE_CYCLES(count<<CYC_MOVEM_L);\r
+}\r
+\r
+\r
+M68KMAKE_OP(movem, 32, er, .)\r
+{\r
+ uint i = 0;\r
+ uint register_list = OPER_I_16();\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint count = 0;\r
+\r
+ for(; i < 16; i++)\r
+ if(register_list & (1 << i))\r
+ {\r
+ REG_DA[i] = m68ki_read_32(ea);\r
+ ea += 4;\r
+ count++;\r
+ }\r
+\r
+ USE_CYCLES(count<<CYC_MOVEM_L);\r
+}\r
+\r
+\r
+M68KMAKE_OP(movep, 16, re, .)\r
+{\r
+ uint ea = EA_AY_DI_16();\r
+ uint src = DX;\r
+\r
+ m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));\r
+ m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));\r
+}\r
+\r
+\r
+M68KMAKE_OP(movep, 32, re, .)\r
+{\r
+ uint ea = EA_AY_DI_32();\r
+ uint src = DX;\r
+\r
+ m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));\r
+ m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));\r
+ m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));\r
+ m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));\r
+}\r
+\r
+\r
+M68KMAKE_OP(movep, 16, er, .)\r
+{\r
+ uint ea = EA_AY_DI_16();\r
+ uint* r_dst = &DX;\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));\r
+}\r
+\r
+\r
+M68KMAKE_OP(movep, 32, er, .)\r
+{\r
+ uint ea = EA_AY_DI_32();\r
+\r
+ DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)\r
+ + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);\r
+}\r
+\r
+\r
+M68KMAKE_OP(moves, 8, ., .)\r
+{\r
+ if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
+ {\r
+ if(FLAG_S)\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ if(BIT_B(word2)) /* Register to memory */\r
+ {\r
+ m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));\r
+ return;\r
+ }\r
+ if(BIT_F(word2)) /* Memory to address register */\r
+ {\r
+ REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));\r
+ if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
+ USE_CYCLES(2);\r
+ return;\r
+ }\r
+ /* Memory to data register */\r
+ REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);\r
+ if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
+ USE_CYCLES(2);\r
+ return;\r
+ }\r
+ m68ki_exception_privilege_violation();\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(moves, 16, ., .)\r
+{\r
+ if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
+ {\r
+ if(FLAG_S)\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ if(BIT_B(word2)) /* Register to memory */\r
+ {\r
+ m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));\r
+ return;\r
+ }\r
+ if(BIT_F(word2)) /* Memory to address register */\r
+ {\r
+ REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));\r
+ if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
+ USE_CYCLES(2);\r
+ return;\r
+ }\r
+ /* Memory to data register */\r
+ REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);\r
+ if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
+ USE_CYCLES(2);\r
+ return;\r
+ }\r
+ m68ki_exception_privilege_violation();\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(moves, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
+ {\r
+ if(FLAG_S)\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ if(BIT_B(word2)) /* Register to memory */\r
+ {\r
+ m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);\r
+ if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
+ USE_CYCLES(2);\r
+ return;\r
+ }\r
+ /* Memory to register */\r
+ REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);\r
+ if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
+ USE_CYCLES(2);\r
+ return;\r
+ }\r
+ m68ki_exception_privilege_violation();\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(moveq, 32, ., .)\r
+{\r
+ uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(move16, 32, ., .)\r
+{\r
+ UINT16 w2 = OPER_I_16();\r
+ int ax = REG_IR & 7;\r
+ int ay = (w2 >> 12) & 7;\r
+\r
+ m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));\r
+ m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));\r
+ m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));\r
+ m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));\r
+\r
+ REG_A[ax] += 16;\r
+ REG_A[ay] += 16;\r
+}\r
+\r
+\r
+M68KMAKE_OP(muls, 16, ., d)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_Z = res;\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(muls, 16, ., .)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_Z = res;\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(mulu, 16, ., d)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_Z = res;\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(mulu, 16, ., .)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_Z = res;\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(mull, 32, ., d)\r
+{\r
+#if M68K_USE_64_BIT\r
+\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint64 src = DY;\r
+ uint64 dst = REG_D[(word2 >> 12) & 7];\r
+ uint64 res;\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ if(BIT_B(word2)) /* signed */\r
+ {\r
+ res = (sint64)((sint32)src) * (sint64)((sint32)dst);\r
+ if(!BIT_A(word2))\r
+ {\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_V = ((sint64)res != (sint32)res)<<7;\r
+ REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
+ return;\r
+ }\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
+ FLAG_N = NFLAG_64(res);\r
+ FLAG_V = VFLAG_CLEAR;\r
+ REG_D[word2 & 7] = (res >> 32);\r
+ REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
+ return;\r
+ }\r
+\r
+ res = src * dst;\r
+ if(!BIT_A(word2))\r
+ {\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_V = (res > 0xffffffff)<<7;\r
+ REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
+ return;\r
+ }\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
+ FLAG_N = NFLAG_64(res);\r
+ FLAG_V = VFLAG_CLEAR;\r
+ REG_D[word2 & 7] = (res >> 32);\r
+ REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+\r
+#else\r
+\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint src = DY;\r
+ uint dst = REG_D[(word2 >> 12) & 7];\r
+ uint neg = GET_MSB_32(src ^ dst);\r
+ uint src1;\r
+ uint src2;\r
+ uint dst1;\r
+ uint dst2;\r
+ uint r1;\r
+ uint r2;\r
+ uint r3;\r
+ uint r4;\r
+ uint lo;\r
+ uint hi;\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ if(BIT_B(word2)) /* signed */\r
+ {\r
+ if(GET_MSB_32(src))\r
+ src = (uint)MASK_OUT_ABOVE_32(-(sint)src);\r
+ if(GET_MSB_32(dst))\r
+ dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);\r
+ }\r
+\r
+ src1 = MASK_OUT_ABOVE_16(src);\r
+ src2 = src>>16;\r
+ dst1 = MASK_OUT_ABOVE_16(dst);\r
+ dst2 = dst>>16;\r
+\r
+\r
+ r1 = src1 * dst1;\r
+ r2 = src1 * dst2;\r
+ r3 = src2 * dst1;\r
+ r4 = src2 * dst2;\r
+\r
+ lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);\r
+ hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);\r
+\r
+ if(BIT_B(word2) && neg)\r
+ {\r
+ hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));\r
+ lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);\r
+ }\r
+\r
+ if(BIT_A(word2))\r
+ {\r
+ REG_D[word2 & 7] = hi;\r
+ REG_D[(word2 >> 12) & 7] = lo;\r
+ FLAG_N = NFLAG_32(hi);\r
+ FLAG_Z = hi | lo;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ REG_D[(word2 >> 12) & 7] = lo;\r
+ FLAG_N = NFLAG_32(lo);\r
+ FLAG_Z = lo;\r
+ if(BIT_B(word2))\r
+ FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;\r
+ else\r
+ FLAG_V = (hi != 0) << 7;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+\r
+#endif\r
+}\r
+\r
+\r
+M68KMAKE_OP(mull, 32, ., .)\r
+{\r
+#if M68K_USE_64_BIT\r
+\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint64 src = M68KMAKE_GET_OPER_AY_32;\r
+ uint64 dst = REG_D[(word2 >> 12) & 7];\r
+ uint64 res;\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ if(BIT_B(word2)) /* signed */\r
+ {\r
+ res = (sint64)((sint32)src) * (sint64)((sint32)dst);\r
+ if(!BIT_A(word2))\r
+ {\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_V = ((sint64)res != (sint32)res)<<7;\r
+ REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
+ return;\r
+ }\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
+ FLAG_N = NFLAG_64(res);\r
+ FLAG_V = VFLAG_CLEAR;\r
+ REG_D[word2 & 7] = (res >> 32);\r
+ REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
+ return;\r
+ }\r
+\r
+ res = src * dst;\r
+ if(!BIT_A(word2))\r
+ {\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_V = (res > 0xffffffff)<<7;\r
+ REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
+ return;\r
+ }\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
+ FLAG_N = NFLAG_64(res);\r
+ FLAG_V = VFLAG_CLEAR;\r
+ REG_D[word2 & 7] = (res >> 32);\r
+ REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+\r
+#else\r
+\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint word2 = OPER_I_16();\r
+ uint src = M68KMAKE_GET_OPER_AY_32;\r
+ uint dst = REG_D[(word2 >> 12) & 7];\r
+ uint neg = GET_MSB_32(src ^ dst);\r
+ uint src1;\r
+ uint src2;\r
+ uint dst1;\r
+ uint dst2;\r
+ uint r1;\r
+ uint r2;\r
+ uint r3;\r
+ uint r4;\r
+ uint lo;\r
+ uint hi;\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+\r
+ if(BIT_B(word2)) /* signed */\r
+ {\r
+ if(GET_MSB_32(src))\r
+ src = (uint)MASK_OUT_ABOVE_32(-(sint)src);\r
+ if(GET_MSB_32(dst))\r
+ dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);\r
+ }\r
+\r
+ src1 = MASK_OUT_ABOVE_16(src);\r
+ src2 = src>>16;\r
+ dst1 = MASK_OUT_ABOVE_16(dst);\r
+ dst2 = dst>>16;\r
+\r
+\r
+ r1 = src1 * dst1;\r
+ r2 = src1 * dst2;\r
+ r3 = src2 * dst1;\r
+ r4 = src2 * dst2;\r
+\r
+ lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);\r
+ hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);\r
+\r
+ if(BIT_B(word2) && neg)\r
+ {\r
+ hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));\r
+ lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);\r
+ }\r
+\r
+ if(BIT_A(word2))\r
+ {\r
+ REG_D[word2 & 7] = hi;\r
+ REG_D[(word2 >> 12) & 7] = lo;\r
+ FLAG_N = NFLAG_32(hi);\r
+ FLAG_Z = hi | lo;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ REG_D[(word2 >> 12) & 7] = lo;\r
+ FLAG_N = NFLAG_32(lo);\r
+ FLAG_Z = lo;\r
+ if(BIT_B(word2))\r
+ FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;\r
+ else\r
+ FLAG_V = (hi != 0) << 7;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+\r
+#endif\r
+}\r
+\r
+\r
+M68KMAKE_OP(nbcd, 8, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint dst = *r_dst;\r
+ uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());\r
+\r
+ if(res != 0x9a)\r
+ {\r
+ FLAG_V = ~res; /* Undefined V behavior */\r
+\r
+ if((res & 0x0f) == 0xa)\r
+ res = (res & 0xf0) + 0x10;\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+\r
+ FLAG_V &= res; /* Undefined V behavior part II */\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+\r
+ FLAG_Z |= res;\r
+ FLAG_C = CFLAG_SET;\r
+ FLAG_X = XFLAG_SET;\r
+ }\r
+ else\r
+ {\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_X = XFLAG_CLEAR;\r
+ }\r
+ FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
+}\r
+\r
+\r
+M68KMAKE_OP(nbcd, 8, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());\r
+\r
+ if(res != 0x9a)\r
+ {\r
+ FLAG_V = ~res; /* Undefined V behavior */\r
+\r
+ if((res & 0x0f) == 0xa)\r
+ res = (res & 0xf0) + 0x10;\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+\r
+ FLAG_V &= res; /* Undefined V behavior part II */\r
+\r
+ m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));\r
+\r
+ FLAG_Z |= res;\r
+ FLAG_C = CFLAG_SET;\r
+ FLAG_X = XFLAG_SET;\r
+ }\r
+ else\r
+ {\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_X = XFLAG_CLEAR;\r
+ }\r
+ FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
+}\r
+\r
+\r
+M68KMAKE_OP(neg, 8, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_C = FLAG_X = CFLAG_8(res);\r
+ FLAG_V = *r_dst & res;\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(neg, 8, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint src = m68ki_read_8(ea);\r
+ uint res = 0 - src;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_C = FLAG_X = CFLAG_8(res);\r
+ FLAG_V = src & res;\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+\r
+ m68ki_write_8(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(neg, 16, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_C = FLAG_X = CFLAG_16(res);\r
+ FLAG_V = (*r_dst & res)>>8;\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(neg, 16, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint src = m68ki_read_16(ea);\r
+ uint res = 0 - src;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_C = FLAG_X = CFLAG_16(res);\r
+ FLAG_V = (src & res)>>8;\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+\r
+ m68ki_write_16(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(neg, 32, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint res = 0 - *r_dst;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);\r
+ FLAG_V = (*r_dst & res)>>24;\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+\r
+ *r_dst = FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(neg, 32, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint src = m68ki_read_32(ea);\r
+ uint res = 0 - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);\r
+ FLAG_V = (src & res)>>24;\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+\r
+ m68ki_write_32(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(negx, 8, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_V = *r_dst & res;\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+ FLAG_Z |= res;\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+}\r
+\r
+\r
+M68KMAKE_OP(negx, 8, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint src = m68ki_read_8(ea);\r
+ uint res = 0 - src - XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_V = src & res;\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_8(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(negx, 16, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_V = (*r_dst & res)>>8;\r
+\r
+ res = MASK_OUT_ABOVE_16(res);\r
+ FLAG_Z |= res;\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+}\r
+\r
+\r
+M68KMAKE_OP(negx, 16, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint src = m68ki_read_16(ea);\r
+ uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_V = (src & res)>>8;\r
+\r
+ res = MASK_OUT_ABOVE_16(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_16(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(negx, 32, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);\r
+ FLAG_V = (*r_dst & res)>>24;\r
+\r
+ res = MASK_OUT_ABOVE_32(res);\r
+ FLAG_Z |= res;\r
+\r
+ *r_dst = res;\r
+}\r
+\r
+\r
+M68KMAKE_OP(negx, 32, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint src = m68ki_read_32(ea);\r
+ uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);\r
+ FLAG_V = (src & res)>>24;\r
+\r
+ res = MASK_OUT_ABOVE_32(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_32(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(nop, 0, ., .)\r
+{\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+}\r
+\r
+\r
+M68KMAKE_OP(not, 8, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint res = MASK_OUT_ABOVE_8(~*r_dst);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(not, 8, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(not, 16, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint res = MASK_OUT_ABOVE_16(~*r_dst);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(not, 16, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(not, 32, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(not, 32, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(or, 8, er, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(or, 8, er, .)\r
+{\r
+ uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(or, 16, er, d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(or, 16, er, .)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(or, 32, er, d)\r
+{\r
+ uint res = DX |= DY;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(or, 32, er, .)\r
+{\r
+ uint res = DX |= M68KMAKE_GET_OPER_AY_32;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(or, 8, re, .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(or, 16, re, .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(or, 32, re, .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint res = DX | m68ki_read_32(ea);\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(ori, 8, ., d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(ori, 8, ., .)\r
+{\r
+ uint src = OPER_I_8();\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));\r
+\r
+ m68ki_write_8(ea, res);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(ori, 16, ., d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(ori, 16, ., .)\r
+{\r
+ uint src = OPER_I_16();\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(ori, 32, ., d)\r
+{\r
+ uint res = DY |= OPER_I_32();\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(ori, 32, ., .)\r
+{\r
+ uint src = OPER_I_32();\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint res = src | m68ki_read_32(ea);\r
+\r
+ m68ki_write_32(ea, res);\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(ori, 16, toc, .)\r
+{\r
+ m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());\r
+}\r
+\r
+\r
+M68KMAKE_OP(ori, 16, tos, .)\r
+{\r
+ if(FLAG_S)\r
+ {\r
+ uint src = OPER_I_16();\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_set_sr(m68ki_get_sr() | src);\r
+ return;\r
+ }\r
+ m68ki_exception_privilege_violation();\r
+}\r
+\r
+\r
+M68KMAKE_OP(pack, 16, rr, .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ /* Note: DX and DY are reversed in Motorola's docs */\r
+ uint src = DY + OPER_I_16();\r
+ uint* r_dst = &DX;\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(pack, 16, mm, ax7)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ /* Note: AX and AY are reversed in Motorola's docs */\r
+ uint ea_src = EA_AY_PD_8();\r
+ uint src = m68ki_read_8(ea_src);\r
+ ea_src = EA_AY_PD_8();\r
+ src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
+\r
+ m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(pack, 16, mm, ay7)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ /* Note: AX and AY are reversed in Motorola's docs */\r
+ uint ea_src = EA_A7_PD_8();\r
+ uint src = m68ki_read_8(ea_src);\r
+ ea_src = EA_A7_PD_8();\r
+ src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
+\r
+ m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(pack, 16, mm, axy7)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint ea_src = EA_A7_PD_8();\r
+ uint src = m68ki_read_8(ea_src);\r
+ ea_src = EA_A7_PD_8();\r
+ src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
+\r
+ m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(pack, 16, mm, .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ /* Note: AX and AY are reversed in Motorola's docs */\r
+ uint ea_src = EA_AY_PD_8();\r
+ uint src = m68ki_read_8(ea_src);\r
+ ea_src = EA_AY_PD_8();\r
+ src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
+\r
+ m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(pea, 32, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+\r
+ m68ki_push_32(ea);\r
+}\r
+\r
+\r
+M68KMAKE_OP(pflush, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
+ {\r
+ // Nothing to do, unless address translation cache is emulated\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(reset, 0, ., .)\r
+{\r
+ if(FLAG_S)\r
+ {\r
+ m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */\r
+ USE_CYCLES(CYC_RESET);\r
+ return;\r
+ }\r
+ m68ki_exception_privilege_violation();\r
+}\r
+\r
+\r
+M68KMAKE_OP(ror, 8, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint shift = orig_shift & 7;\r
+ uint src = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = ROR_8(src, shift);\r
+\r
+ if(orig_shift != 0)\r
+ USE_CYCLES(orig_shift<<CYC_SHIFT);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = src << (9-orig_shift);\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(ror, 16, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = ROR_16(src, shift);\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = src << (9-shift);\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(ror, 32, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint64 src = *r_dst;\r
+ uint res = ROR_32(src, shift);\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = src << (9-shift);\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(ror, 8, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint orig_shift = DX & 0x3f;\r
+ uint shift = orig_shift & 7;\r
+ uint src = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = ROR_8(src, shift);\r
+\r
+ if(orig_shift != 0)\r
+ {\r
+ USE_CYCLES(orig_shift<<CYC_SHIFT);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+ FLAG_C = src << (8-((shift-1)&7));\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_8(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(ror, 16, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint orig_shift = DX & 0x3f;\r
+ uint shift = orig_shift & 15;\r
+ uint src = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = ROR_16(src, shift);\r
+\r
+ if(orig_shift != 0)\r
+ {\r
+ USE_CYCLES(orig_shift<<CYC_SHIFT);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+ FLAG_C = (src >> ((shift - 1) & 15)) << 8;\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_16(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(ror, 32, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint orig_shift = DX & 0x3f;\r
+ uint shift = orig_shift & 31;\r
+ uint64 src = *r_dst;\r
+ uint res = ROR_32(src, shift);\r
+\r
+ if(orig_shift != 0)\r
+ {\r
+ USE_CYCLES(orig_shift<<CYC_SHIFT);\r
+\r
+ *r_dst = res;\r
+ FLAG_C = (src >> ((shift - 1) & 31)) << 8;\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_32(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(ror, 16, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint src = m68ki_read_16(ea);\r
+ uint res = ROR_16(src, 1);\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = src << 8;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(rol, 8, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint shift = orig_shift & 7;\r
+ uint src = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = ROL_8(src, shift);\r
+\r
+ if(orig_shift != 0)\r
+ USE_CYCLES(orig_shift<<CYC_SHIFT);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = src << orig_shift;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(rol, 16, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = ROL_16(src, shift);\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = src >> (8-shift);\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(rol, 32, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint64 src = *r_dst;\r
+ uint res = ROL_32(src, shift);\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = src >> (24-shift);\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(rol, 8, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint orig_shift = DX & 0x3f;\r
+ uint shift = orig_shift & 7;\r
+ uint src = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = ROL_8(src, shift);\r
+\r
+ if(orig_shift != 0)\r
+ {\r
+ USE_CYCLES(orig_shift<<CYC_SHIFT);\r
+\r
+ if(shift != 0)\r
+ {\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+ FLAG_C = src << shift;\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+ FLAG_C = (src & 1)<<8;\r
+ FLAG_N = NFLAG_8(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_8(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(rol, 16, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint orig_shift = DX & 0x3f;\r
+ uint shift = orig_shift & 15;\r
+ uint src = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));\r
+\r
+ if(orig_shift != 0)\r
+ {\r
+ USE_CYCLES(orig_shift<<CYC_SHIFT);\r
+\r
+ if(shift != 0)\r
+ {\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+ FLAG_C = (src << shift) >> 8;\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+ FLAG_C = (src & 1)<<8;\r
+ FLAG_N = NFLAG_16(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_16(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(rol, 32, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint orig_shift = DX & 0x3f;\r
+ uint shift = orig_shift & 31;\r
+ uint64 src = *r_dst;\r
+ uint res = ROL_32(src, shift);\r
+\r
+ if(orig_shift != 0)\r
+ {\r
+ USE_CYCLES(orig_shift<<CYC_SHIFT);\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_C = (src >> (32 - shift)) << 8;\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_N = NFLAG_32(src);\r
+ FLAG_Z = src;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(rol, 16, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint src = m68ki_read_16(ea);\r
+ uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_C = src >> 7;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(roxr, 8, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ FLAG_C = FLAG_X = res;\r
+ res = MASK_OUT_ABOVE_8(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(roxr, 16, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ FLAG_C = FLAG_X = res >> 8;\r
+ res = MASK_OUT_ABOVE_16(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(roxr, 32, s, .)\r
+{\r
+#if M68K_USE_64_BIT\r
+\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint64 src = *r_dst;\r
+ uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ res = ROR_33_64(res, shift);\r
+\r
+ FLAG_C = FLAG_X = res >> 24;\r
+ res = MASK_OUT_ABOVE_32(res);\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+\r
+#else\r
+\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = *r_dst;\r
+ uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));\r
+ uint new_x_flag = src & (1 << (shift - 1));\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_C = FLAG_X = (new_x_flag != 0)<<8;\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+\r
+#endif\r
+}\r
+\r
+\r
+M68KMAKE_OP(roxr, 8, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint orig_shift = DX & 0x3f;\r
+\r
+ if(orig_shift != 0)\r
+ {\r
+ uint shift = orig_shift % 9;\r
+ uint src = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);\r
+\r
+ USE_CYCLES(orig_shift<<CYC_SHIFT);\r
+\r
+ FLAG_C = FLAG_X = res;\r
+ res = MASK_OUT_ABOVE_8(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = FLAG_X;\r
+ FLAG_N = NFLAG_8(*r_dst);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(roxr, 16, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint orig_shift = DX & 0x3f;\r
+\r
+ if(orig_shift != 0)\r
+ {\r
+ uint shift = orig_shift % 17;\r
+ uint src = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);\r
+\r
+ USE_CYCLES(orig_shift<<CYC_SHIFT);\r
+\r
+ FLAG_C = FLAG_X = res >> 8;\r
+ res = MASK_OUT_ABOVE_16(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = FLAG_X;\r
+ FLAG_N = NFLAG_16(*r_dst);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(roxr, 32, r, .)\r
+{\r
+#if M68K_USE_64_BIT\r
+\r
+ uint* r_dst = &DY;\r
+ uint orig_shift = DX & 0x3f;\r
+\r
+ if(orig_shift != 0)\r
+ {\r
+ uint shift = orig_shift % 33;\r
+ uint64 src = *r_dst;\r
+ uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
+\r
+ res = ROR_33_64(res, shift);\r
+\r
+ USE_CYCLES(orig_shift<<CYC_SHIFT);\r
+\r
+ FLAG_C = FLAG_X = res >> 24;\r
+ res = MASK_OUT_ABOVE_32(res);\r
+\r
+ *r_dst = res;\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = FLAG_X;\r
+ FLAG_N = NFLAG_32(*r_dst);\r
+ FLAG_Z = *r_dst;\r
+ FLAG_V = VFLAG_CLEAR;\r
+\r
+#else\r
+\r
+ uint* r_dst = &DY;\r
+ uint orig_shift = DX & 0x3f;\r
+ uint shift = orig_shift % 33;\r
+ uint src = *r_dst;\r
+ uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));\r
+ uint new_x_flag = src & (1 << (shift - 1));\r
+\r
+ if(orig_shift != 0)\r
+ USE_CYCLES(orig_shift<<CYC_SHIFT);\r
+\r
+ if(shift != 0)\r
+ {\r
+ *r_dst = res;\r
+ FLAG_X = (new_x_flag != 0)<<8;\r
+ }\r
+ else\r
+ res = src;\r
+ FLAG_C = FLAG_X;\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+\r
+#endif\r
+}\r
+\r
+\r
+M68KMAKE_OP(roxr, 16, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint src = m68ki_read_16(ea);\r
+ uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);\r
+\r
+ FLAG_C = FLAG_X = res >> 8;\r
+ res = MASK_OUT_ABOVE_16(res);\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(roxl, 8, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ FLAG_C = FLAG_X = res;\r
+ res = MASK_OUT_ABOVE_8(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(roxl, 16, s, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ FLAG_C = FLAG_X = res >> 8;\r
+ res = MASK_OUT_ABOVE_16(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(roxl, 32, s, .)\r
+{\r
+#if M68K_USE_64_BIT\r
+\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint64 src = *r_dst;\r
+ uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ res = ROL_33_64(res, shift);\r
+\r
+ FLAG_C = FLAG_X = res >> 24;\r
+ res = MASK_OUT_ABOVE_32(res);\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+\r
+#else\r
+\r
+ uint* r_dst = &DY;\r
+ uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint src = *r_dst;\r
+ uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));\r
+ uint new_x_flag = src & (1 << (32 - shift));\r
+\r
+ if(shift != 0)\r
+ USE_CYCLES(shift<<CYC_SHIFT);\r
+\r
+ *r_dst = res;\r
+\r
+ FLAG_C = FLAG_X = (new_x_flag != 0)<<8;\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+\r
+#endif\r
+}\r
+\r
+\r
+M68KMAKE_OP(roxl, 8, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint orig_shift = DX & 0x3f;\r
+\r
+\r
+ if(orig_shift != 0)\r
+ {\r
+ uint shift = orig_shift % 9;\r
+ uint src = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);\r
+\r
+ USE_CYCLES(orig_shift<<CYC_SHIFT);\r
+\r
+ FLAG_C = FLAG_X = res;\r
+ res = MASK_OUT_ABOVE_8(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = FLAG_X;\r
+ FLAG_N = NFLAG_8(*r_dst);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(roxl, 16, r, .)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint orig_shift = DX & 0x3f;\r
+\r
+ if(orig_shift != 0)\r
+ {\r
+ uint shift = orig_shift % 17;\r
+ uint src = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);\r
+\r
+ USE_CYCLES(orig_shift<<CYC_SHIFT);\r
+\r
+ FLAG_C = FLAG_X = res >> 8;\r
+ res = MASK_OUT_ABOVE_16(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = FLAG_X;\r
+ FLAG_N = NFLAG_16(*r_dst);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(roxl, 32, r, .)\r
+{\r
+#if M68K_USE_64_BIT\r
+\r
+ uint* r_dst = &DY;\r
+ uint orig_shift = DX & 0x3f;\r
+\r
+ if(orig_shift != 0)\r
+ {\r
+ uint shift = orig_shift % 33;\r
+ uint64 src = *r_dst;\r
+ uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
+\r
+ res = ROL_33_64(res, shift);\r
+\r
+ USE_CYCLES(orig_shift<<CYC_SHIFT);\r
+\r
+ FLAG_C = FLAG_X = res >> 24;\r
+ res = MASK_OUT_ABOVE_32(res);\r
+\r
+ *r_dst = res;\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ return;\r
+ }\r
+\r
+ FLAG_C = FLAG_X;\r
+ FLAG_N = NFLAG_32(*r_dst);\r
+ FLAG_Z = *r_dst;\r
+ FLAG_V = VFLAG_CLEAR;\r
+\r
+#else\r
+\r
+ uint* r_dst = &DY;\r
+ uint orig_shift = DX & 0x3f;\r
+ uint shift = orig_shift % 33;\r
+ uint src = *r_dst;\r
+ uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));\r
+ uint new_x_flag = src & (1 << (32 - shift));\r
+\r
+ if(orig_shift != 0)\r
+ USE_CYCLES(orig_shift<<CYC_SHIFT);\r
+\r
+ if(shift != 0)\r
+ {\r
+ *r_dst = res;\r
+ FLAG_X = (new_x_flag != 0)<<8;\r
+ }\r
+ else\r
+ res = src;\r
+ FLAG_C = FLAG_X;\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+\r
+#endif\r
+}\r
+\r
+\r
+M68KMAKE_OP(roxl, 16, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint src = m68ki_read_16(ea);\r
+ uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);\r
+\r
+ FLAG_C = FLAG_X = res >> 8;\r
+ res = MASK_OUT_ABOVE_16(res);\r
+\r
+ m68ki_write_16(ea, res);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(rtd, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
+ {\r
+ uint new_pc = m68ki_pull_32();\r
+\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));\r
+ m68ki_jump(new_pc);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(rte, 32, ., .)\r
+{\r
+ if(FLAG_S)\r
+ {\r
+ uint new_sr;\r
+ uint new_pc;\r
+ uint format_word;\r
+\r
+ m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+\r
+ if(CPU_TYPE_IS_000(CPU_TYPE))\r
+ {\r
+ new_sr = m68ki_pull_16();\r
+ new_pc = m68ki_pull_32();\r
+ m68ki_jump(new_pc);\r
+ m68ki_set_sr(new_sr);\r
+\r
+ CPU_INSTR_MODE = INSTRUCTION_YES;\r
+ CPU_RUN_MODE = RUN_MODE_NORMAL;\r
+\r
+ return;\r
+ }\r
+\r
+ if(CPU_TYPE_IS_010(CPU_TYPE))\r
+ {\r
+ format_word = m68ki_read_16(REG_A[7]+6) >> 12;\r
+ if(format_word == 0)\r
+ {\r
+ new_sr = m68ki_pull_16();\r
+ new_pc = m68ki_pull_32();\r
+ m68ki_fake_pull_16(); /* format word */\r
+ m68ki_jump(new_pc);\r
+ m68ki_set_sr(new_sr);\r
+ CPU_INSTR_MODE = INSTRUCTION_YES;\r
+ CPU_RUN_MODE = RUN_MODE_NORMAL;\r
+ return;\r
+ }\r
+ CPU_INSTR_MODE = INSTRUCTION_YES;\r
+ CPU_RUN_MODE = RUN_MODE_NORMAL;\r
+ /* Not handling bus fault (9) */\r
+ m68ki_exception_format_error();\r
+ return;\r
+ }\r
+\r
+ /* Otherwise it's 020 */\r
+rte_loop:\r
+ format_word = m68ki_read_16(REG_A[7]+6) >> 12;\r
+ switch(format_word)\r
+ {\r
+ case 0: /* Normal */\r
+ new_sr = m68ki_pull_16();\r
+ new_pc = m68ki_pull_32();\r
+ m68ki_fake_pull_16(); /* format word */\r
+ m68ki_jump(new_pc);\r
+ m68ki_set_sr(new_sr);\r
+ CPU_INSTR_MODE = INSTRUCTION_YES;\r
+ CPU_RUN_MODE = RUN_MODE_NORMAL;\r
+ return;\r
+ case 1: /* Throwaway */\r
+ new_sr = m68ki_pull_16();\r
+ m68ki_fake_pull_32(); /* program counter */\r
+ m68ki_fake_pull_16(); /* format word */\r
+ m68ki_set_sr_noint(new_sr);\r
+ goto rte_loop;\r
+ case 2: /* Trap */\r
+ new_sr = m68ki_pull_16();\r
+ new_pc = m68ki_pull_32();\r
+ m68ki_fake_pull_16(); /* format word */\r
+ m68ki_fake_pull_32(); /* address */\r
+ m68ki_jump(new_pc);\r
+ m68ki_set_sr(new_sr);\r
+ CPU_INSTR_MODE = INSTRUCTION_YES;\r
+ CPU_RUN_MODE = RUN_MODE_NORMAL;\r
+ return;\r
+ }\r
+ /* Not handling long or short bus fault */\r
+ CPU_INSTR_MODE = INSTRUCTION_YES;\r
+ CPU_RUN_MODE = RUN_MODE_NORMAL;\r
+ m68ki_exception_format_error();\r
+ return;\r
+ }\r
+ m68ki_exception_privilege_violation();\r
+}\r
+\r
+\r
+M68KMAKE_OP(rtm, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
+ {\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
+ m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
+ m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(rtr, 32, ., .)\r
+{\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_set_ccr(m68ki_pull_16());\r
+ m68ki_jump(m68ki_pull_32());\r
+}\r
+\r
+\r
+M68KMAKE_OP(rts, 32, ., .)\r
+{\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_jump(m68ki_pull_32());\r
+}\r
+\r
+\r
+M68KMAKE_OP(sbcd, 8, rr, .)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = DY;\r
+ uint dst = *r_dst;\r
+ uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
+\r
+// FLAG_V = ~res; /* Undefined V behavior */\r
+ FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to assume cleared. */\r
+\r
+ if(res > 9)\r
+ res -= 6;\r
+ res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
+ if(res > 0x99)\r
+ {\r
+ res += 0xa0;\r
+ FLAG_X = FLAG_C = CFLAG_SET;\r
+ FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
+ }\r
+ else\r
+ FLAG_N = FLAG_X = FLAG_C = 0;\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+\r
+// FLAG_V &= res; /* Undefined V behavior part II */\r
+// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
+ FLAG_Z |= res;\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+}\r
+\r
+\r
+M68KMAKE_OP(sbcd, 8, mm, ax7)\r
+{\r
+ uint src = OPER_AY_PD_8();\r
+ uint ea = EA_A7_PD_8();\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
+\r
+// FLAG_V = ~res; /* Undefined V behavior */\r
+ FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */\r
+\r
+ if(res > 9)\r
+ res -= 6;\r
+ res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
+ if(res > 0x99)\r
+ {\r
+ res += 0xa0;\r
+ FLAG_X = FLAG_C = CFLAG_SET;\r
+ FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
+ }\r
+ else\r
+ FLAG_N = FLAG_X = FLAG_C = 0;\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+\r
+// FLAG_V &= res; /* Undefined V behavior part II */\r
+// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_8(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(sbcd, 8, mm, ay7)\r
+{\r
+ uint src = OPER_A7_PD_8();\r
+ uint ea = EA_AX_PD_8();\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
+\r
+// FLAG_V = ~res; /* Undefined V behavior */\r
+ FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */\r
+\r
+ if(res > 9)\r
+ res -= 6;\r
+ res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
+ if(res > 0x99)\r
+ {\r
+ res += 0xa0;\r
+ FLAG_X = FLAG_C = CFLAG_SET;\r
+ FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
+ }\r
+ else\r
+ FLAG_N = FLAG_X = FLAG_C = 0;\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+\r
+// FLAG_V &= res; /* Undefined V behavior part II */\r
+// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_8(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(sbcd, 8, mm, axy7)\r
+{\r
+ uint src = OPER_A7_PD_8();\r
+ uint ea = EA_A7_PD_8();\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
+\r
+// FLAG_V = ~res; /* Undefined V behavior */\r
+ FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */\r
+\r
+ if(res > 9)\r
+ res -= 6;\r
+ res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
+ if(res > 0x99)\r
+ {\r
+ res += 0xa0;\r
+ FLAG_X = FLAG_C = CFLAG_SET;\r
+ FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
+ }\r
+ else\r
+ FLAG_N = FLAG_X = FLAG_C = 0;\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+\r
+// FLAG_V &= res; /* Undefined V behavior part II */\r
+// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_8(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(sbcd, 8, mm, .)\r
+{\r
+ uint src = OPER_AY_PD_8();\r
+ uint ea = EA_AX_PD_8();\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
+\r
+// FLAG_V = ~res; /* Undefined V behavior */\r
+ FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */\r
+\r
+ if(res > 9)\r
+ res -= 6;\r
+ res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
+ if(res > 0x99)\r
+ {\r
+ res += 0xa0;\r
+ FLAG_X = FLAG_C = CFLAG_SET;\r
+ FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
+ }\r
+ else\r
+ FLAG_N = FLAG_X = FLAG_C = 0;\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+\r
+// FLAG_V &= res; /* Undefined V behavior part II */\r
+// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_8(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(st, 8, ., d)\r
+{\r
+ DY |= 0xff;\r
+}\r
+\r
+\r
+M68KMAKE_OP(st, 8, ., .)\r
+{\r
+ m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);\r
+}\r
+\r
+\r
+M68KMAKE_OP(sf, 8, ., d)\r
+{\r
+ DY &= 0xffffff00;\r
+}\r
+\r
+\r
+M68KMAKE_OP(sf, 8, ., .)\r
+{\r
+ m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);\r
+}\r
+\r
+\r
+M68KMAKE_OP(scc, 8, ., d)\r
+{\r
+ if(M68KMAKE_CC)\r
+ {\r
+ DY |= 0xff;\r
+ USE_CYCLES(CYC_SCC_R_TRUE);\r
+ return;\r
+ }\r
+ DY &= 0xffffff00;\r
+}\r
+\r
+\r
+M68KMAKE_OP(scc, 8, ., .)\r
+{\r
+ m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);\r
+}\r
+\r
+\r
+M68KMAKE_OP(stop, 0, ., .)\r
+{\r
+ if(FLAG_S)\r
+ {\r
+ uint new_sr = OPER_I_16();\r
+ m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
+ CPU_STOPPED |= STOP_LEVEL_STOP;\r
+ m68ki_set_sr(new_sr);\r
+ m68ki_remaining_cycles = 0;\r
+ return;\r
+ }\r
+ m68ki_exception_privilege_violation();\r
+}\r
+\r
+\r
+M68KMAKE_OP(sub, 8, er, d)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = MASK_OUT_ABOVE_8(DY);\r
+ uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(sub, 8, er, .)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = M68KMAKE_GET_OPER_AY_8;\r
+ uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(sub, 16, er, d)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = MASK_OUT_ABOVE_16(DY);\r
+ uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_V = VFLAG_SUB_16(src, dst, res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(sub, 16, er, a)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = MASK_OUT_ABOVE_16(AY);\r
+ uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_V = VFLAG_SUB_16(src, dst, res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(sub, 16, er, .)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = M68KMAKE_GET_OPER_AY_16;\r
+ uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_V = VFLAG_SUB_16(src, dst, res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(sub, 32, er, d)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = DY;\r
+ uint dst = *r_dst;\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+\r
+ *r_dst = FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(sub, 32, er, a)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = AY;\r
+ uint dst = *r_dst;\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+\r
+ *r_dst = FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(sub, 32, er, .)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = M68KMAKE_GET_OPER_AY_32;\r
+ uint dst = *r_dst;\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+\r
+ *r_dst = FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(sub, 8, re, .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint src = MASK_OUT_ABOVE_8(DX);\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+\r
+ m68ki_write_8(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(sub, 16, re, .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint src = MASK_OUT_ABOVE_16(DX);\r
+ uint dst = m68ki_read_16(ea);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_V = VFLAG_SUB_16(src, dst, res);\r
+\r
+ m68ki_write_16(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(sub, 32, re, .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint src = DX;\r
+ uint dst = m68ki_read_32(ea);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+\r
+ m68ki_write_32(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(suba, 16, ., d)\r
+{\r
+ uint* r_dst = &AX;\r
+\r
+ *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));\r
+}\r
+\r
+\r
+M68KMAKE_OP(suba, 16, ., a)\r
+{\r
+ uint* r_dst = &AX;\r
+\r
+ *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));\r
+}\r
+\r
+\r
+M68KMAKE_OP(suba, 16, ., .)\r
+{\r
+ uint* r_dst = &AX;\r
+\r
+ *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(M68KMAKE_GET_OPER_AY_16));\r
+}\r
+\r
+\r
+M68KMAKE_OP(suba, 32, ., d)\r
+{\r
+ uint* r_dst = &AX;\r
+\r
+ *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);\r
+}\r
+\r
+\r
+M68KMAKE_OP(suba, 32, ., a)\r
+{\r
+ uint* r_dst = &AX;\r
+\r
+ *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);\r
+}\r
+\r
+\r
+M68KMAKE_OP(suba, 32, ., .)\r
+{\r
+ uint* r_dst = &AX;\r
+\r
+ *r_dst = MASK_OUT_ABOVE_32(*r_dst - M68KMAKE_GET_OPER_AY_32);\r
+}\r
+\r
+\r
+M68KMAKE_OP(subi, 8, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint src = OPER_I_8();\r
+ uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(subi, 8, ., .)\r
+{\r
+ uint src = OPER_I_8();\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+\r
+ m68ki_write_8(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(subi, 16, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint src = OPER_I_16();\r
+ uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_V = VFLAG_SUB_16(src, dst, res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(subi, 16, ., .)\r
+{\r
+ uint src = OPER_I_16();\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint dst = m68ki_read_16(ea);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_V = VFLAG_SUB_16(src, dst, res);\r
+\r
+ m68ki_write_16(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(subi, 32, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint src = OPER_I_32();\r
+ uint dst = *r_dst;\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+\r
+ *r_dst = FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(subi, 32, ., .)\r
+{\r
+ uint src = OPER_I_32();\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint dst = m68ki_read_32(ea);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+\r
+ m68ki_write_32(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(subq, 8, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(subq, 8, ., .)\r
+{\r
+ uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_8(res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+\r
+ m68ki_write_8(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(subq, 16, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_V = VFLAG_SUB_16(src, dst, res);\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(subq, 16, ., a)\r
+{\r
+ uint* r_dst = &AY;\r
+\r
+ *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));\r
+}\r
+\r
+\r
+M68KMAKE_OP(subq, 16, ., .)\r
+{\r
+ uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint ea = M68KMAKE_GET_EA_AY_16;\r
+ uint dst = m68ki_read_16(ea);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_16(res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_V = VFLAG_SUB_16(src, dst, res);\r
+\r
+ m68ki_write_16(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(subq, 32, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+ uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint dst = *r_dst;\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+\r
+ *r_dst = FLAG_Z;\r
+}\r
+\r
+\r
+M68KMAKE_OP(subq, 32, ., a)\r
+{\r
+ uint* r_dst = &AY;\r
+\r
+ *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));\r
+}\r
+\r
+\r
+M68KMAKE_OP(subq, 32, ., .)\r
+{\r
+ uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
+ uint ea = M68KMAKE_GET_EA_AY_32;\r
+ uint dst = m68ki_read_32(ea);\r
+ uint res = dst - src;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = MASK_OUT_ABOVE_32(res);\r
+ FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+\r
+ m68ki_write_32(ea, FLAG_Z);\r
+}\r
+\r
+\r
+M68KMAKE_OP(subx, 8, rr, .)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = MASK_OUT_ABOVE_8(DY);\r
+ uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
+ uint res = dst - src - XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+ FLAG_Z |= res;\r
+\r
+ *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
+}\r
+\r
+\r
+M68KMAKE_OP(subx, 16, rr, .)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = MASK_OUT_ABOVE_16(DY);\r
+ uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
+ uint res = dst - src - XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_V = VFLAG_SUB_16(src, dst, res);\r
+\r
+ res = MASK_OUT_ABOVE_16(res);\r
+ FLAG_Z |= res;\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
+}\r
+\r
+\r
+M68KMAKE_OP(subx, 32, rr, .)\r
+{\r
+ uint* r_dst = &DX;\r
+ uint src = DY;\r
+ uint dst = *r_dst;\r
+ uint res = dst - src - XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+\r
+ res = MASK_OUT_ABOVE_32(res);\r
+ FLAG_Z |= res;\r
+\r
+ *r_dst = res;\r
+}\r
+\r
+\r
+M68KMAKE_OP(subx, 8, mm, ax7)\r
+{\r
+ uint src = OPER_AY_PD_8();\r
+ uint ea = EA_A7_PD_8();\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = dst - src - XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_8(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(subx, 8, mm, ay7)\r
+{\r
+ uint src = OPER_A7_PD_8();\r
+ uint ea = EA_AX_PD_8();\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = dst - src - XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_8(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(subx, 8, mm, axy7)\r
+{\r
+ uint src = OPER_A7_PD_8();\r
+ uint ea = EA_A7_PD_8();\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = dst - src - XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_8(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(subx, 8, mm, .)\r
+{\r
+ uint src = OPER_AY_PD_8();\r
+ uint ea = EA_AX_PD_8();\r
+ uint dst = m68ki_read_8(ea);\r
+ uint res = dst - src - XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_X = FLAG_C = CFLAG_8(res);\r
+ FLAG_V = VFLAG_SUB_8(src, dst, res);\r
+\r
+ res = MASK_OUT_ABOVE_8(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_8(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(subx, 16, mm, .)\r
+{\r
+ uint src = OPER_AY_PD_16();\r
+ uint ea = EA_AX_PD_16();\r
+ uint dst = m68ki_read_16(ea);\r
+ uint res = dst - src - XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_X = FLAG_C = CFLAG_16(res);\r
+ FLAG_V = VFLAG_SUB_16(src, dst, res);\r
+\r
+ res = MASK_OUT_ABOVE_16(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_16(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(subx, 32, mm, .)\r
+{\r
+ uint src = OPER_AY_PD_32();\r
+ uint ea = EA_AX_PD_32();\r
+ uint dst = m68ki_read_32(ea);\r
+ uint res = dst - src - XFLAG_AS_1();\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
+ FLAG_V = VFLAG_SUB_32(src, dst, res);\r
+\r
+ res = MASK_OUT_ABOVE_32(res);\r
+ FLAG_Z |= res;\r
+\r
+ m68ki_write_32(ea, res);\r
+}\r
+\r
+\r
+M68KMAKE_OP(swap, 32, ., .)\r
+{\r
+ uint* r_dst = &DY;\r
+\r
+ FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);\r
+ *r_dst = (*r_dst>>16) | FLAG_Z;\r
+\r
+ FLAG_Z = *r_dst;\r
+ FLAG_N = NFLAG_32(*r_dst);\r
+ FLAG_C = CFLAG_CLEAR;\r
+ FLAG_V = VFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(tas, 8, ., d)\r
+{\r
+ uint* r_dst = &DY;\r
+\r
+ FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);\r
+ FLAG_N = NFLAG_8(*r_dst);\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ *r_dst |= 0x80;\r
+}\r
+\r
+\r
+M68KMAKE_OP(tas, 8, ., .)\r
+{\r
+ uint ea = M68KMAKE_GET_EA_AY_8;\r
+ uint dst = m68ki_read_8(ea);\r
+\r
+ FLAG_Z = dst;\r
+ FLAG_N = NFLAG_8(dst);\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+// m68ki_write_8(ea, dst | 0x80); // notaz: genesis, but only to mem\r
+}\r
+\r
+\r
+M68KMAKE_OP(trap, 0, ., .)\r
+{\r
+ /* Trap#n stacks exception frame type 0 */\r
+ m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */\r
+}\r
+\r
+\r
+M68KMAKE_OP(trapt, 0, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(trapt, 16, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(trapt, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(trapf, 0, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(trapf, 16, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ REG_PC += 2;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(trapf, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ REG_PC += 4;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(trapcc, 0, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ if(M68KMAKE_CC)\r
+ m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(trapcc, 16, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ if(M68KMAKE_CC)\r
+ {\r
+ m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
+ return;\r
+ }\r
+ REG_PC += 2;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(trapcc, 32, ., .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ if(M68KMAKE_CC)\r
+ {\r
+ m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
+ return;\r
+ }\r
+ REG_PC += 4;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(trapv, 0, ., .)\r
+{\r
+ if(COND_VC())\r
+ {\r
+ return;\r
+ }\r
+ m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
+}\r
+\r
+\r
+M68KMAKE_OP(tst, 8, ., d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_8(DY);\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(tst, 8, ., .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_8;\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(tst, 8, ., pcdi)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint res = OPER_PCDI_8();\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(tst, 8, ., pcix)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint res = OPER_PCIX_8();\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(tst, 8, ., i)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint res = OPER_I_8();\r
+\r
+ FLAG_N = NFLAG_8(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(tst, 16, ., d)\r
+{\r
+ uint res = MASK_OUT_ABOVE_16(DY);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(tst, 16, ., a)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint res = MAKE_INT_16(AY);\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(tst, 16, ., .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_16;\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(tst, 16, ., pcdi)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint res = OPER_PCDI_16();\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(tst, 16, ., pcix)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint res = OPER_PCIX_16();\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(tst, 16, ., i)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint res = OPER_I_16();\r
+\r
+ FLAG_N = NFLAG_16(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(tst, 32, ., d)\r
+{\r
+ uint res = DY;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(tst, 32, ., a)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint res = AY;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(tst, 32, ., .)\r
+{\r
+ uint res = M68KMAKE_GET_OPER_AY_32;\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+}\r
+\r
+\r
+M68KMAKE_OP(tst, 32, ., pcdi)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint res = OPER_PCDI_32();\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(tst, 32, ., pcix)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint res = OPER_PCIX_32();\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(tst, 32, ., i)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint res = OPER_I_32();\r
+\r
+ FLAG_N = NFLAG_32(res);\r
+ FLAG_Z = res;\r
+ FLAG_V = VFLAG_CLEAR;\r
+ FLAG_C = CFLAG_CLEAR;\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(unlk, 32, ., a7)\r
+{\r
+ REG_A[7] = m68ki_read_32(REG_A[7]);\r
+}\r
+\r
+\r
+M68KMAKE_OP(unlk, 32, ., .)\r
+{\r
+ uint* r_dst = &AY;\r
+\r
+ REG_A[7] = *r_dst;\r
+ *r_dst = m68ki_pull_32();\r
+}\r
+\r
+\r
+M68KMAKE_OP(unpk, 16, rr, .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ /* Note: DX and DY are reversed in Motorola's docs */\r
+ uint src = DY;\r
+ uint* r_dst = &DX;\r
+\r
+ *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(unpk, 16, mm, ax7)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ /* Note: AX and AY are reversed in Motorola's docs */\r
+ uint src = OPER_AY_PD_8();\r
+ uint ea_dst;\r
+\r
+ src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
+ ea_dst = EA_A7_PD_8();\r
+ m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
+ ea_dst = EA_A7_PD_8();\r
+ m68ki_write_8(ea_dst, src & 0xff);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(unpk, 16, mm, ay7)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ /* Note: AX and AY are reversed in Motorola's docs */\r
+ uint src = OPER_A7_PD_8();\r
+ uint ea_dst;\r
+\r
+ src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
+ ea_dst = EA_AX_PD_8();\r
+ m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
+ ea_dst = EA_AX_PD_8();\r
+ m68ki_write_8(ea_dst, src & 0xff);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(unpk, 16, mm, axy7)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ uint src = OPER_A7_PD_8();\r
+ uint ea_dst;\r
+\r
+ src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
+ ea_dst = EA_A7_PD_8();\r
+ m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
+ ea_dst = EA_A7_PD_8();\r
+ m68ki_write_8(ea_dst, src & 0xff);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+M68KMAKE_OP(unpk, 16, mm, .)\r
+{\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ /* Note: AX and AY are reversed in Motorola's docs */\r
+ uint src = OPER_AY_PD_8();\r
+ uint ea_dst;\r
+\r
+ src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
+ ea_dst = EA_AX_PD_8();\r
+ m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
+ ea_dst = EA_AX_PD_8();\r
+ m68ki_write_8(ea_dst, src & 0xff);\r
+ return;\r
+ }\r
+ m68ki_exception_illegal();\r
+}\r
+\r
+\r
+\r
+XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
+M68KMAKE_END\r
notaz.gp2x.de / picodrive.git / blobdiff