--- /dev/null
+#include <stdio.h>\r
+/* ======================================================================== */\r
+/* ========================= LICENSING & COPYRIGHT ======================== */\r
+/* ======================================================================== */\r
+/*\r
+ * MUSASHI\r
+ * Version 3.3\r
+ *\r
+ * A portable Motorola M680x0 processor emulation engine.\r
+ * Copyright 1998-2001 Karl Stenerud. All rights reserved.\r
+ *\r
+ * This code may be freely used for non-commercial purposes as long as this\r
+ * copyright notice remains unaltered in the source code and any binary files\r
+ * containing this code in compiled form.\r
+ *\r
+ * All other lisencing terms must be negotiated with the author\r
+ * (Karl Stenerud).\r
+ *\r
+ * The latest version of this code can be obtained at:\r
+ * http://kstenerud.cjb.net\r
+ */\r
+\r
+\r
+\r
+\r
+#ifndef M68KCPU__HEADER\r
+#define M68KCPU__HEADER\r
+\r
+// notaz: something's missing this\r
+#ifndef UINT16\r
+#define UINT32 unsigned int\r
+#define UINT16 unsigned short\r
+#define UINT8 unsigned char\r
+#endif\r
+\r
+#include "m68k.h"\r
+#include <limits.h>\r
+\r
+#if M68K_EMULATE_ADDRESS_ERROR\r
+#include <setjmp.h>\r
+#endif /* M68K_EMULATE_ADDRESS_ERROR */\r
+\r
+/* ======================================================================== */\r
+/* ==================== ARCHITECTURE-DEPENDANT DEFINES ==================== */\r
+/* ======================================================================== */\r
+\r
+/* Check for > 32bit sizes */\r
+#if UINT_MAX > 0xffffffff\r
+ #define M68K_INT_GT_32_BIT 1\r
+#else\r
+ #define M68K_INT_GT_32_BIT 0\r
+#endif\r
+\r
+/* Data types used in this emulation core */\r
+#undef sint8\r
+#undef sint16\r
+#undef sint32\r
+#undef sint64\r
+#undef uint8\r
+#undef uint16\r
+#undef uint32\r
+#undef uint64\r
+#undef sint\r
+#undef uint\r
+\r
+#define sint8 signed char /* ASG: changed from char to signed char */\r
+#define sint16 signed short\r
+#define sint32 signed long\r
+#define uint8 unsigned char\r
+#define uint16 unsigned short\r
+#define uint32 unsigned long\r
+\r
+/* signed and unsigned int must be at least 32 bits wide */\r
+#define sint signed int\r
+#define uint unsigned int\r
+\r
+\r
+#if M68K_USE_64_BIT\r
+#define sint64 signed long long\r
+#define uint64 unsigned long long\r
+#else\r
+#define sint64 sint32\r
+#define uint64 uint32\r
+#endif /* M68K_USE_64_BIT */\r
+\r
+\r
+\r
+/* Allow for architectures that don't have 8-bit sizes */\r
+#if UCHAR_MAX == 0xff\r
+ #define MAKE_INT_8(A) (sint8)(A)\r
+#else\r
+ #undef sint8\r
+ #define sint8 signed int\r
+ #undef uint8\r
+ #define uint8 unsigned int\r
+ INLINE sint MAKE_INT_8(uint value)\r
+ {\r
+ return (value & 0x80) ? value | ~0xff : value & 0xff;\r
+ }\r
+#endif /* UCHAR_MAX == 0xff */\r
+\r
+\r
+/* Allow for architectures that don't have 16-bit sizes */\r
+#if USHRT_MAX == 0xffff\r
+ #define MAKE_INT_16(A) (sint16)(A)\r
+#else\r
+ #undef sint16\r
+ #define sint16 signed int\r
+ #undef uint16\r
+ #define uint16 unsigned int\r
+ INLINE sint MAKE_INT_16(uint value)\r
+ {\r
+ return (value & 0x8000) ? value | ~0xffff : value & 0xffff;\r
+ }\r
+#endif /* USHRT_MAX == 0xffff */\r
+\r
+\r
+/* Allow for architectures that don't have 32-bit sizes */\r
+#if ULONG_MAX == 0xffffffff\r
+ #define MAKE_INT_32(A) (sint32)(A)\r
+#else\r
+ #undef sint32\r
+ #define sint32 signed int\r
+ #undef uint32\r
+ #define uint32 unsigned int\r
+ INLINE sint MAKE_INT_32(uint value)\r
+ {\r
+ return (value & 0x80000000) ? value | ~0xffffffff : value & 0xffffffff;\r
+ }\r
+#endif /* ULONG_MAX == 0xffffffff */\r
+\r
+// notaz\r
+INLINE sint32 MAKE_INT_24(uint value)\r
+{\r
+ return (value & 0x800000) ? value | ~0xffffff : value & 0xffffff;\r
+}\r
+\r
+\r
+\r
+/* ======================================================================== */\r
+/* ============================ GENERAL DEFINES =========================== */\r
+/* ======================================================================== */\r
+\r
+/* Exception Vectors handled by emulation */\r
+#define EXCEPTION_BUS_ERROR 2 /* This one is not emulated! */\r
+#define EXCEPTION_ADDRESS_ERROR 3 /* This one is partially emulated (doesn't stack a proper frame yet) */\r
+#define EXCEPTION_ILLEGAL_INSTRUCTION 4\r
+#define EXCEPTION_ZERO_DIVIDE 5\r
+#define EXCEPTION_CHK 6\r
+#define EXCEPTION_TRAPV 7\r
+#define EXCEPTION_PRIVILEGE_VIOLATION 8\r
+#define EXCEPTION_TRACE 9\r
+#define EXCEPTION_1010 10\r
+#define EXCEPTION_1111 11\r
+#define EXCEPTION_FORMAT_ERROR 14\r
+#define EXCEPTION_UNINITIALIZED_INTERRUPT 15\r
+#define EXCEPTION_SPURIOUS_INTERRUPT 24\r
+#define EXCEPTION_INTERRUPT_AUTOVECTOR 24\r
+#define EXCEPTION_TRAP_BASE 32\r
+\r
+/* Function codes set by CPU during data/address bus activity */\r
+#define FUNCTION_CODE_USER_DATA 1\r
+#define FUNCTION_CODE_USER_PROGRAM 2\r
+#define FUNCTION_CODE_SUPERVISOR_DATA 5\r
+#define FUNCTION_CODE_SUPERVISOR_PROGRAM 6\r
+#define FUNCTION_CODE_CPU_SPACE 7\r
+\r
+/* CPU types for deciding what to emulate */\r
+#define CPU_TYPE_000 1\r
+#define CPU_TYPE_008 2\r
+#define CPU_TYPE_010 4\r
+#define CPU_TYPE_EC020 8\r
+#define CPU_TYPE_020 16\r
+#define CPU_TYPE_040 32\r
+\r
+/* Different ways to stop the CPU */\r
+#define STOP_LEVEL_STOP 1\r
+#define STOP_LEVEL_HALT 2\r
+\r
+/* Used for 68000 address error processing */\r
+#define INSTRUCTION_YES 0\r
+#define INSTRUCTION_NO 0x08\r
+#define MODE_READ 0x10\r
+#define MODE_WRITE 0\r
+\r
+#define RUN_MODE_NORMAL 0\r
+#define RUN_MODE_BERR_AERR_RESET 1\r
+\r
+#ifndef NULL\r
+#define NULL ((void*)0)\r
+#endif\r
+\r
+/* ======================================================================== */\r
+/* ================================ MACROS ================================ */\r
+/* ======================================================================== */\r
+\r
+\r
+/* ---------------------------- General Macros ---------------------------- */\r
+\r
+/* Bit Isolation Macros */\r
+#define BIT_0(A) ((A) & 0x00000001)\r
+#define BIT_1(A) ((A) & 0x00000002)\r
+#define BIT_2(A) ((A) & 0x00000004)\r
+#define BIT_3(A) ((A) & 0x00000008)\r
+#define BIT_4(A) ((A) & 0x00000010)\r
+#define BIT_5(A) ((A) & 0x00000020)\r
+#define BIT_6(A) ((A) & 0x00000040)\r
+#define BIT_7(A) ((A) & 0x00000080)\r
+#define BIT_8(A) ((A) & 0x00000100)\r
+#define BIT_9(A) ((A) & 0x00000200)\r
+#define BIT_A(A) ((A) & 0x00000400)\r
+#define BIT_B(A) ((A) & 0x00000800)\r
+#define BIT_C(A) ((A) & 0x00001000)\r
+#define BIT_D(A) ((A) & 0x00002000)\r
+#define BIT_E(A) ((A) & 0x00004000)\r
+#define BIT_F(A) ((A) & 0x00008000)\r
+#define BIT_10(A) ((A) & 0x00010000)\r
+#define BIT_11(A) ((A) & 0x00020000)\r
+#define BIT_12(A) ((A) & 0x00040000)\r
+#define BIT_13(A) ((A) & 0x00080000)\r
+#define BIT_14(A) ((A) & 0x00100000)\r
+#define BIT_15(A) ((A) & 0x00200000)\r
+#define BIT_16(A) ((A) & 0x00400000)\r
+#define BIT_17(A) ((A) & 0x00800000)\r
+#define BIT_18(A) ((A) & 0x01000000)\r
+#define BIT_19(A) ((A) & 0x02000000)\r
+#define BIT_1A(A) ((A) & 0x04000000)\r
+#define BIT_1B(A) ((A) & 0x08000000)\r
+#define BIT_1C(A) ((A) & 0x10000000)\r
+#define BIT_1D(A) ((A) & 0x20000000)\r
+#define BIT_1E(A) ((A) & 0x40000000)\r
+#define BIT_1F(A) ((A) & 0x80000000)\r
+\r
+/* Get the most significant bit for specific sizes */\r
+#define GET_MSB_8(A) ((A) & 0x80)\r
+#define GET_MSB_9(A) ((A) & 0x100)\r
+#define GET_MSB_16(A) ((A) & 0x8000)\r
+#define GET_MSB_17(A) ((A) & 0x10000)\r
+#define GET_MSB_32(A) ((A) & 0x80000000)\r
+#if M68K_USE_64_BIT\r
+#define GET_MSB_33(A) ((A) & 0x100000000)\r
+#endif /* M68K_USE_64_BIT */\r
+\r
+/* Isolate nibbles */\r
+#define LOW_NIBBLE(A) ((A) & 0x0f)\r
+#define HIGH_NIBBLE(A) ((A) & 0xf0)\r
+\r
+/* These are used to isolate 8, 16, and 32 bit sizes */\r
+#define MASK_OUT_ABOVE_2(A) ((A) & 3)\r
+#define MASK_OUT_ABOVE_8(A) ((A) & 0xff)\r
+#define MASK_OUT_ABOVE_16(A) ((A) & 0xffff)\r
+#define MASK_OUT_BELOW_2(A) ((A) & ~3)\r
+#define MASK_OUT_BELOW_8(A) ((A) & ~0xff)\r
+#define MASK_OUT_BELOW_16(A) ((A) & ~0xffff)\r
+\r
+/* No need to mask if we are 32 bit */\r
+#if M68K_INT_GT_32_BIT || M68K_USE_64_BIT\r
+ #define MASK_OUT_ABOVE_32(A) ((A) & 0xffffffff)\r
+ #define MASK_OUT_BELOW_32(A) ((A) & ~0xffffffff)\r
+#else\r
+ #define MASK_OUT_ABOVE_32(A) (A)\r
+ #define MASK_OUT_BELOW_32(A) 0\r
+#endif /* M68K_INT_GT_32_BIT || M68K_USE_64_BIT */\r
+\r
+/* Simulate address lines of 68k family */\r
+#define ADDRESS_68K(A) ((A)&CPU_ADDRESS_MASK)\r
+\r
+\r
+/* Shift & Rotate Macros. */\r
+#define LSL(A, C) ((A) << (C))\r
+#define LSR(A, C) ((A) >> (C))\r
+\r
+/* Some > 32-bit optimizations */\r
+#if M68K_INT_GT_32_BIT\r
+ /* Shift left and right */\r
+ #define LSR_32(A, C) ((A) >> (C))\r
+ #define LSL_32(A, C) ((A) << (C))\r
+#else\r
+ /* We have to do this because the morons at ANSI decided that shifts\r
+ * by >= data size are undefined.\r
+ */\r
+ #define LSR_32(A, C) ((C) < 32 ? (A) >> (C) : 0)\r
+ #define LSL_32(A, C) ((C) < 32 ? (A) << (C) : 0)\r
+#endif /* M68K_INT_GT_32_BIT */\r
+\r
+#if M68K_USE_64_BIT\r
+ #define LSL_32_64(A, C) ((A) << (C))\r
+ #define LSR_32_64(A, C) ((A) >> (C))\r
+ #define ROL_33_64(A, C) (LSL_32_64(A, C) | LSR_32_64(A, 33-(C)))\r
+ #define ROR_33_64(A, C) (LSR_32_64(A, C) | LSL_32_64(A, 33-(C)))\r
+#endif /* M68K_USE_64_BIT */\r
+\r
+#define ROL_8(A, C) MASK_OUT_ABOVE_8(LSL(A, C) | LSR(A, 8-(C)))\r
+#define ROL_9(A, C) (LSL(A, C) | LSR(A, 9-(C)))\r
+#define ROL_16(A, C) MASK_OUT_ABOVE_16(LSL(A, C) | LSR(A, 16-(C)))\r
+#define ROL_17(A, C) (LSL(A, C) | LSR(A, 17-(C)))\r
+#define ROL_32(A, C) MASK_OUT_ABOVE_32(LSL_32(A, C) | LSR_32(A, 32-(C)))\r
+#define ROL_33(A, C) (LSL_32(A, C) | LSR_32(A, 33-(C)))\r
+\r
+#define ROR_8(A, C) MASK_OUT_ABOVE_8(LSR(A, C) | LSL(A, 8-(C)))\r
+#define ROR_9(A, C) (LSR(A, C) | LSL(A, 9-(C)))\r
+#define ROR_16(A, C) MASK_OUT_ABOVE_16(LSR(A, C) | LSL(A, 16-(C)))\r
+#define ROR_17(A, C) (LSR(A, C) | LSL(A, 17-(C)))\r
+#define ROR_32(A, C) MASK_OUT_ABOVE_32(LSR_32(A, C) | LSL_32(A, 32-(C)))\r
+#define ROR_33(A, C) (LSR_32(A, C) | LSL_32(A, 33-(C)))\r
+\r
+\r
+\r
+/* ------------------------------ CPU Access ------------------------------ */\r
+\r
+/* Access the CPU registers */\r
+#define CPU_TYPE m68ki_cpu.cpu_type\r
+\r
+#define REG_DA m68ki_cpu.dar /* easy access to data and address regs */\r
+#define REG_D m68ki_cpu.dar\r
+#define REG_A (m68ki_cpu.dar+8)\r
+#define REG_PPC m68ki_cpu.ppc\r
+#define REG_PC m68ki_cpu.pc\r
+#define REG_SP_BASE m68ki_cpu.sp\r
+#define REG_USP m68ki_cpu.sp[0]\r
+#define REG_ISP m68ki_cpu.sp[4]\r
+#define REG_MSP m68ki_cpu.sp[6]\r
+#define REG_SP m68ki_cpu.dar[15]\r
+#define REG_VBR m68ki_cpu.vbr\r
+#define REG_SFC m68ki_cpu.sfc\r
+#define REG_DFC m68ki_cpu.dfc\r
+#define REG_CACR m68ki_cpu.cacr\r
+#define REG_CAAR m68ki_cpu.caar\r
+#define REG_IR m68ki_cpu.ir\r
+\r
+#define FLAG_T1 m68ki_cpu.t1_flag\r
+#define FLAG_T0 m68ki_cpu.t0_flag\r
+#define FLAG_S m68ki_cpu.s_flag\r
+#define FLAG_M m68ki_cpu.m_flag\r
+#define FLAG_X m68ki_cpu.x_flag\r
+#define FLAG_N m68ki_cpu.n_flag\r
+#define FLAG_Z m68ki_cpu.not_z_flag\r
+#define FLAG_V m68ki_cpu.v_flag\r
+#define FLAG_C m68ki_cpu.c_flag\r
+#define FLAG_INT_MASK m68ki_cpu.int_mask\r
+\r
+#define CPU_INT_LEVEL m68ki_cpu.int_level /* ASG: changed from CPU_INTS_PENDING */\r
+#define CPU_INT_CYCLES m68ki_cpu.int_cycles /* ASG */\r
+#define CPU_STOPPED m68ki_cpu.stopped\r
+#define CPU_PREF_ADDR m68ki_cpu.pref_addr\r
+#define CPU_PREF_DATA m68ki_cpu.pref_data\r
+#define CPU_ADDRESS_MASK m68ki_cpu.address_mask\r
+#define CPU_SR_MASK m68ki_cpu.sr_mask\r
+#define CPU_INSTR_MODE m68ki_cpu.instr_mode\r
+#define CPU_RUN_MODE m68ki_cpu.run_mode\r
+\r
+#define CYC_INSTRUCTION m68ki_cpu.cyc_instruction\r
+#define CYC_EXCEPTION m68ki_cpu.cyc_exception\r
+#define CYC_BCC_NOTAKE_B m68ki_cpu.cyc_bcc_notake_b\r
+#define CYC_BCC_NOTAKE_W m68ki_cpu.cyc_bcc_notake_w\r
+#define CYC_DBCC_F_NOEXP m68ki_cpu.cyc_dbcc_f_noexp\r
+#define CYC_DBCC_F_EXP m68ki_cpu.cyc_dbcc_f_exp\r
+#define CYC_SCC_R_TRUE m68ki_cpu.cyc_scc_r_true\r
+#define CYC_MOVEM_W m68ki_cpu.cyc_movem_w\r
+#define CYC_MOVEM_L m68ki_cpu.cyc_movem_l\r
+#define CYC_SHIFT m68ki_cpu.cyc_shift\r
+#define CYC_RESET m68ki_cpu.cyc_reset\r
+\r
+\r
+#define CALLBACK_INT_ACK m68ki_cpu.int_ack_callback\r
+#define CALLBACK_BKPT_ACK m68ki_cpu.bkpt_ack_callback\r
+#define CALLBACK_RESET_INSTR m68ki_cpu.reset_instr_callback\r
+#define CALLBACK_CMPILD_INSTR m68ki_cpu.cmpild_instr_callback\r
+#define CALLBACK_RTE_INSTR m68ki_cpu.rte_instr_callback\r
+#define CALLBACK_PC_CHANGED m68ki_cpu.pc_changed_callback\r
+#define CALLBACK_SET_FC m68ki_cpu.set_fc_callback\r
+#define CALLBACK_INSTR_HOOK m68ki_cpu.instr_hook_callback\r
+\r
+\r
+\r
+/* ----------------------------- Configuration ---------------------------- */\r
+\r
+/* These defines are dependant on the configuration defines in m68kconf.h */\r
+\r
+/* Disable certain comparisons if we're not using all CPU types */\r
+#if M68K_EMULATE_040\r
+ #define CPU_TYPE_IS_040_PLUS(A) ((A) & CPU_TYPE_040)\r
+ #define CPU_TYPE_IS_040_LESS(A) 1\r
+#else\r
+ #define CPU_TYPE_IS_040_PLUS(A) 0\r
+ #define CPU_TYPE_IS_040_LESS(A) 1\r
+#endif\r
+\r
+#if M68K_EMULATE_020\r
+ #define CPU_TYPE_IS_020_PLUS(A) ((A) & (CPU_TYPE_020 | CPU_TYPE_040))\r
+ #define CPU_TYPE_IS_020_LESS(A) 1\r
+#else\r
+ #define CPU_TYPE_IS_020_PLUS(A) 0\r
+ #define CPU_TYPE_IS_020_LESS(A) 1\r
+#endif\r
+\r
+#if M68K_EMULATE_EC020\r
+ #define CPU_TYPE_IS_EC020_PLUS(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_040))\r
+ #define CPU_TYPE_IS_EC020_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010 | CPU_TYPE_EC020))\r
+#else\r
+ #define CPU_TYPE_IS_EC020_PLUS(A) CPU_TYPE_IS_020_PLUS(A)\r
+ #define CPU_TYPE_IS_EC020_LESS(A) CPU_TYPE_IS_020_LESS(A)\r
+#endif\r
+\r
+#if M68K_EMULATE_010\r
+ #define CPU_TYPE_IS_010(A) ((A) == CPU_TYPE_010)\r
+ #define CPU_TYPE_IS_010_PLUS(A) ((A) & (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_040))\r
+ #define CPU_TYPE_IS_010_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010))\r
+#else\r
+ #define CPU_TYPE_IS_010(A) 0\r
+ #define CPU_TYPE_IS_010_PLUS(A) CPU_TYPE_IS_EC020_PLUS(A)\r
+ #define CPU_TYPE_IS_010_LESS(A) CPU_TYPE_IS_EC020_LESS(A)\r
+#endif\r
+\r
+#if M68K_EMULATE_020 || M68K_EMULATE_EC020\r
+ #define CPU_TYPE_IS_020_VARIANT(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020))\r
+#else\r
+ #define CPU_TYPE_IS_020_VARIANT(A) 0\r
+#endif\r
+\r
+#if M68K_EMULATE_040 || M68K_EMULATE_020 || M68K_EMULATE_EC020 || M68K_EMULATE_010\r
+ #define CPU_TYPE_IS_000(A) ((A) == CPU_TYPE_000 || (A) == CPU_TYPE_008)\r
+#else\r
+ #define CPU_TYPE_IS_000(A) 1\r
+#endif\r
+\r
+\r
+#if !M68K_SEPARATE_READS\r
+#define m68k_read_immediate_16(A) m68ki_read_program_16(A)\r
+#define m68k_read_immediate_32(A) m68ki_read_program_32(A)\r
+\r
+#define m68k_read_pcrelative_8(A) m68ki_read_program_8(A)\r
+#define m68k_read_pcrelative_16(A) m68ki_read_program_16(A)\r
+#define m68k_read_pcrelative_32(A) m68ki_read_program_32(A)\r
+#endif /* M68K_SEPARATE_READS */\r
+\r
+\r
+/* Enable or disable callback functions */\r
+#if M68K_EMULATE_INT_ACK\r
+ #if M68K_EMULATE_INT_ACK == OPT_SPECIFY_HANDLER\r
+ #define m68ki_int_ack(A) M68K_INT_ACK_CALLBACK(A)\r
+ #else\r
+ #define m68ki_int_ack(A) CALLBACK_INT_ACK(A)\r
+ #endif\r
+#else\r
+ /* Default action is to used autovector mode, which is most common */\r
+ #define m68ki_int_ack(A) M68K_INT_ACK_AUTOVECTOR\r
+#endif /* M68K_EMULATE_INT_ACK */\r
+\r
+#if M68K_EMULATE_BKPT_ACK\r
+ #if M68K_EMULATE_BKPT_ACK == OPT_SPECIFY_HANDLER\r
+ #define m68ki_bkpt_ack(A) M68K_BKPT_ACK_CALLBACK(A)\r
+ #else\r
+ #define m68ki_bkpt_ack(A) CALLBACK_BKPT_ACK(A)\r
+ #endif\r
+#else\r
+ #define m68ki_bkpt_ack(A)\r
+#endif /* M68K_EMULATE_BKPT_ACK */\r
+\r
+#if M68K_EMULATE_RESET\r
+ #if M68K_EMULATE_RESET == OPT_SPECIFY_HANDLER\r
+ #define m68ki_output_reset() M68K_RESET_CALLBACK()\r
+ #else\r
+ #define m68ki_output_reset() CALLBACK_RESET_INSTR()\r
+ #endif\r
+#else\r
+ #define m68ki_output_reset()\r
+#endif /* M68K_EMULATE_RESET */\r
+\r
+#if M68K_CMPILD_HAS_CALLBACK\r
+ #if M68K_CMPILD_HAS_CALLBACK == OPT_SPECIFY_HANDLER\r
+ #define m68ki_cmpild_callback(v,r) M68K_CMPILD_CALLBACK(v,r)\r
+ #else\r
+ #define m68ki_cmpild_callback(v,r) CALLBACK_CMPILD_INSTR(v,r)\r
+ #endif\r
+#else\r
+ #define m68ki_cmpild_callback(v,r)\r
+#endif /* M68K_CMPILD_HAS_CALLBACK */\r
+\r
+#if M68K_RTE_HAS_CALLBACK\r
+ #if M68K_RTE_HAS_CALLBACK == OPT_SPECIFY_HANDLER\r
+ #define m68ki_rte_callback() M68K_RTE_CALLBACK()\r
+ #else\r
+ #define m68ki_rte_callback() CALLBACK_RTE_INSTR()\r
+ #endif\r
+#else\r
+ #define m68ki_rte_callback()\r
+#endif /* M68K_RTE_HAS_CALLBACK */\r
+\r
+#if M68K_INSTRUCTION_HOOK\r
+ #if M68K_INSTRUCTION_HOOK == OPT_SPECIFY_HANDLER\r
+ #define m68ki_instr_hook() M68K_INSTRUCTION_CALLBACK()\r
+ #else\r
+ #define m68ki_instr_hook() CALLBACK_INSTR_HOOK()\r
+ #endif\r
+#else\r
+ #define m68ki_instr_hook()\r
+#endif /* M68K_INSTRUCTION_HOOK */\r
+\r
+#if M68K_MONITOR_PC\r
+ #if M68K_MONITOR_PC == OPT_SPECIFY_HANDLER\r
+ #define m68ki_pc_changed(A) M68K_SET_PC_CALLBACK(ADDRESS_68K(A))\r
+ #else\r
+ #define m68ki_pc_changed(A) CALLBACK_PC_CHANGED(ADDRESS_68K(A))\r
+ #endif\r
+#else\r
+ #define m68ki_pc_changed(A)\r
+#endif /* M68K_MONITOR_PC */\r
+\r
+\r
+/* Enable or disable function code emulation */\r
+#if M68K_EMULATE_FC\r
+ #if M68K_EMULATE_FC == OPT_SPECIFY_HANDLER\r
+ #define m68ki_set_fc(A) M68K_SET_FC_CALLBACK(A)\r
+ #else\r
+ #define m68ki_set_fc(A) CALLBACK_SET_FC(A)\r
+ #endif\r
+ #define m68ki_use_data_space() m68ki_address_space = FUNCTION_CODE_USER_DATA\r
+ #define m68ki_use_program_space() m68ki_address_space = FUNCTION_CODE_USER_PROGRAM\r
+ #define m68ki_get_address_space() m68ki_address_space\r
+#else\r
+ #define m68ki_set_fc(A)\r
+ #define m68ki_use_data_space()\r
+ #define m68ki_use_program_space()\r
+ #define m68ki_get_address_space() FUNCTION_CODE_USER_DATA\r
+#endif /* M68K_EMULATE_FC */\r
+\r
+\r
+/* Enable or disable trace emulation */\r
+#if M68K_EMULATE_TRACE\r
+ /* Initiates trace checking before each instruction (t1) */\r
+ #define m68ki_trace_t1() m68ki_tracing = FLAG_T1\r
+ /* adds t0 to trace checking if we encounter change of flow */\r
+ #define m68ki_trace_t0() m68ki_tracing |= FLAG_T0\r
+ /* Clear all tracing */\r
+ #define m68ki_clear_trace() m68ki_tracing = 0\r
+ /* Cause a trace exception if we are tracing */\r
+ #define m68ki_exception_if_trace() if(m68ki_tracing) m68ki_exception_trace()\r
+#else\r
+ #define m68ki_trace_t1()\r
+ #define m68ki_trace_t0()\r
+ #define m68ki_clear_trace()\r
+ #define m68ki_exception_if_trace()\r
+#endif /* M68K_EMULATE_TRACE */\r
+\r
+\r
+\r
+/* Address error */\r
+#if M68K_EMULATE_ADDRESS_ERROR\r
+ #include <setjmp.h>\r
+ extern jmp_buf m68ki_aerr_trap;\r
+\r
+ #define m68ki_set_address_error_trap() \\r
+ if(setjmp(m68ki_aerr_trap) != 0) \\r
+ { \\r
+ m68ki_exception_address_error(); \\r
+ if(CPU_STOPPED) \\r
+ { \\r
+ SET_CYCLES(0); \\r
+ CPU_INT_CYCLES = 0; \\r
+ return m68ki_initial_cycles; \\r
+ } \\r
+ }\r
+\r
+ #define m68ki_check_address_error(ADDR, WRITE_MODE, FC) \\r
+ if((ADDR)&1) \\r
+ { \\r
+ m68ki_aerr_address = ADDR; \\r
+ m68ki_aerr_write_mode = WRITE_MODE; \\r
+ m68ki_aerr_fc = FC; \\r
+ longjmp(m68ki_aerr_trap, 1); \\r
+ }\r
+\r
+ #define m68ki_check_address_error_010_less(ADDR, WRITE_MODE, FC) \\r
+ if (CPU_TYPE_IS_010_LESS(CPU_TYPE)) \\r
+ { \\r
+ m68ki_check_address_error(ADDR, WRITE_MODE, FC) \\r
+ }\r
+#else\r
+ #define m68ki_set_address_error_trap()\r
+ #define m68ki_check_address_error(ADDR, WRITE_MODE, FC)\r
+ #define m68ki_check_address_error_010_less(ADDR, WRITE_MODE, FC)\r
+#endif /* M68K_ADDRESS_ERROR */\r
+\r
+/* Logging */\r
+#if M68K_LOG_ENABLE\r
+ #include <stdio.h>\r
+ extern FILE* M68K_LOG_FILEHANDLE\r
+ extern char* m68ki_cpu_names[];\r
+\r
+ #define M68K_DO_LOG(A) if(M68K_LOG_FILEHANDLE) fprintf A\r
+ #if M68K_LOG_1010_1111\r
+ #define M68K_DO_LOG_EMU(A) if(M68K_LOG_FILEHANDLE) fprintf A\r
+ #else\r
+ #define M68K_DO_LOG_EMU(A)\r
+ #endif\r
+#else\r
+ #define M68K_DO_LOG(A)\r
+ #define M68K_DO_LOG_EMU(A)\r
+#endif\r
+\r
+\r
+\r
+/* -------------------------- EA / Operand Access ------------------------- */\r
+\r
+/*\r
+ * The general instruction format follows this pattern:\r
+ * .... XXX. .... .YYY\r
+ * where XXX is register X and YYY is register Y\r
+ */\r
+/* Data Register Isolation */\r
+#define DX (REG_D[(REG_IR >> 9) & 7])\r
+#define DY (REG_D[REG_IR & 7])\r
+/* Address Register Isolation */\r
+#define AX (REG_A[(REG_IR >> 9) & 7])\r
+#define AY (REG_A[REG_IR & 7])\r
+\r
+\r
+/* Effective Address Calculations */\r
+#define EA_AY_AI_8() AY /* address register indirect */\r
+#define EA_AY_AI_16() EA_AY_AI_8()\r
+#define EA_AY_AI_32() EA_AY_AI_8()\r
+#define EA_AY_PI_8() (AY++) /* postincrement (size = byte) */\r
+#define EA_AY_PI_16() ((AY+=2)-2) /* postincrement (size = word) */\r
+#define EA_AY_PI_32() ((AY+=4)-4) /* postincrement (size = long) */\r
+#define EA_AY_PD_8() (--AY) /* predecrement (size = byte) */\r
+#define EA_AY_PD_16() (AY-=2) /* predecrement (size = word) */\r
+#define EA_AY_PD_32() (AY-=4) /* predecrement (size = long) */\r
+#define EA_AY_DI_8() (AY+MAKE_INT_16(m68ki_read_imm_16())) /* displacement */\r
+#define EA_AY_DI_16() EA_AY_DI_8()\r
+#define EA_AY_DI_32() EA_AY_DI_8()\r
+#define EA_AY_IX_8() m68ki_get_ea_ix(AY) /* indirect + index */\r
+#define EA_AY_IX_16() EA_AY_IX_8()\r
+#define EA_AY_IX_32() EA_AY_IX_8()\r
+\r
+#define EA_AX_AI_8() AX\r
+#define EA_AX_AI_16() EA_AX_AI_8()\r
+#define EA_AX_AI_32() EA_AX_AI_8()\r
+#define EA_AX_PI_8() (AX++)\r
+#define EA_AX_PI_16() ((AX+=2)-2)\r
+#define EA_AX_PI_32() ((AX+=4)-4)\r
+#define EA_AX_PD_8() (--AX)\r
+#define EA_AX_PD_16() (AX-=2)\r
+#define EA_AX_PD_32() (AX-=4)\r
+#define EA_AX_DI_8() (AX+MAKE_INT_16(m68ki_read_imm_16()))\r
+#define EA_AX_DI_16() EA_AX_DI_8()\r
+#define EA_AX_DI_32() EA_AX_DI_8()\r
+#define EA_AX_IX_8() m68ki_get_ea_ix(AX)\r
+#define EA_AX_IX_16() EA_AX_IX_8()\r
+#define EA_AX_IX_32() EA_AX_IX_8()\r
+\r
+#define EA_A7_PI_8() ((REG_A[7]+=2)-2)\r
+#define EA_A7_PD_8() (REG_A[7]-=2)\r
+\r
+#define EA_AW_8() MAKE_INT_16(m68ki_read_imm_16()) /* absolute word */\r
+#define EA_AW_16() EA_AW_8()\r
+#define EA_AW_32() EA_AW_8()\r
+#define EA_AL_8() m68ki_read_imm_32() /* absolute long */\r
+#define EA_AL_16() EA_AL_8()\r
+#define EA_AL_32() EA_AL_8()\r
+#define EA_PCDI_8() m68ki_get_ea_pcdi() /* pc indirect + displacement */\r
+#define EA_PCDI_16() EA_PCDI_8()\r
+#define EA_PCDI_32() EA_PCDI_8()\r
+#define EA_PCIX_8() m68ki_get_ea_pcix() /* pc indirect + index */\r
+#define EA_PCIX_16() EA_PCIX_8()\r
+#define EA_PCIX_32() EA_PCIX_8()\r
+\r
+\r
+#define OPER_I_8() m68ki_read_imm_8()\r
+#define OPER_I_16() m68ki_read_imm_16()\r
+#define OPER_I_32() m68ki_read_imm_32()\r
+\r
+\r
+\r
+/* --------------------------- Status Register ---------------------------- */\r
+\r
+/* Flag Calculation Macros */\r
+#define CFLAG_8(A) (A)\r
+#define CFLAG_16(A) ((A)>>8)\r
+\r
+#if M68K_INT_GT_32_BIT\r
+ #define CFLAG_ADD_32(S, D, R) ((R)>>24)\r
+ #define CFLAG_SUB_32(S, D, R) ((R)>>24)\r
+#else\r
+ #define CFLAG_ADD_32(S, D, R) (((S & D) | (~R & (S | D)))>>23)\r
+ #define CFLAG_SUB_32(S, D, R) (((S & R) | (~D & (S | R)))>>23)\r
+#endif /* M68K_INT_GT_32_BIT */\r
+\r
+#define VFLAG_ADD_8(S, D, R) ((S^R) & (D^R))\r
+#define VFLAG_ADD_16(S, D, R) (((S^R) & (D^R))>>8)\r
+#define VFLAG_ADD_32(S, D, R) (((S^R) & (D^R))>>24)\r
+\r
+#define VFLAG_SUB_8(S, D, R) ((S^D) & (R^D))\r
+#define VFLAG_SUB_16(S, D, R) (((S^D) & (R^D))>>8)\r
+#define VFLAG_SUB_32(S, D, R) (((S^D) & (R^D))>>24)\r
+\r
+#define NFLAG_8(A) (A)\r
+#define NFLAG_16(A) ((A)>>8)\r
+#define NFLAG_32(A) ((A)>>24)\r
+#define NFLAG_64(A) ((A)>>56)\r
+\r
+#define ZFLAG_8(A) MASK_OUT_ABOVE_8(A)\r
+#define ZFLAG_16(A) MASK_OUT_ABOVE_16(A)\r
+#define ZFLAG_32(A) MASK_OUT_ABOVE_32(A)\r
+\r
+\r
+/* Flag values */\r
+#define NFLAG_SET 0x80\r
+#define NFLAG_CLEAR 0\r
+#define CFLAG_SET 0x100\r
+#define CFLAG_CLEAR 0\r
+#define XFLAG_SET 0x100\r
+#define XFLAG_CLEAR 0\r
+#define VFLAG_SET 0x80\r
+#define VFLAG_CLEAR 0\r
+#define ZFLAG_SET 0\r
+#define ZFLAG_CLEAR 0xffffffff\r
+\r
+#define SFLAG_SET 4\r
+#define SFLAG_CLEAR 0\r
+#define MFLAG_SET 2\r
+#define MFLAG_CLEAR 0\r
+\r
+/* Turn flag values into 1 or 0 */\r
+#define XFLAG_AS_1() ((FLAG_X>>8)&1)\r
+#define NFLAG_AS_1() ((FLAG_N>>7)&1)\r
+#define VFLAG_AS_1() ((FLAG_V>>7)&1)\r
+#define ZFLAG_AS_1() (!FLAG_Z)\r
+#define CFLAG_AS_1() ((FLAG_C>>8)&1)\r
+\r
+\r
+/* Conditions */\r
+#define COND_CS() (FLAG_C&0x100)\r
+#define COND_CC() (!COND_CS())\r
+#define COND_VS() (FLAG_V&0x80)\r
+#define COND_VC() (!COND_VS())\r
+#define COND_NE() FLAG_Z\r
+#define COND_EQ() (!COND_NE())\r
+#define COND_MI() (FLAG_N&0x80)\r
+#define COND_PL() (!COND_MI())\r
+#define COND_LT() ((FLAG_N^FLAG_V)&0x80)\r
+#define COND_GE() (!COND_LT())\r
+#define COND_HI() (COND_CC() && COND_NE())\r
+#define COND_LS() (COND_CS() || COND_EQ())\r
+#define COND_GT() (COND_GE() && COND_NE())\r
+#define COND_LE() (COND_LT() || COND_EQ())\r
+\r
+/* Reversed conditions */\r
+#define COND_NOT_CS() COND_CC()\r
+#define COND_NOT_CC() COND_CS()\r
+#define COND_NOT_VS() COND_VC()\r
+#define COND_NOT_VC() COND_VS()\r
+#define COND_NOT_NE() COND_EQ()\r
+#define COND_NOT_EQ() COND_NE()\r
+#define COND_NOT_MI() COND_PL()\r
+#define COND_NOT_PL() COND_MI()\r
+#define COND_NOT_LT() COND_GE()\r
+#define COND_NOT_GE() COND_LT()\r
+#define COND_NOT_HI() COND_LS()\r
+#define COND_NOT_LS() COND_HI()\r
+#define COND_NOT_GT() COND_LE()\r
+#define COND_NOT_LE() COND_GT()\r
+\r
+/* Not real conditions, but here for convenience */\r
+#define COND_XS() (FLAG_X&0x100)\r
+#define COND_XC() (!COND_XS)\r
+\r
+\r
+/* Get the condition code register */\r
+#define m68ki_get_ccr() ((COND_XS() >> 4) | \\r
+ (COND_MI() >> 4) | \\r
+ (COND_EQ() << 2) | \\r
+ (COND_VS() >> 6) | \\r
+ (COND_CS() >> 8))\r
+\r
+/* Get the status register */\r
+#define m68ki_get_sr() ( FLAG_T1 | \\r
+ FLAG_T0 | \\r
+ (FLAG_S << 11) | \\r
+ (FLAG_M << 11) | \\r
+ FLAG_INT_MASK | \\r
+ m68ki_get_ccr())\r
+\r
+\r
+\r
+/* ---------------------------- Cycle Counting ---------------------------- */\r
+\r
+#define ADD_CYCLES(A) m68ki_remaining_cycles += (A)\r
+#define USE_CYCLES(A) m68ki_remaining_cycles -= (A)\r
+#define SET_CYCLES(A) m68ki_remaining_cycles = A\r
+#define GET_CYCLES() m68ki_remaining_cycles\r
+#define USE_ALL_CYCLES() m68ki_remaining_cycles = 0\r
+\r
+\r
+\r
+/* ----------------------------- Read / Write ----------------------------- */\r
+\r
+/* Read from the current address space */\r
+#define m68ki_read_8(A) m68ki_read_8_fc (A, FLAG_S | m68ki_get_address_space())\r
+#define m68ki_read_16(A) m68ki_read_16_fc(A, FLAG_S | m68ki_get_address_space())\r
+#define m68ki_read_32(A) m68ki_read_32_fc(A, FLAG_S | m68ki_get_address_space())\r
+\r
+/* Write to the current data space */\r
+#define m68ki_write_8(A, V) m68ki_write_8_fc (A, FLAG_S | FUNCTION_CODE_USER_DATA, V)\r
+#define m68ki_write_16(A, V) m68ki_write_16_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V)\r
+#define m68ki_write_32(A, V) m68ki_write_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V)\r
+\r
+#if M68K_SIMULATE_PD_WRITES\r
+#define m68ki_write_32_pd(A, V) m68ki_write_32_pd_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V)\r
+#else\r
+#define m68ki_write_32_pd(A, V) m68ki_write_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V)\r
+#endif\r
+\r
+/* map read immediate 8 to read immediate 16 */\r
+#define m68ki_read_imm_8() MASK_OUT_ABOVE_8(m68ki_read_imm_16())\r
+\r
+/* Map PC-relative reads */\r
+#define m68ki_read_pcrel_8(A) m68k_read_pcrelative_8(A)\r
+#define m68ki_read_pcrel_16(A) m68k_read_pcrelative_16(A)\r
+#define m68ki_read_pcrel_32(A) m68k_read_pcrelative_32(A)\r
+\r
+/* Read from the program space */\r
+#define m68ki_read_program_8(A) m68ki_read_8_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM)\r
+#define m68ki_read_program_16(A) m68ki_read_16_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM)\r
+#define m68ki_read_program_32(A) m68ki_read_32_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM)\r
+\r
+/* Read from the data space */\r
+#define m68ki_read_data_8(A) m68ki_read_8_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA)\r
+#define m68ki_read_data_16(A) m68ki_read_16_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA)\r
+#define m68ki_read_data_32(A) m68ki_read_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA)\r
+\r
+\r
+\r
+/* ======================================================================== */\r
+/* =============================== PROTOTYPES ============================= */\r
+/* ======================================================================== */\r
+\r
+typedef struct\r
+{\r
+ uint cpu_type; /* CPU Type: 68000, 68008, 68010, 68EC020, or 68020 */\r
+ uint dar[16]; /* Data and Address Registers */\r
+ uint ppc; /* Previous program counter */\r
+ uint pc; /* Program Counter */\r
+ uint sp[7]; /* User, Interrupt, and Master Stack Pointers */\r
+ uint vbr; /* Vector Base Register (m68010+) */\r
+ uint sfc; /* Source Function Code Register (m68010+) */\r
+ uint dfc; /* Destination Function Code Register (m68010+) */\r
+ uint cacr; /* Cache Control Register (m68020, unemulated) */\r
+ uint caar; /* Cache Address Register (m68020, unemulated) */\r
+ uint ir; /* Instruction Register */\r
+ uint t1_flag; /* Trace 1 */\r
+ uint t0_flag; /* Trace 0 */\r
+ uint s_flag; /* Supervisor */\r
+ uint m_flag; /* Master/Interrupt state */\r
+ uint x_flag; /* Extend */\r
+ uint n_flag; /* Negative */\r
+ uint not_z_flag; /* Zero, inverted for speedups */\r
+ uint v_flag; /* Overflow */\r
+ uint c_flag; /* Carry */\r
+ uint int_mask; /* I0-I2 */\r
+ uint int_level; /* State of interrupt pins IPL0-IPL2 -- ASG: changed from ints_pending */\r
+ uint int_cycles; /* ASG: extra cycles from generated interrupts */\r
+ uint stopped; /* Stopped state */\r
+ uint pref_addr; /* Last prefetch address */\r
+ uint pref_data; /* Data in the prefetch queue */\r
+ uint address_mask; /* Available address pins */\r
+ uint sr_mask; /* Implemented status register bits */\r
+ uint instr_mode; /* Stores whether we are in instruction mode or group 0/1 exception mode */\r
+ uint run_mode; /* Stores whether we are processing a reset, bus error, address error, or something else */\r
+\r
+ /* Clocks required for instructions / exceptions */\r
+ uint cyc_bcc_notake_b;\r
+ uint cyc_bcc_notake_w;\r
+ uint cyc_dbcc_f_noexp;\r
+ uint cyc_dbcc_f_exp;\r
+ uint cyc_scc_r_true;\r
+ uint cyc_movem_w;\r
+ uint cyc_movem_l;\r
+ uint cyc_shift;\r
+ uint cyc_reset;\r
+ uint8* cyc_instruction;\r
+ uint8* cyc_exception;\r
+\r
+ /* Callbacks to host */\r
+ int (*int_ack_callback)(int int_line); /* Interrupt Acknowledge */\r
+ void (*bkpt_ack_callback)(unsigned int data); /* Breakpoint Acknowledge */\r
+ void (*reset_instr_callback)(void); /* Called when a RESET instruction is encountered */\r
+ void (*cmpild_instr_callback)(unsigned int, int); /* Called when a CMPI.L #v, Dn instruction is encountered */\r
+ void (*rte_instr_callback)(void); /* Called when a RTE instruction is encountered */\r
+ void (*pc_changed_callback)(unsigned int new_pc); /* Called when the PC changes by a large amount */\r
+ void (*set_fc_callback)(unsigned int new_fc); /* Called when the CPU function code changes */\r
+ void (*instr_hook_callback)(void); /* Called every instruction cycle prior to execution */\r
+\r
+} m68ki_cpu_core;\r
+\r
+\r
+extern m68ki_cpu_core *m68ki_cpu_p;\r
+#define m68ki_cpu (*m68ki_cpu_p) // test\r
+\r
+extern sint m68ki_remaining_cycles;\r
+extern uint m68ki_tracing;\r
+extern uint8 m68ki_shift_8_table[];\r
+extern uint16 m68ki_shift_16_table[];\r
+extern uint m68ki_shift_32_table[];\r
+extern uint8 m68ki_exception_cycle_table[][256];\r
+extern uint m68ki_address_space;\r
+extern uint8 m68ki_ea_idx_cycle_table[];\r
+\r
+extern uint m68ki_aerr_address;\r
+extern uint m68ki_aerr_write_mode;\r
+extern uint m68ki_aerr_fc;\r
+\r
+/* Read data immediately after the program counter */\r
+INLINE uint m68ki_read_imm_16(void);\r
+INLINE uint m68ki_read_imm_32(void);\r
+\r
+/* Read data with specific function code */\r
+INLINE uint m68ki_read_8_fc (uint address, uint fc);\r
+INLINE uint m68ki_read_16_fc (uint address, uint fc);\r
+INLINE uint m68ki_read_32_fc (uint address, uint fc);\r
+\r
+/* Write data with specific function code */\r
+INLINE void m68ki_write_8_fc (uint address, uint fc, uint value);\r
+INLINE void m68ki_write_16_fc(uint address, uint fc, uint value);\r
+INLINE void m68ki_write_32_fc(uint address, uint fc, uint value);\r
+#if M68K_SIMULATE_PD_WRITES\r
+INLINE void m68ki_write_32_pd_fc(uint address, uint fc, uint value);\r
+#endif /* M68K_SIMULATE_PD_WRITES */\r
+\r
+/* Indexed and PC-relative ea fetching */\r
+INLINE uint m68ki_get_ea_pcdi(void);\r
+INLINE uint m68ki_get_ea_pcix(void);\r
+INLINE uint m68ki_get_ea_ix(uint An);\r
+\r
+/* Operand fetching */\r
+INLINE uint OPER_AY_AI_8(void);\r
+INLINE uint OPER_AY_AI_16(void);\r
+INLINE uint OPER_AY_AI_32(void);\r
+INLINE uint OPER_AY_PI_8(void);\r
+INLINE uint OPER_AY_PI_16(void);\r
+INLINE uint OPER_AY_PI_32(void);\r
+INLINE uint OPER_AY_PD_8(void);\r
+INLINE uint OPER_AY_PD_16(void);\r
+INLINE uint OPER_AY_PD_32(void);\r
+INLINE uint OPER_AY_DI_8(void);\r
+INLINE uint OPER_AY_DI_16(void);\r
+INLINE uint OPER_AY_DI_32(void);\r
+INLINE uint OPER_AY_IX_8(void);\r
+INLINE uint OPER_AY_IX_16(void);\r
+INLINE uint OPER_AY_IX_32(void);\r
+\r
+INLINE uint OPER_AX_AI_8(void);\r
+INLINE uint OPER_AX_AI_16(void);\r
+INLINE uint OPER_AX_AI_32(void);\r
+INLINE uint OPER_AX_PI_8(void);\r
+INLINE uint OPER_AX_PI_16(void);\r
+INLINE uint OPER_AX_PI_32(void);\r
+INLINE uint OPER_AX_PD_8(void);\r
+INLINE uint OPER_AX_PD_16(void);\r
+INLINE uint OPER_AX_PD_32(void);\r
+INLINE uint OPER_AX_DI_8(void);\r
+INLINE uint OPER_AX_DI_16(void);\r
+INLINE uint OPER_AX_DI_32(void);\r
+INLINE uint OPER_AX_IX_8(void);\r
+INLINE uint OPER_AX_IX_16(void);\r
+INLINE uint OPER_AX_IX_32(void);\r
+\r
+INLINE uint OPER_A7_PI_8(void);\r
+INLINE uint OPER_A7_PD_8(void);\r
+\r
+INLINE uint OPER_AW_8(void);\r
+INLINE uint OPER_AW_16(void);\r
+INLINE uint OPER_AW_32(void);\r
+INLINE uint OPER_AL_8(void);\r
+INLINE uint OPER_AL_16(void);\r
+INLINE uint OPER_AL_32(void);\r
+INLINE uint OPER_PCDI_8(void);\r
+INLINE uint OPER_PCDI_16(void);\r
+INLINE uint OPER_PCDI_32(void);\r
+INLINE uint OPER_PCIX_8(void);\r
+INLINE uint OPER_PCIX_16(void);\r
+INLINE uint OPER_PCIX_32(void);\r
+\r
+/* Stack operations */\r
+INLINE void m68ki_push_16(uint value);\r
+INLINE void m68ki_push_32(uint value);\r
+INLINE uint m68ki_pull_16(void);\r
+INLINE uint m68ki_pull_32(void);\r
+\r
+/* Program flow operations */\r
+INLINE void m68ki_jump(uint new_pc);\r
+INLINE void m68ki_jump_vector(uint vector);\r
+INLINE void m68ki_branch_8(uint offset);\r
+INLINE void m68ki_branch_16(uint offset);\r
+INLINE void m68ki_branch_32(uint offset);\r
+\r
+/* Status register operations. */\r
+INLINE void m68ki_set_s_flag(uint value); /* Only bit 2 of value should be set (i.e. 4 or 0) */\r
+INLINE void m68ki_set_sm_flag(uint value); /* only bits 1 and 2 of value should be set */\r
+INLINE void m68ki_set_ccr(uint value); /* set the condition code register */\r
+INLINE void m68ki_set_sr(uint value); /* set the status register */\r
+INLINE void m68ki_set_sr_noint(uint value); /* set the status register */\r
+\r
+/* Exception processing */\r
+INLINE uint m68ki_init_exception(void); /* Initial exception processing */\r
+\r
+INLINE void m68ki_stack_frame_3word(uint pc, uint sr); /* Stack various frame types */\r
+INLINE void m68ki_stack_frame_buserr(uint sr);\r
+\r
+INLINE void m68ki_stack_frame_0000(uint pc, uint sr, uint vector);\r
+INLINE void m68ki_stack_frame_0001(uint pc, uint sr, uint vector);\r
+INLINE void m68ki_stack_frame_0010(uint sr, uint vector);\r
+INLINE void m68ki_stack_frame_1000(uint pc, uint sr, uint vector);\r
+INLINE void m68ki_stack_frame_1010(uint sr, uint vector, uint pc);\r
+INLINE void m68ki_stack_frame_1011(uint sr, uint vector, uint pc);\r
+\r
+INLINE void m68ki_exception_trap(uint vector);\r
+INLINE void m68ki_exception_trapN(uint vector);\r
+INLINE void m68ki_exception_trace(void);\r
+INLINE void m68ki_exception_privilege_violation(void);\r
+INLINE void m68ki_exception_1010(void);\r
+INLINE void m68ki_exception_1111(void);\r
+INLINE void m68ki_exception_illegal(void);\r
+INLINE void m68ki_exception_format_error(void);\r
+INLINE void m68ki_exception_address_error(void);\r
+INLINE void m68ki_exception_interrupt(uint int_level);\r
+INLINE void m68ki_check_interrupts(void); /* ASG: check for interrupts */\r
+\r
+/* quick disassembly (used for logging) */\r
+char* m68ki_disassemble_quick(unsigned int pc, unsigned int cpu_type);\r
+\r
+\r
+/* ======================================================================== */\r
+/* =========================== UTILITY FUNCTIONS ========================== */\r
+/* ======================================================================== */\r
+\r
+\r
+/* ---------------------------- Read Immediate ---------------------------- */\r
+\r
+/* Handles all immediate reads, does address error check, function code setting,\r
+ * and prefetching if they are enabled in m68kconf.h\r
+ */\r
+INLINE uint m68ki_read_imm_16(void)\r
+{\r
+ m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */\r
+#if M68K_EMULATE_PREFETCH\r
+ if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR)\r
+ {\r
+ CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC);\r
+ CPU_PREF_DATA = m68k_read_immediate_32(ADDRESS_68K(CPU_PREF_ADDR));\r
+ }\r
+ REG_PC += 2;\r
+ return MASK_OUT_ABOVE_16(CPU_PREF_DATA >> ((2-((REG_PC-2)&2))<<3));\r
+#else\r
+ REG_PC += 2;\r
+ return m68k_read_immediate_16(ADDRESS_68K(REG_PC-2));\r
+#endif /* M68K_EMULATE_PREFETCH */\r
+}\r
+INLINE uint m68ki_read_imm_32(void)\r
+{\r
+#if M68K_EMULATE_PREFETCH\r
+ uint temp_val;\r
+\r
+ m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */\r
+ if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR)\r
+ {\r
+ CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC);\r
+ CPU_PREF_DATA = m68k_read_immediate_32(ADDRESS_68K(CPU_PREF_ADDR));\r
+ }\r
+ temp_val = CPU_PREF_DATA;\r
+ REG_PC += 2;\r
+ if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR)\r
+ {\r
+ CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC);\r
+ CPU_PREF_DATA = m68k_read_immediate_32(ADDRESS_68K(CPU_PREF_ADDR));\r
+ temp_val = MASK_OUT_ABOVE_32((temp_val << 16) | (CPU_PREF_DATA >> 16));\r
+ }\r
+ REG_PC += 2;\r
+\r
+ return temp_val;\r
+#else\r
+ m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */\r
+ REG_PC += 4;\r
+ return m68k_read_immediate_32(ADDRESS_68K(REG_PC-4));\r
+#endif /* M68K_EMULATE_PREFETCH */\r
+}\r
+\r
+\r
+\r
+/* ------------------------- Top level read/write ------------------------- */\r
+\r
+/* Handles all memory accesses (except for immediate reads if they are\r
+ * configured to use separate functions in m68kconf.h).\r
+ * All memory accesses must go through these top level functions.\r
+ * These functions will also check for address error and set the function\r
+ * code if they are enabled in m68kconf.h.\r
+ */\r
+INLINE uint m68ki_read_8_fc(uint address, uint fc)\r
+{\r
+ m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */\r
+ return m68k_read_memory_8(ADDRESS_68K(address));\r
+}\r
+INLINE uint m68ki_read_16_fc(uint address, uint fc)\r
+{\r
+ m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_check_address_error_010_less(address, MODE_READ, fc); /* auto-disable (see m68kcpu.h) */\r
+ return m68k_read_memory_16(ADDRESS_68K(address));\r
+}\r
+INLINE uint m68ki_read_32_fc(uint address, uint fc)\r
+{\r
+ m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_check_address_error_010_less(address, MODE_READ, fc); /* auto-disable (see m68kcpu.h) */\r
+ return m68k_read_memory_32(ADDRESS_68K(address));\r
+}\r
+\r
+INLINE void m68ki_write_8_fc(uint address, uint fc, uint value)\r
+{\r
+ m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */\r
+ m68k_write_memory_8(ADDRESS_68K(address), value);\r
+}\r
+INLINE void m68ki_write_16_fc(uint address, uint fc, uint value)\r
+{\r
+ m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_check_address_error_010_less(address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */\r
+ m68k_write_memory_16(ADDRESS_68K(address), value);\r
+}\r
+INLINE void m68ki_write_32_fc(uint address, uint fc, uint value)\r
+{\r
+ m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_check_address_error_010_less(address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */\r
+ m68k_write_memory_32(ADDRESS_68K(address), value);\r
+}\r
+\r
+#if M68K_SIMULATE_PD_WRITES\r
+INLINE void m68ki_write_32_pd_fc(uint address, uint fc, uint value)\r
+{\r
+ m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */\r
+ m68ki_check_address_error_010_less(address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */\r
+ m68k_write_memory_32_pd(ADDRESS_68K(address), value);\r
+}\r
+#endif\r
+\r
+\r
+/* --------------------- Effective Address Calculation -------------------- */\r
+\r
+/* The program counter relative addressing modes cause operands to be\r
+ * retrieved from program space, not data space.\r
+ */\r
+INLINE uint m68ki_get_ea_pcdi(void)\r
+{\r
+ uint old_pc = REG_PC;\r
+ m68ki_use_program_space(); /* auto-disable */\r
+ return old_pc + MAKE_INT_16(m68ki_read_imm_16());\r
+}\r
+\r
+\r
+INLINE uint m68ki_get_ea_pcix(void)\r
+{\r
+ m68ki_use_program_space(); /* auto-disable */\r
+ return m68ki_get_ea_ix(REG_PC);\r
+}\r
+\r
+/* Indexed addressing modes are encoded as follows:\r
+ *\r
+ * Base instruction format:\r
+ * F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0\r
+ * x x x x x x x x x x | 1 1 0 | BASE REGISTER (An)\r
+ *\r
+ * Base instruction format for destination EA in move instructions:\r
+ * F E D C | B A 9 | 8 7 6 | 5 4 3 2 1 0\r
+ * x x x x | BASE REG | 1 1 0 | X X X X X X (An)\r
+ *\r
+ * Brief extension format:\r
+ * F | E D C | B | A 9 | 8 | 7 6 5 4 3 2 1 0\r
+ * D/A | REGISTER | W/L | SCALE | 0 | DISPLACEMENT\r
+ *\r
+ * Full extension format:\r
+ * F E D C B A 9 8 7 6 5 4 3 2 1 0\r
+ * D/A | REGISTER | W/L | SCALE | 1 | BS | IS | BD SIZE | 0 | I/IS\r
+ * BASE DISPLACEMENT (0, 16, 32 bit) (bd)\r
+ * OUTER DISPLACEMENT (0, 16, 32 bit) (od)\r
+ *\r
+ * D/A: 0 = Dn, 1 = An (Xn)\r
+ * W/L: 0 = W (sign extend), 1 = L (.SIZE)\r
+ * SCALE: 00=1, 01=2, 10=4, 11=8 (*SCALE)\r
+ * BS: 0=add base reg, 1=suppress base reg (An suppressed)\r
+ * IS: 0=add index, 1=suppress index (Xn suppressed)\r
+ * BD SIZE: 00=reserved, 01=NULL, 10=Word, 11=Long (size of bd)\r
+ *\r
+ * IS I/IS Operation\r
+ * 0 000 No Memory Indirect\r
+ * 0 001 indir prex with null outer\r
+ * 0 010 indir prex with word outer\r
+ * 0 011 indir prex with long outer\r
+ * 0 100 reserved\r
+ * 0 101 indir postx with null outer\r
+ * 0 110 indir postx with word outer\r
+ * 0 111 indir postx with long outer\r
+ * 1 000 no memory indirect\r
+ * 1 001 mem indir with null outer\r
+ * 1 010 mem indir with word outer\r
+ * 1 011 mem indir with long outer\r
+ * 1 100-111 reserved\r
+ */\r
+INLINE uint m68ki_get_ea_ix(uint An)\r
+{\r
+ /* An = base register */\r
+ uint extension = m68ki_read_imm_16();\r
+ uint Xn = 0; /* Index register */\r
+ uint bd = 0; /* Base Displacement */\r
+ uint od = 0; /* Outer Displacement */\r
+\r
+ if(CPU_TYPE_IS_010_LESS(CPU_TYPE))\r
+ {\r
+ /* Calculate index */\r
+ Xn = REG_DA[extension>>12]; /* Xn */\r
+ if(!BIT_B(extension)) /* W/L */\r
+ Xn = MAKE_INT_16(Xn);\r
+\r
+ /* Add base register and displacement and return */\r
+ return An + Xn + MAKE_INT_8(extension);\r
+ }\r
+\r
+ /* Brief extension format */\r
+ if(!BIT_8(extension))\r
+ {\r
+ /* Calculate index */\r
+ Xn = REG_DA[extension>>12]; /* Xn */\r
+ if(!BIT_B(extension)) /* W/L */\r
+ Xn = MAKE_INT_16(Xn);\r
+ /* Add scale if proper CPU type */\r
+ if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ Xn <<= (extension>>9) & 3; /* SCALE */\r
+\r
+ /* Add base register and displacement and return */\r
+ return An + Xn + MAKE_INT_8(extension);\r
+ }\r
+\r
+ /* Full extension format */\r
+\r
+ USE_CYCLES(m68ki_ea_idx_cycle_table[extension&0x3f]);\r
+\r
+ /* Check if base register is present */\r
+ if(BIT_7(extension)) /* BS */\r
+ An = 0; /* An */\r
+\r
+ /* Check if index is present */\r
+ if(!BIT_6(extension)) /* IS */\r
+ {\r
+ Xn = REG_DA[extension>>12]; /* Xn */\r
+ if(!BIT_B(extension)) /* W/L */\r
+ Xn = MAKE_INT_16(Xn);\r
+ Xn <<= (extension>>9) & 3; /* SCALE */\r
+ }\r
+\r
+ /* Check if base displacement is present */\r
+ if(BIT_5(extension)) /* BD SIZE */\r
+ bd = BIT_4(extension) ? m68ki_read_imm_32() : MAKE_INT_16(m68ki_read_imm_16());\r
+\r
+ /* If no indirect action, we are done */\r
+ if(!(extension&7)) /* No Memory Indirect */\r
+ return An + bd + Xn;\r
+\r
+ /* Check if outer displacement is present */\r
+ if(BIT_1(extension)) /* I/IS: od */\r
+ od = BIT_0(extension) ? m68ki_read_imm_32() : MAKE_INT_16(m68ki_read_imm_16());\r
+\r
+ /* Postindex */\r
+ if(BIT_2(extension)) /* I/IS: 0 = preindex, 1 = postindex */\r
+ return m68ki_read_32(An + bd) + Xn + od;\r
+\r
+ /* Preindex */\r
+ return m68ki_read_32(An + bd + Xn) + od;\r
+}\r
+\r
+\r
+/* Fetch operands */\r
+INLINE uint OPER_AY_AI_8(void) {uint ea = EA_AY_AI_8(); return m68ki_read_8(ea); }\r
+INLINE uint OPER_AY_AI_16(void) {uint ea = EA_AY_AI_16(); return m68ki_read_16(ea);}\r
+INLINE uint OPER_AY_AI_32(void) {uint ea = EA_AY_AI_32(); return m68ki_read_32(ea);}\r
+INLINE uint OPER_AY_PI_8(void) {uint ea = EA_AY_PI_8(); return m68ki_read_8(ea); }\r
+INLINE uint OPER_AY_PI_16(void) {uint ea = EA_AY_PI_16(); return m68ki_read_16(ea);}\r
+INLINE uint OPER_AY_PI_32(void) {uint ea = EA_AY_PI_32(); return m68ki_read_32(ea);}\r
+INLINE uint OPER_AY_PD_8(void) {uint ea = EA_AY_PD_8(); return m68ki_read_8(ea); }\r
+INLINE uint OPER_AY_PD_16(void) {uint ea = EA_AY_PD_16(); return m68ki_read_16(ea);}\r
+INLINE uint OPER_AY_PD_32(void) {uint ea = EA_AY_PD_32(); return m68ki_read_32(ea);}\r
+INLINE uint OPER_AY_DI_8(void) {uint ea = EA_AY_DI_8(); return m68ki_read_8(ea); }\r
+INLINE uint OPER_AY_DI_16(void) {uint ea = EA_AY_DI_16(); return m68ki_read_16(ea);}\r
+INLINE uint OPER_AY_DI_32(void) {uint ea = EA_AY_DI_32(); return m68ki_read_32(ea);}\r
+INLINE uint OPER_AY_IX_8(void) {uint ea = EA_AY_IX_8(); return m68ki_read_8(ea); }\r
+INLINE uint OPER_AY_IX_16(void) {uint ea = EA_AY_IX_16(); return m68ki_read_16(ea);}\r
+INLINE uint OPER_AY_IX_32(void) {uint ea = EA_AY_IX_32(); return m68ki_read_32(ea);}\r
+\r
+INLINE uint OPER_AX_AI_8(void) {uint ea = EA_AX_AI_8(); return m68ki_read_8(ea); }\r
+INLINE uint OPER_AX_AI_16(void) {uint ea = EA_AX_AI_16(); return m68ki_read_16(ea);}\r
+INLINE uint OPER_AX_AI_32(void) {uint ea = EA_AX_AI_32(); return m68ki_read_32(ea);}\r
+INLINE uint OPER_AX_PI_8(void) {uint ea = EA_AX_PI_8(); return m68ki_read_8(ea); }\r
+INLINE uint OPER_AX_PI_16(void) {uint ea = EA_AX_PI_16(); return m68ki_read_16(ea);}\r
+INLINE uint OPER_AX_PI_32(void) {uint ea = EA_AX_PI_32(); return m68ki_read_32(ea);}\r
+INLINE uint OPER_AX_PD_8(void) {uint ea = EA_AX_PD_8(); return m68ki_read_8(ea); }\r
+INLINE uint OPER_AX_PD_16(void) {uint ea = EA_AX_PD_16(); return m68ki_read_16(ea);}\r
+INLINE uint OPER_AX_PD_32(void) {uint ea = EA_AX_PD_32(); return m68ki_read_32(ea);}\r
+INLINE uint OPER_AX_DI_8(void) {uint ea = EA_AX_DI_8(); return m68ki_read_8(ea); }\r
+INLINE uint OPER_AX_DI_16(void) {uint ea = EA_AX_DI_16(); return m68ki_read_16(ea);}\r
+INLINE uint OPER_AX_DI_32(void) {uint ea = EA_AX_DI_32(); return m68ki_read_32(ea);}\r
+INLINE uint OPER_AX_IX_8(void) {uint ea = EA_AX_IX_8(); return m68ki_read_8(ea); }\r
+INLINE uint OPER_AX_IX_16(void) {uint ea = EA_AX_IX_16(); return m68ki_read_16(ea);}\r
+INLINE uint OPER_AX_IX_32(void) {uint ea = EA_AX_IX_32(); return m68ki_read_32(ea);}\r
+\r
+INLINE uint OPER_A7_PI_8(void) {uint ea = EA_A7_PI_8(); return m68ki_read_8(ea); }\r
+INLINE uint OPER_A7_PD_8(void) {uint ea = EA_A7_PD_8(); return m68ki_read_8(ea); }\r
+\r
+INLINE uint OPER_AW_8(void) {uint ea = EA_AW_8(); return m68ki_read_8(ea); }\r
+INLINE uint OPER_AW_16(void) {uint ea = EA_AW_16(); return m68ki_read_16(ea);}\r
+INLINE uint OPER_AW_32(void) {uint ea = EA_AW_32(); return m68ki_read_32(ea);}\r
+INLINE uint OPER_AL_8(void) {uint ea = EA_AL_8(); return m68ki_read_8(ea); }\r
+INLINE uint OPER_AL_16(void) {uint ea = EA_AL_16(); return m68ki_read_16(ea);}\r
+INLINE uint OPER_AL_32(void) {uint ea = EA_AL_32(); return m68ki_read_32(ea);}\r
+INLINE uint OPER_PCDI_8(void) {uint ea = EA_PCDI_8(); return m68ki_read_pcrel_8(ea); }\r
+INLINE uint OPER_PCDI_16(void) {uint ea = EA_PCDI_16(); return m68ki_read_pcrel_16(ea);}\r
+INLINE uint OPER_PCDI_32(void) {uint ea = EA_PCDI_32(); return m68ki_read_pcrel_32(ea);}\r
+INLINE uint OPER_PCIX_8(void) {uint ea = EA_PCIX_8(); return m68ki_read_pcrel_8(ea); }\r
+INLINE uint OPER_PCIX_16(void) {uint ea = EA_PCIX_16(); return m68ki_read_pcrel_16(ea);}\r
+INLINE uint OPER_PCIX_32(void) {uint ea = EA_PCIX_32(); return m68ki_read_pcrel_32(ea);}\r
+\r
+\r
+\r
+/* ---------------------------- Stack Functions --------------------------- */\r
+\r
+/* Push/pull data from the stack */\r
+INLINE void m68ki_push_16(uint value)\r
+{\r
+ REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2);\r
+ m68ki_write_16(REG_SP, value);\r
+}\r
+\r
+INLINE void m68ki_push_32(uint value)\r
+{\r
+ REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4);\r
+ m68ki_write_32(REG_SP, value);\r
+}\r
+\r
+INLINE uint m68ki_pull_16(void)\r
+{\r
+ REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2);\r
+ return m68ki_read_16(REG_SP-2);\r
+}\r
+\r
+INLINE uint m68ki_pull_32(void)\r
+{\r
+ REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4);\r
+ return m68ki_read_32(REG_SP-4);\r
+}\r
+\r
+\r
+/* Increment/decrement the stack as if doing a push/pull but\r
+ * don't do any memory access.\r
+ */\r
+INLINE void m68ki_fake_push_16(void)\r
+{\r
+ REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2);\r
+}\r
+\r
+INLINE void m68ki_fake_push_32(void)\r
+{\r
+ REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4);\r
+}\r
+\r
+INLINE void m68ki_fake_pull_16(void)\r
+{\r
+ REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2);\r
+}\r
+\r
+INLINE void m68ki_fake_pull_32(void)\r
+{\r
+ REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4);\r
+}\r
+\r
+\r
+/* ----------------------------- Program Flow ----------------------------- */\r
+\r
+/* Jump to a new program location or vector.\r
+ * These functions will also call the pc_changed callback if it was enabled\r
+ * in m68kconf.h.\r
+ */\r
+INLINE void m68ki_jump(uint new_pc)\r
+{\r
+ REG_PC = new_pc;\r
+ m68ki_pc_changed(REG_PC);\r
+}\r
+\r
+INLINE void m68ki_jump_vector(uint vector)\r
+{\r
+ REG_PC = (vector<<2) + REG_VBR;\r
+ REG_PC = m68ki_read_data_32(REG_PC);\r
+ m68ki_pc_changed(REG_PC);\r
+}\r
+\r
+\r
+/* Branch to a new memory location.\r
+ * The 32-bit branch will call pc_changed if it was enabled in m68kconf.h.\r
+ * So far I've found no problems with not calling pc_changed for 8 or 16\r
+ * bit branches.\r
+ */\r
+INLINE void m68ki_branch_8(uint offset)\r
+{\r
+ REG_PC += MAKE_INT_8(offset);\r
+}\r
+\r
+INLINE void m68ki_branch_16(uint offset)\r
+{\r
+ REG_PC += MAKE_INT_16(offset);\r
+}\r
+\r
+INLINE void m68ki_branch_32(uint offset)\r
+{\r
+ REG_PC += offset;\r
+ m68ki_pc_changed(REG_PC);\r
+}\r
+\r
+\r
+\r
+/* ---------------------------- Status Register --------------------------- */\r
+\r
+/* Set the S flag and change the active stack pointer.\r
+ * Note that value MUST be 4 or 0.\r
+ */\r
+INLINE void m68ki_set_s_flag(uint value)\r
+{\r
+ /* Backup the old stack pointer */\r
+ REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)] = REG_SP;\r
+ /* Set the S flag */\r
+ FLAG_S = value;\r
+ /* Set the new stack pointer */\r
+ REG_SP = REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)];\r
+}\r
+\r
+/* Set the S and M flags and change the active stack pointer.\r
+ * Note that value MUST be 0, 2, 4, or 6 (bit2 = S, bit1 = M).\r
+ */\r
+INLINE void m68ki_set_sm_flag(uint value)\r
+{\r
+ /* Backup the old stack pointer */\r
+ REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)] = REG_SP;\r
+ /* Set the S and M flags */\r
+ FLAG_S = value & SFLAG_SET;\r
+ FLAG_M = value & MFLAG_SET;\r
+ /* Set the new stack pointer */\r
+ REG_SP = REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)];\r
+}\r
+\r
+/* Set the S and M flags. Don't touch the stack pointer. */\r
+INLINE void m68ki_set_sm_flag_nosp(uint value)\r
+{\r
+ /* Set the S and M flags */\r
+ FLAG_S = value & SFLAG_SET;\r
+ FLAG_M = value & MFLAG_SET;\r
+}\r
+\r
+\r
+/* Set the condition code register */\r
+INLINE void m68ki_set_ccr(uint value)\r
+{\r
+ FLAG_X = BIT_4(value) << 4;\r
+ FLAG_N = BIT_3(value) << 4;\r
+ FLAG_Z = !BIT_2(value);\r
+ FLAG_V = BIT_1(value) << 6;\r
+ FLAG_C = BIT_0(value) << 8;\r
+}\r
+\r
+/* Set the status register but don't check for interrupts */\r
+INLINE void m68ki_set_sr_noint(uint value)\r
+{\r
+ /* Mask out the "unimplemented" bits */\r
+ value &= CPU_SR_MASK;\r
+\r
+ /* Now set the status register */\r
+ FLAG_T1 = BIT_F(value);\r
+ FLAG_T0 = BIT_E(value);\r
+ FLAG_INT_MASK = value & 0x0700;\r
+ m68ki_set_ccr(value);\r
+ m68ki_set_sm_flag((value >> 11) & 6);\r
+}\r
+\r
+/* Set the status register but don't check for interrupts nor\r
+ * change the stack pointer\r
+ */\r
+INLINE void m68ki_set_sr_noint_nosp(uint value)\r
+{\r
+ /* Mask out the "unimplemented" bits */\r
+ value &= CPU_SR_MASK;\r
+\r
+ /* Now set the status register */\r
+ FLAG_T1 = BIT_F(value);\r
+ FLAG_T0 = BIT_E(value);\r
+ FLAG_INT_MASK = value & 0x0700;\r
+ m68ki_set_ccr(value);\r
+ m68ki_set_sm_flag_nosp((value >> 11) & 6);\r
+}\r
+\r
+/* Set the status register and check for interrupts */\r
+INLINE void m68ki_set_sr(uint value)\r
+{\r
+ m68ki_set_sr_noint(value);\r
+ m68ki_check_interrupts();\r
+}\r
+\r
+\r
+/* ------------------------- Exception Processing ------------------------- */\r
+\r
+/* Initiate exception processing */\r
+INLINE uint m68ki_init_exception(void)\r
+{\r
+ /* Save the old status register */\r
+ uint sr = m68ki_get_sr();\r
+\r
+ /* Turn off trace flag, clear pending traces */\r
+ FLAG_T1 = FLAG_T0 = 0;\r
+ m68ki_clear_trace();\r
+ /* Enter supervisor mode */\r
+ m68ki_set_s_flag(SFLAG_SET);\r
+\r
+ return sr;\r
+}\r
+\r
+/* 3 word stack frame (68000 only) */\r
+INLINE void m68ki_stack_frame_3word(uint pc, uint sr)\r
+{\r
+ m68ki_push_32(pc);\r
+ m68ki_push_16(sr);\r
+}\r
+\r
+/* Format 0 stack frame.\r
+ * This is the standard stack frame for 68010+.\r
+ */\r
+INLINE void m68ki_stack_frame_0000(uint pc, uint sr, uint vector)\r
+{\r
+ /* Stack a 3-word frame if we are 68000 */\r
+ if(CPU_TYPE == CPU_TYPE_000 || CPU_TYPE == CPU_TYPE_008)\r
+ {\r
+ m68ki_stack_frame_3word(pc, sr);\r
+ return;\r
+ }\r
+ m68ki_push_16(vector<<2);\r
+ m68ki_push_32(pc);\r
+ m68ki_push_16(sr);\r
+}\r
+\r
+/* Format 1 stack frame (68020).\r
+ * For 68020, this is the 4 word throwaway frame.\r
+ */\r
+INLINE void m68ki_stack_frame_0001(uint pc, uint sr, uint vector)\r
+{\r
+ m68ki_push_16(0x1000 | (vector<<2));\r
+ m68ki_push_32(pc);\r
+ m68ki_push_16(sr);\r
+}\r
+\r
+/* Format 2 stack frame.\r
+ * This is used only by 68020 for trap exceptions.\r
+ */\r
+INLINE void m68ki_stack_frame_0010(uint sr, uint vector)\r
+{\r
+ m68ki_push_32(REG_PPC);\r
+ m68ki_push_16(0x2000 | (vector<<2));\r
+ m68ki_push_32(REG_PC);\r
+ m68ki_push_16(sr);\r
+}\r
+\r
+\r
+/* Bus error stack frame (68000 only).\r
+ */\r
+INLINE void m68ki_stack_frame_buserr(uint sr)\r
+{\r
+ m68ki_push_32(REG_PC);\r
+ m68ki_push_16(sr);\r
+ m68ki_push_16(REG_IR);\r
+ m68ki_push_32(m68ki_aerr_address); /* access address */\r
+ /* 0 0 0 0 0 0 0 0 0 0 0 R/W I/N FC\r
+ * R/W 0 = write, 1 = read\r
+ * I/N 0 = instruction, 1 = not\r
+ * FC 3-bit function code\r
+ */\r
+ m68ki_push_16(m68ki_aerr_write_mode | CPU_INSTR_MODE | m68ki_aerr_fc);\r
+}\r
+\r
+/* Format 8 stack frame (68010).\r
+ * 68010 only. This is the 29 word bus/address error frame.\r
+ */\r
+void m68ki_stack_frame_1000(uint pc, uint sr, uint vector)\r
+{\r
+ /* VERSION\r
+ * NUMBER\r
+ * INTERNAL INFORMATION, 16 WORDS\r
+ */\r
+ m68ki_fake_push_32();\r
+ m68ki_fake_push_32();\r
+ m68ki_fake_push_32();\r
+ m68ki_fake_push_32();\r
+ m68ki_fake_push_32();\r
+ m68ki_fake_push_32();\r
+ m68ki_fake_push_32();\r
+ m68ki_fake_push_32();\r
+\r
+ /* INSTRUCTION INPUT BUFFER */\r
+ m68ki_push_16(0);\r
+\r
+ /* UNUSED, RESERVED (not written) */\r
+ m68ki_fake_push_16();\r
+\r
+ /* DATA INPUT BUFFER */\r
+ m68ki_push_16(0);\r
+\r
+ /* UNUSED, RESERVED (not written) */\r
+ m68ki_fake_push_16();\r
+\r
+ /* DATA OUTPUT BUFFER */\r
+ m68ki_push_16(0);\r
+\r
+ /* UNUSED, RESERVED (not written) */\r
+ m68ki_fake_push_16();\r
+\r
+ /* FAULT ADDRESS */\r
+ m68ki_push_32(0);\r
+\r
+ /* SPECIAL STATUS WORD */\r
+ m68ki_push_16(0);\r
+\r
+ /* 1000, VECTOR OFFSET */\r
+ m68ki_push_16(0x8000 | (vector<<2));\r
+\r
+ /* PROGRAM COUNTER */\r
+ m68ki_push_32(pc);\r
+\r
+ /* STATUS REGISTER */\r
+ m68ki_push_16(sr);\r
+}\r
+\r
+/* Format A stack frame (short bus fault).\r
+ * This is used only by 68020 for bus fault and address error\r
+ * if the error happens at an instruction boundary.\r
+ * PC stacked is address of next instruction.\r
+ */\r
+void m68ki_stack_frame_1010(uint sr, uint vector, uint pc)\r
+{\r
+ /* INTERNAL REGISTER */\r
+ m68ki_push_16(0);\r
+\r
+ /* INTERNAL REGISTER */\r
+ m68ki_push_16(0);\r
+\r
+ /* DATA OUTPUT BUFFER (2 words) */\r
+ m68ki_push_32(0);\r
+\r
+ /* INTERNAL REGISTER */\r
+ m68ki_push_16(0);\r
+\r
+ /* INTERNAL REGISTER */\r
+ m68ki_push_16(0);\r
+\r
+ /* DATA CYCLE FAULT ADDRESS (2 words) */\r
+ m68ki_push_32(0);\r
+\r
+ /* INSTRUCTION PIPE STAGE B */\r
+ m68ki_push_16(0);\r
+\r
+ /* INSTRUCTION PIPE STAGE C */\r
+ m68ki_push_16(0);\r
+\r
+ /* SPECIAL STATUS REGISTER */\r
+ m68ki_push_16(0);\r
+\r
+ /* INTERNAL REGISTER */\r
+ m68ki_push_16(0);\r
+\r
+ /* 1010, VECTOR OFFSET */\r
+ m68ki_push_16(0xa000 | (vector<<2));\r
+\r
+ /* PROGRAM COUNTER */\r
+ m68ki_push_32(pc);\r
+\r
+ /* STATUS REGISTER */\r
+ m68ki_push_16(sr);\r
+}\r
+\r
+/* Format B stack frame (long bus fault).\r
+ * This is used only by 68020 for bus fault and address error\r
+ * if the error happens during instruction execution.\r
+ * PC stacked is address of instruction in progress.\r
+ */\r
+void m68ki_stack_frame_1011(uint sr, uint vector, uint pc)\r
+{\r
+ /* INTERNAL REGISTERS (18 words) */\r
+ m68ki_push_32(0);\r
+ m68ki_push_32(0);\r
+ m68ki_push_32(0);\r
+ m68ki_push_32(0);\r
+ m68ki_push_32(0);\r
+ m68ki_push_32(0);\r
+ m68ki_push_32(0);\r
+ m68ki_push_32(0);\r
+ m68ki_push_32(0);\r
+\r
+ /* VERSION# (4 bits), INTERNAL INFORMATION */\r
+ m68ki_push_16(0);\r
+\r
+ /* INTERNAL REGISTERS (3 words) */\r
+ m68ki_push_32(0);\r
+ m68ki_push_16(0);\r
+\r
+ /* DATA INTPUT BUFFER (2 words) */\r
+ m68ki_push_32(0);\r
+\r
+ /* INTERNAL REGISTERS (2 words) */\r
+ m68ki_push_32(0);\r
+\r
+ /* STAGE B ADDRESS (2 words) */\r
+ m68ki_push_32(0);\r
+\r
+ /* INTERNAL REGISTER (4 words) */\r
+ m68ki_push_32(0);\r
+ m68ki_push_32(0);\r
+\r
+ /* DATA OUTPUT BUFFER (2 words) */\r
+ m68ki_push_32(0);\r
+\r
+ /* INTERNAL REGISTER */\r
+ m68ki_push_16(0);\r
+\r
+ /* INTERNAL REGISTER */\r
+ m68ki_push_16(0);\r
+\r
+ /* DATA CYCLE FAULT ADDRESS (2 words) */\r
+ m68ki_push_32(0);\r
+\r
+ /* INSTRUCTION PIPE STAGE B */\r
+ m68ki_push_16(0);\r
+\r
+ /* INSTRUCTION PIPE STAGE C */\r
+ m68ki_push_16(0);\r
+\r
+ /* SPECIAL STATUS REGISTER */\r
+ m68ki_push_16(0);\r
+\r
+ /* INTERNAL REGISTER */\r
+ m68ki_push_16(0);\r
+\r
+ /* 1011, VECTOR OFFSET */\r
+ m68ki_push_16(0xb000 | (vector<<2));\r
+\r
+ /* PROGRAM COUNTER */\r
+ m68ki_push_32(pc);\r
+\r
+ /* STATUS REGISTER */\r
+ m68ki_push_16(sr);\r
+}\r
+\r
+\r
+/* Used for Group 2 exceptions.\r
+ * These stack a type 2 frame on the 020.\r
+ */\r
+INLINE void m68ki_exception_trap(uint vector)\r
+{\r
+ uint sr = m68ki_init_exception();\r
+\r
+ if(CPU_TYPE_IS_010_LESS(CPU_TYPE))\r
+ m68ki_stack_frame_0000(REG_PC, sr, vector);\r
+ else\r
+ m68ki_stack_frame_0010(sr, vector);\r
+\r
+ m68ki_jump_vector(vector);\r
+\r
+ /* Use up some clock cycles */\r
+ USE_CYCLES(CYC_EXCEPTION[vector]);\r
+}\r
+\r
+/* Trap#n stacks a 0 frame but behaves like group2 otherwise */\r
+INLINE void m68ki_exception_trapN(uint vector)\r
+{\r
+ uint sr = m68ki_init_exception();\r
+ m68ki_stack_frame_0000(REG_PC, sr, vector);\r
+ m68ki_jump_vector(vector);\r
+\r
+ /* Use up some clock cycles */\r
+ USE_CYCLES(CYC_EXCEPTION[vector]);\r
+}\r
+\r
+/* Exception for trace mode */\r
+INLINE void m68ki_exception_trace(void)\r
+{\r
+ uint sr = m68ki_init_exception();\r
+\r
+ if(CPU_TYPE_IS_010_LESS(CPU_TYPE))\r
+ {\r
+ #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON\r
+ if(CPU_TYPE_IS_000(CPU_TYPE))\r
+ {\r
+ CPU_INSTR_MODE = INSTRUCTION_NO;\r
+ }\r
+ #endif /* M68K_EMULATE_ADDRESS_ERROR */\r
+ m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_TRACE);\r
+ }\r
+ else\r
+ m68ki_stack_frame_0010(sr, EXCEPTION_TRACE);\r
+\r
+ m68ki_jump_vector(EXCEPTION_TRACE);\r
+\r
+ /* Trace nullifies a STOP instruction */\r
+ CPU_STOPPED &= ~STOP_LEVEL_STOP;\r
+\r
+ /* Use up some clock cycles */\r
+ USE_CYCLES(CYC_EXCEPTION[EXCEPTION_TRACE]);\r
+}\r
+\r
+/* Exception for privilege violation */\r
+INLINE void m68ki_exception_privilege_violation(void)\r
+{\r
+ uint sr = m68ki_init_exception();\r
+\r
+ #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON\r
+ if(CPU_TYPE_IS_000(CPU_TYPE))\r
+ {\r
+ CPU_INSTR_MODE = INSTRUCTION_NO;\r
+ }\r
+ #endif /* M68K_EMULATE_ADDRESS_ERROR */\r
+\r
+ m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_PRIVILEGE_VIOLATION);\r
+ m68ki_jump_vector(EXCEPTION_PRIVILEGE_VIOLATION);\r
+\r
+ /* Use up some clock cycles and undo the instruction's cycles */\r
+ USE_CYCLES(CYC_EXCEPTION[EXCEPTION_PRIVILEGE_VIOLATION] - CYC_INSTRUCTION[REG_IR]);\r
+}\r
+\r
+/* Exception for A-Line instructions */\r
+INLINE void m68ki_exception_1010(void)\r
+{\r
+ uint sr;\r
+#if M68K_LOG_1010_1111 == OPT_ON\r
+ M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: called 1010 instruction %04x (%s)\n",\r
+ m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR,\r
+ m68ki_disassemble_quick(ADDRESS_68K(REG_PPC))));\r
+#endif\r
+\r
+ sr = m68ki_init_exception();\r
+ m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_1010);\r
+ m68ki_jump_vector(EXCEPTION_1010);\r
+\r
+ /* Use up some clock cycles and undo the instruction's cycles */\r
+ USE_CYCLES(CYC_EXCEPTION[EXCEPTION_1010] - CYC_INSTRUCTION[REG_IR]);\r
+}\r
+\r
+/* Exception for F-Line instructions */\r
+INLINE void m68ki_exception_1111(void)\r
+{\r
+ uint sr;\r
+\r
+#if M68K_LOG_1010_1111 == OPT_ON\r
+ M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: called 1111 instruction %04x (%s)\n",\r
+ m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR,\r
+ m68ki_disassemble_quick(ADDRESS_68K(REG_PPC))));\r
+#endif\r
+\r
+ sr = m68ki_init_exception();\r
+ m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_1111);\r
+ m68ki_jump_vector(EXCEPTION_1111);\r
+\r
+ /* Use up some clock cycles and undo the instruction's cycles */\r
+ USE_CYCLES(CYC_EXCEPTION[EXCEPTION_1111] - CYC_INSTRUCTION[REG_IR]);\r
+}\r
+\r
+/* Exception for illegal instructions */\r
+INLINE void m68ki_exception_illegal(void)\r
+{\r
+ uint sr;\r
+\r
+ M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: illegal instruction %04x (%s)\n",\r
+ m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR,\r
+ m68ki_disassemble_quick(ADDRESS_68K(REG_PPC))));\r
+\r
+ sr = m68ki_init_exception();\r
+\r
+ #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON\r
+ if(CPU_TYPE_IS_000(CPU_TYPE))\r
+ {\r
+ CPU_INSTR_MODE = INSTRUCTION_NO;\r
+ }\r
+ #endif /* M68K_EMULATE_ADDRESS_ERROR */\r
+\r
+ m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_ILLEGAL_INSTRUCTION);\r
+ m68ki_jump_vector(EXCEPTION_ILLEGAL_INSTRUCTION);\r
+\r
+ /* Use up some clock cycles and undo the instruction's cycles */\r
+ USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ILLEGAL_INSTRUCTION] - CYC_INSTRUCTION[REG_IR]);\r
+}\r
+\r
+/* Exception for format errror in RTE */\r
+INLINE void m68ki_exception_format_error(void)\r
+{\r
+ uint sr = m68ki_init_exception();\r
+ m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_FORMAT_ERROR);\r
+ m68ki_jump_vector(EXCEPTION_FORMAT_ERROR);\r
+\r
+ /* Use up some clock cycles and undo the instruction's cycles */\r
+ USE_CYCLES(CYC_EXCEPTION[EXCEPTION_FORMAT_ERROR] - CYC_INSTRUCTION[REG_IR]);\r
+}\r
+\r
+/* Exception for address error */\r
+INLINE void m68ki_exception_address_error(void)\r
+{\r
+ uint sr = m68ki_init_exception();\r
+\r
+ /* If we were processing a bus error, address error, or reset,\r
+ * this is a catastrophic failure.\r
+ * Halt the CPU\r
+ */\r
+ if(CPU_RUN_MODE == RUN_MODE_BERR_AERR_RESET)\r
+ {\r
+m68k_read_memory_8(0x00ffff01);\r
+ CPU_STOPPED = STOP_LEVEL_HALT;\r
+ return;\r
+ }\r
+ CPU_RUN_MODE = RUN_MODE_BERR_AERR_RESET;\r
+\r
+ /* Note: This is implemented for 68000 only! */\r
+ m68ki_stack_frame_buserr(sr);\r
+\r
+ m68ki_jump_vector(EXCEPTION_ADDRESS_ERROR);\r
+\r
+ /* Use up some clock cycles and undo the instruction's cycles */\r
+ USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ADDRESS_ERROR] - CYC_INSTRUCTION[REG_IR]);\r
+}\r
+\r
+/* Service an interrupt request and start exception processing */\r
+void m68ki_exception_interrupt(uint int_level)\r
+{\r
+ uint vector;\r
+ uint sr;\r
+ uint new_pc;\r
+\r
+ #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON\r
+ if(CPU_TYPE_IS_000(CPU_TYPE))\r
+ {\r
+ CPU_INSTR_MODE = INSTRUCTION_NO;\r
+ }\r
+ #endif /* M68K_EMULATE_ADDRESS_ERROR */\r
+\r
+ /* Turn off the stopped state */\r
+ CPU_STOPPED &= ~STOP_LEVEL_STOP;\r
+\r
+ /* If we are halted, don't do anything */\r
+ if(CPU_STOPPED)\r
+ return;\r
+\r
+ /* Acknowledge the interrupt */\r
+ vector = m68ki_int_ack(int_level);\r
+\r
+ /* Get the interrupt vector */\r
+ if(vector == M68K_INT_ACK_AUTOVECTOR)\r
+ /* Use the autovectors. This is the most commonly used implementation */\r
+ vector = EXCEPTION_INTERRUPT_AUTOVECTOR+int_level;\r
+ else if(vector == M68K_INT_ACK_SPURIOUS)\r
+ /* Called if no devices respond to the interrupt acknowledge */\r
+ vector = EXCEPTION_SPURIOUS_INTERRUPT;\r
+ else if(vector > 255)\r
+ {\r
+ M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: Interrupt acknowledge returned invalid vector $%x\n",\r
+ m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC), vector));\r
+ return;\r
+ }\r
+\r
+ /* Start exception processing */\r
+ sr = m68ki_init_exception();\r
+\r
+ /* Set the interrupt mask to the level of the one being serviced */\r
+ FLAG_INT_MASK = int_level<<8;\r
+\r
+ /* Get the new PC */\r
+ new_pc = m68ki_read_data_32((vector<<2) + REG_VBR);\r
+\r
+ /* If vector is uninitialized, call the uninitialized interrupt vector */\r
+ if(new_pc == 0)\r
+ new_pc = m68ki_read_data_32((EXCEPTION_UNINITIALIZED_INTERRUPT<<2) + REG_VBR);\r
+\r
+ /* Generate a stack frame */\r
+ m68ki_stack_frame_0000(REG_PC, sr, vector);\r
+ if(FLAG_M && CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
+ {\r
+ /* Create throwaway frame */\r
+ m68ki_set_sm_flag(FLAG_S); /* clear M */\r
+ sr |= 0x2000; /* Same as SR in master stack frame except S is forced high */\r
+ m68ki_stack_frame_0001(REG_PC, sr, vector);\r
+ }\r
+\r
+ m68ki_jump(new_pc);\r
+\r
+ /* Defer cycle counting until later */\r
+ CPU_INT_CYCLES += CYC_EXCEPTION[vector];\r
+\r
+#if !M68K_EMULATE_INT_ACK\r
+ /* Automatically clear IRQ if we are not using an acknowledge scheme */\r
+ CPU_INT_LEVEL = 0;\r
+#endif /* M68K_EMULATE_INT_ACK */\r
+}\r
+\r
+\r
+/* ASG: Check for interrupts */\r
+INLINE void m68ki_check_interrupts(void)\r
+{\r
+ if(CPU_INT_LEVEL > FLAG_INT_MASK)\r
+ m68ki_exception_interrupt(CPU_INT_LEVEL>>8);\r
+}\r
+\r
+\r
+\r
+/* ======================================================================== */\r
+/* ============================== END OF FILE ============================= */\r
+/* ======================================================================== */\r
+\r
+#endif /* M68KCPU__HEADER */\r
notaz.gp2x.de / picodrive.git / blobdiff