/* ======================================================================== */\r
/*\r
* MUSASHI\r
- * Version 3.3\r
+ * Version 3.31\r
*\r
* A portable Motorola M680x0 processor emulation engine.\r
- * Copyright 1998-2001 Karl Stenerud. All rights reserved.\r
+ * Copyright 1998-2007 Karl Stenerud. All rights reserved.\r
*\r
* This code may be freely used for non-commercial purposes as long as this\r
* copyright notice remains unaltered in the source code and any binary files\r
static uint g_cpu_ir; /* instruction register */\r
static uint g_cpu_type;\r
static uint g_opcode_type;\r
-static unsigned char* g_rawop;\r
+static const unsigned char* g_rawop;\r
static uint g_rawbasepc;\r
-static uint g_rawlength;\r
\r
/* used by ops like asr, ror, addq, etc */\r
static uint g_3bit_qdata_table[8] = {8, 1, 2, 3, 4, 5, 6, 7};\r
if (g_rawop)\r
result = g_rawop[g_cpu_pc + 1 - g_rawbasepc];\r
else\r
- result = m68k_read_disassembler_16(g_cpu_pc & g_address_mask) & 0xff;\r
+ result = m68k_read_disassembler_16(g_cpu_pc & g_address_mask) & 0xffff; // 0xff ???\r
g_cpu_pc += advance;\r
return result;\r
}\r
result = (g_rawop[g_cpu_pc + 0 - g_rawbasepc] << 8) |\r
g_rawop[g_cpu_pc + 1 - g_rawbasepc];\r
else\r
- result = m68k_read_disassembler_16(g_cpu_pc & g_address_mask) & 0xffff; // & 0xff; ??\r
+ result = m68k_read_disassembler_16(g_cpu_pc & g_address_mask) & 0xffff; // 0xff ???\r
g_cpu_pc += advance;\r
return result;\r
}\r
(g_rawop[g_cpu_pc + 2 - g_rawbasepc] << 8) |\r
g_rawop[g_cpu_pc + 3 - g_rawbasepc];\r
else\r
- result = m68k_read_disassembler_32(g_cpu_pc & g_address_mask); // & 0xff; ??\r
+ result = m68k_read_disassembler_32(g_cpu_pc & g_address_mask) & 0xffff; // 0xff ???\r
g_cpu_pc += advance;\r
return result;\r
}\r
sprintf(g_dasm_str, "extb.l D%d; (2+)", g_cpu_ir&7);\r
}\r
\r
+static void d68040_fpu(void)\r
+{\r
+ char float_data_format[8][3] =\r
+ {\r
+ ".l", ".s", ".x", ".p", ".w", ".d", ".b", ".?"\r
+ };\r
+\r
+ char mnemonic[40];\r
+ uint w2, src, dst_reg;\r
+ LIMIT_CPU_TYPES(M68040_PLUS);\r
+ w2 = read_imm_16();\r
+\r
+ src = (w2 >> 10) & 0x7;\r
+ dst_reg = (w2 >> 7) & 0x7;\r
+\r
+ switch ((w2 >> 13) & 0x7)\r
+ {\r
+ case 0x0:\r
+ case 0x2:\r
+ {\r
+ switch(w2 & 0x7f)\r
+ {\r
+ case 0x00: sprintf(mnemonic, "fmove"); break;\r
+ case 0x01: sprintf(mnemonic, "fint"); break;\r
+ case 0x02: sprintf(mnemonic, "fsinh"); break;\r
+ case 0x03: sprintf(mnemonic, "fintrz"); break;\r
+ case 0x04: sprintf(mnemonic, "fsqrt"); break;\r
+ case 0x06: sprintf(mnemonic, "flognp1"); break;\r
+ case 0x08: sprintf(mnemonic, "fetoxm1"); break;\r
+ case 0x09: sprintf(mnemonic, "ftanh1"); break;\r
+ case 0x0a: sprintf(mnemonic, "fatan"); break;\r
+ case 0x0c: sprintf(mnemonic, "fasin"); break;\r
+ case 0x0d: sprintf(mnemonic, "fatanh"); break;\r
+ case 0x0e: sprintf(mnemonic, "fsin"); break;\r
+ case 0x0f: sprintf(mnemonic, "ftan"); break;\r
+ case 0x10: sprintf(mnemonic, "fetox"); break;\r
+ case 0x11: sprintf(mnemonic, "ftwotox"); break;\r
+ case 0x12: sprintf(mnemonic, "ftentox"); break;\r
+ case 0x14: sprintf(mnemonic, "flogn"); break;\r
+ case 0x15: sprintf(mnemonic, "flog10"); break;\r
+ case 0x16: sprintf(mnemonic, "flog2"); break;\r
+ case 0x18: sprintf(mnemonic, "fabs"); break;\r
+ case 0x19: sprintf(mnemonic, "fcosh"); break;\r
+ case 0x1a: sprintf(mnemonic, "fneg"); break;\r
+ case 0x1c: sprintf(mnemonic, "facos"); break;\r
+ case 0x1d: sprintf(mnemonic, "fcos"); break;\r
+ case 0x1e: sprintf(mnemonic, "fgetexp"); break;\r
+ case 0x1f: sprintf(mnemonic, "fgetman"); break;\r
+ case 0x20: sprintf(mnemonic, "fdiv"); break;\r
+ case 0x21: sprintf(mnemonic, "fmod"); break;\r
+ case 0x22: sprintf(mnemonic, "fadd"); break;\r
+ case 0x23: sprintf(mnemonic, "fmul"); break;\r
+ case 0x24: sprintf(mnemonic, "fsgldiv"); break;\r
+ case 0x25: sprintf(mnemonic, "frem"); break;\r
+ case 0x26: sprintf(mnemonic, "fscale"); break;\r
+ case 0x27: sprintf(mnemonic, "fsglmul"); break;\r
+ case 0x28: sprintf(mnemonic, "fsub"); break;\r
+ case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:\r
+ sprintf(mnemonic, "fsincos"); break;\r
+ case 0x38: sprintf(mnemonic, "fcmp"); break;\r
+ case 0x3a: sprintf(mnemonic, "ftst"); break;\r
+ case 0x41: sprintf(mnemonic, "fssqrt"); break;\r
+ case 0x45: sprintf(mnemonic, "fdsqrt"); break;\r
+ case 0x58: sprintf(mnemonic, "fsabs"); break;\r
+ case 0x5a: sprintf(mnemonic, "fsneg"); break;\r
+ case 0x5c: sprintf(mnemonic, "fdabs"); break;\r
+ case 0x5e: sprintf(mnemonic, "fdneg"); break;\r
+ case 0x60: sprintf(mnemonic, "fsdiv"); break;\r
+ case 0x62: sprintf(mnemonic, "fsadd"); break;\r
+ case 0x63: sprintf(mnemonic, "fsmul"); break;\r
+ case 0x64: sprintf(mnemonic, "fddiv"); break;\r
+ case 0x66: sprintf(mnemonic, "fdadd"); break;\r
+ case 0x67: sprintf(mnemonic, "fdmul"); break;\r
+ case 0x68: sprintf(mnemonic, "fssub"); break;\r
+ case 0x6c: sprintf(mnemonic, "fdsub"); break;\r
+\r
+ default: sprintf(mnemonic, "FPU (?)"); break;\r
+ }\r
+\r
+ if (w2 & 0x4000)\r
+ {\r
+ sprintf(g_dasm_str, "%s%s %s, FP%d", mnemonic, float_data_format[src], get_ea_mode_str_32(g_cpu_ir), dst_reg);\r
+ }\r
+ else\r
+ {\r
+ sprintf(g_dasm_str, "%s.x FP%d, FP%d", mnemonic, src, dst_reg);\r
+ }\r
+ break;\r
+ }\r
+\r
+ case 0x3:\r
+ {\r
+ sprintf(g_dasm_str, "fmove /todo");\r
+ break;\r
+ }\r
+\r
+ case 0x4:\r
+ case 0x5:\r
+ {\r
+ sprintf(g_dasm_str, "fmove /todo");\r
+ break;\r
+ }\r
+\r
+ case 0x6:\r
+ case 0x7:\r
+ {\r
+ sprintf(g_dasm_str, "fmovem /todo");\r
+ break;\r
+ }\r
+\r
+ default:\r
+ {\r
+ sprintf(g_dasm_str, "FPU (?) ");\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
static void d68000_jmp(void)\r
{\r
sprintf(g_dasm_str, "jmp %s", get_ea_mode_str_32(g_cpu_ir));\r
processor = "?";\r
}\r
\r
- if(BIT_1(g_cpu_ir))\r
+ if(BIT_0(g_cpu_ir))\r
sprintf(g_dasm_str, "movec %c%d, %s; (%s)", BIT_F(extension) ? 'A' : 'D', (extension>>12)&7, reg_name, processor);\r
else\r
sprintf(g_dasm_str, "movec %s, %c%d; (%s)", reg_name, BIT_F(extension) ? 'A' : 'D', (extension>>12)&7, processor);\r
{d68020_extb_32 , 0xfff8, 0x49c0, 0x000},\r
{d68000_ext_16 , 0xfff8, 0x4880, 0x000},\r
{d68000_ext_32 , 0xfff8, 0x48c0, 0x000},\r
+ {d68040_fpu , 0xffc0, 0xf200, 0x000},\r
{d68000_illegal , 0xffff, 0x4afc, 0x000},\r
{d68000_jmp , 0xffc0, 0x4ec0, 0x27b},\r
{d68000_jsr , 0xffc0, 0x4e80, 0x27b},\r
return buff;\r
}\r
\r
-unsigned int m68k_disassemble_raw(char* str_buff, unsigned int pc, unsigned char* opdata, unsigned char* argdata, int length, unsigned int cpu_type)\r
+unsigned int m68k_disassemble_raw(char* str_buff, unsigned int pc, const unsigned char* opdata, const unsigned char* argdata, unsigned int cpu_type)\r
{\r
unsigned int result;\r
\r
g_rawop = opdata;\r
g_rawbasepc = pc;\r
- g_rawlength = length;\r
result = m68k_disassemble(str_buff, pc, cpu_type);\r
g_rawop = NULL;\r
return result;\r
return 0;\r
if(g_instruction_table[instruction] == d68040_pflush)\r
return 0;\r
+ case M68K_CPU_TYPE_68040:\r
+ if(g_instruction_table[instruction] == d68020_cpbcc_16)\r
+ return 0;\r
+ if(g_instruction_table[instruction] == d68020_cpbcc_32)\r
+ return 0;\r
+ if(g_instruction_table[instruction] == d68020_cpdbcc)\r
+ return 0;\r
+ if(g_instruction_table[instruction] == d68020_cpgen)\r
+ return 0;\r
+ if(g_instruction_table[instruction] == d68020_cprestore)\r
+ return 0;\r
+ if(g_instruction_table[instruction] == d68020_cpsave)\r
+ return 0;\r
+ if(g_instruction_table[instruction] == d68020_cpscc)\r
+ return 0;\r
+ if(g_instruction_table[instruction] == d68020_cptrapcc_0)\r
+ return 0;\r
+ if(g_instruction_table[instruction] == d68020_cptrapcc_16)\r
+ return 0;\r
+ if(g_instruction_table[instruction] == d68020_cptrapcc_32)\r
+ return 0;\r
}\r
if(cpu_type != M68K_CPU_TYPE_68020 && cpu_type != M68K_CPU_TYPE_68EC020 &&\r
(g_instruction_table[instruction] == d68020_callm ||\r
notaz.gp2x.de / picodrive.git / blobdiff