#define LINK_BRANCHES 1
// limits (per block)
-#define BLOCK_CYCLE_LIMIT 100
#define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6)
// max literal offset from the block end
#define MAX_LITERALS (BLOCK_CYCLE_LIMIT / 4)
#define MAX_LOCAL_BRANCHES 32
-// debug stuff {
+///
+#define FETCH_OP(pc) \
+ dr_pc_base[(pc) / 2]
+
+#define FETCH32(a) \
+ ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1])
+
+#ifdef DRC_SH2
+
+// debug stuff
+// 1 - ?
+// 2 - ?
+// 4 - log asm
+// {
#ifndef DRC_DEBUG
#define DRC_DEBUG 0
#endif
}
#include "mame/sh2dasm.h"
-#include <platform/linux/host_dasm.h>
+#include <platform/libpicofe/linux/host_dasm.h>
static int insns_compiled, hash_collisions, host_insn_count;
#define COUNT_OP \
host_insn_count++
typedef struct block_desc_ {
u32 addr; // SH2 PC address
+ u32 end_addr; // address after last op
void *tcache_ptr; // translated block for above PC
struct block_desc_ *next; // next block with the same PC hash
#if (DRC_DEBUG & 2)
static int block_counts[TCACHE_BUFFERS];
static int block_link_counts[TCACHE_BUFFERS];
+#define BLOCKID_OVERLAP 0xfffe
+#define BLOCKID_MAX block_max_counts[0]
+
// host register tracking
enum {
HR_FREE,
4, 5, 6, 7,
8, -1, -1, -1,
-1, -1, -1, -1,
- -1, -1, -1, 9,
- -1, -1, -1, 10,
- -1, -1, -1, -1,
+ -1, -1, -1, 9, // r12 .. sp
+ -1, -1, -1, 10, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
+ -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
};
static temp_reg_t reg_temp[] = {
static void REGPARM(2) (*sh2_drc_write16_slot)(u32 a, u32 d);
static int REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
-extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode);
-
// address space stuff
-static void *dr_get_pc_base(u32 pc, int is_slave)
-{
- void *ret = NULL;
- u32 mask = 0;
-
- if ((pc & ~0x7ff) == 0) {
- // BIOS
- ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
- mask = 0x7ff;
- }
- else if ((pc & 0xfffff000) == 0xc0000000) {
- // data array
- ret = Pico32xMem->data_array[is_slave];
- mask = 0xfff;
- }
- else if ((pc & 0xc6000000) == 0x06000000) {
- // SDRAM
- ret = Pico32xMem->sdram;
- mask = 0x03ffff;
- }
- else if ((pc & 0xc6000000) == 0x02000000) {
- // ROM
- ret = Pico.rom;
- mask = 0x3fffff;
- }
-
- if (ret == NULL)
- return (void *)-1; // NULL is valid value
-
- return (char *)ret - (pc & ~mask);
-}
-
static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
{
int poffs = -1;
}
#endif
-static block_desc *dr_add_block(u32 addr, int is_slave, int *blk_id)
+static block_desc *dr_add_block(u32 addr, u32 end_addr, int is_slave, int *blk_id)
{
block_desc *bd;
int tcache_id;
if (bd != NULL) {
dbg(2, "block override for %08x", addr);
bd->tcache_ptr = tcache_ptr;
+ bd->end_addr = end_addr;
*blk_id = bd - block_tables[tcache_id];
return bd;
}
bd = &block_tables[tcache_id][*bcount];
bd->addr = addr;
+ bd->end_addr = end_addr;
bd->tcache_ptr = tcache_ptr;
*blk_id = *bcount;
(*bcount)++;
}
}
rcache_invalidate();
+
+ if (reg_map_g2h[SHR_SR] != -1)
+ emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
+
// assuming arg0 and retval reg matches
return rcache_get_tmp_arg(0);
}
{
int ctxr;
host_arg2reg(ctxr, 2);
+ if (reg_map_g2h[SHR_SR] != -1)
+ emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
+
switch (size) {
case 0: // 8
// XXX: consider inlining sh2_drc_write8
emith_call(sh2_drc_write32);
break;
}
+
+ if (reg_map_g2h[SHR_SR] != -1)
+ emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
rcache_invalidate();
}
goto default_; \
}
-#define FETCH_OP(pc) \
- dr_pc_base[(pc) / 2]
-
-#define FETCH32(a) \
- ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1])
-
#define GET_Fx() \
((op >> 4) & 0x0f)
if (GET_Fx() >= n) \
goto default_
-// op_flags: data from 1st pass
-#define OP_FLAGS(pc) op_flags[((pc) - base_pc) / 2]
-#define OF_DELAY_OP (1 << 0)
+static void *dr_get_pc_base(u32 pc, int is_slave);
static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
{
int literal_addr_count = 0;
int pending_branch_cond = -1;
int pending_branch_pc = 0;
- u8 op_flags[BLOCK_CYCLE_LIMIT + 1];
+ u8 op_flags[BLOCK_CYCLE_LIMIT];
struct {
u32 delayed_op:2;
u32 test_irq:1;
}
tcache_ptr = tcache_ptrs[tcache_id];
- this_block = dr_add_block(base_pc, sh2->is_slave, &blkid_main);
- if (this_block == NULL)
- return NULL;
// predict tcache overflow
tmp = tcache_ptr - tcache_bases[tcache_id];
return NULL;
}
+ // 1st pass: scan forward for local branches
+ scan_block(base_pc, sh2->is_slave, op_flags, &end_pc);
+
+ this_block = dr_add_block(base_pc, end_pc + MAX_LITERAL_OFFSET, // XXX
+ sh2->is_slave, &blkid_main);
+ if (this_block == NULL)
+ return NULL;
+
block_entry = tcache_ptr;
dbg(2, "== %csh2 block #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm',
tcache_id, blkid_main, base_pc, block_entry);
dr_link_blocks(tcache_ptr, base_pc, tcache_id);
- // 1st pass: scan forward for local branches
- memset(op_flags, 0, sizeof(op_flags));
- for (cycles = 0, pc = base_pc; cycles < BLOCK_CYCLE_LIMIT; cycles++, pc += 2) {
- op = FETCH_OP(pc);
- if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR
- signed int offs = ((signed int)(op << 20) >> 19);
- pc += 2;
- OP_FLAGS(pc) |= OF_DELAY_OP;
- ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc + offs + 2,);
- break;
- }
- if ((op & 0xf000) == 0) {
- op &= 0xff;
- if (op == 0x1b) // SLEEP
- break;
- if (op == 0x23 || op == 0x03 || op == 0x0b || op == 0x2b) { // BRAF, BSRF, RTS, RTE
- pc += 2;
- OP_FLAGS(pc) |= OF_DELAY_OP;
- break;
- }
+ // collect branch_targets that don't land on delay slots
+ for (pc = base_pc; pc <= end_pc; pc += 2) {
+ if (!(OP_FLAGS(pc) & OF_TARGET))
+ continue;
+ if (OP_FLAGS(pc) & OF_DELAY_OP) {
+ OP_FLAGS(pc) &= ~OF_TARGET;
continue;
}
- if ((op & 0xf0df) == 0x400b) { // JMP, JSR
- pc += 2;
- OP_FLAGS(pc) |= OF_DELAY_OP;
- break;
- }
- if ((op & 0xf900) == 0x8900) { // BT(S), BF(S)
- signed int offs = ((signed int)(op << 24) >> 23);
- if (op & 0x0400)
- OP_FLAGS(pc + 2) |= OF_DELAY_OP;
- ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc + offs + 4, break);
- }
- if ((op & 0xff00) == 0xc300) // TRAPA
- break;
+ ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc, break);
}
- end_pc = pc;
-
- // clean branch_targets that are not really local,
- // and that land on delay slots
- for (i = 0, tmp = 0; i < branch_target_count; i++) {
- pc = branch_target_pc[i];
- if (base_pc <= pc && pc <= end_pc && !(OP_FLAGS(pc) & OF_DELAY_OP))
- branch_target_pc[tmp++] = branch_target_pc[i];
-
- if (i == branch_target_count - 1) // workaround gcc 4.5.2 bug?
- break;
- }
-
- branch_target_count = tmp;
if (branch_target_count > 0) {
memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
memset(branch_target_blkid, 0, sizeof(branch_target_blkid[0]) * branch_target_count);
op = FETCH_OP(pc);
- i = find_in_array(branch_target_pc, branch_target_count, pc);
- if (i >= 0 || pc == base_pc)
+ if ((OP_FLAGS(pc) & OF_TARGET) || pc == base_pc)
{
+ i = find_in_array(branch_target_pc, branch_target_count, pc);
if (pc != base_pc)
{
/* make "subblock" - just a mid-block entry */
dbg(2, "-- %csh2 subblock #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm',
tcache_id, branch_target_blkid[i], pc, tcache_ptr);
- subblock = dr_add_block(pc, sh2->is_slave, &branch_target_blkid[i]);
+ subblock = dr_add_block(pc, end_pc + MAX_LITERAL_OFFSET, // XXX
+ sh2->is_slave, &branch_target_blkid[i]);
if (subblock == NULL)
return NULL;
#if (DRC_DEBUG & 2)
insns_compiled++;
+#endif
#if (DRC_DEBUG & 4)
DasmSH2(sh2dasm_buff, pc, op);
printf("%08x %04x %s\n", pc, op, sh2dasm_buff);
#endif
+#ifdef DRC_CMP
+ //if (out_pc != 0 && out_pc != (u32)-1)
+ // emit_move_r_imm32(SHR_PC, out_pc);
+ //else
+ if (!drcf.delayed_op) {
+ emit_move_r_imm32(SHR_PC, pc);
+ sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
+ FLUSH_CYCLES(sr);
+ // rcache_clean(); // FIXME
+ rcache_flush();
+ emit_do_static_regs(1, 0);
+ emith_pass_arg_r(0, CONTEXT_REG);
+ emith_call(do_sh2_cmp);
+ }
#endif
pc += 2;
EMITH_JMP_END(DCOND_EQ);
rcache_free_tmp(tmp);
- cycles += 3;
+ cycles += 2;
goto end_op;
}
goto default_;
emith_clear_msb(tmp2, tmp3, 16);
emith_mul(tmp, tmp, tmp2);
rcache_free_tmp(tmp2);
-// FIXME: causes timing issues in Doom?
-// cycles++;
goto end_op;
}
goto default_;
tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
emith_mul_u64(tmp3, tmp4, tmp, tmp2);
+ cycles++;
goto end_op;
case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
emith_mul_s64(tmp3, tmp4, tmp, tmp2);
+ cycles++;
goto end_op;
}
goto default_;
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
+#ifndef DRC_CMP
if (FETCH_OP(pc) == 0x8bfd) { // BF #-2
if (gconst_get(GET_Rn(), &tmp)) {
// XXX: limit burned cycles
emith_sh2_dtbf_loop();
goto end_op;
}
+#endif
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
emith_bic_r_imm(sr, T);
emith_subf_r_imm(tmp, 1);
break;
case 0x03: // STC.L SR,@–Rn 0100nnnn00000011
tmp = SHR_SR;
+ cycles++;
break;
case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011
tmp = SHR_GBR;
+ cycles++;
break;
case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011
tmp = SHR_VBR;
+ cycles++;
break;
default:
goto default_;
break;
case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
tmp = SHR_SR;
+ cycles += 2;
break;
case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
tmp = SHR_GBR;
+ cycles += 2;
break;
case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
tmp = SHR_VBR;
+ cycles += 2;
break;
default:
goto default_;
case 0x0d00: // BT/S label 10001101dddddddd
case 0x0f00: // BF/S label 10001111dddddddd
DELAYED_OP;
- cycles--;
// fallthrough
case 0x0900: // BT label 10001001dddddddd
case 0x0b00: // BF label 10001011dddddddd
pending_branch_cond = (op & 0x0200) ? DCOND_EQ : DCOND_NE;
i = ((signed int)(op << 24) >> 23);
pending_branch_pc = pc + i + 2;
- cycles += 2;
goto end_op;
}
goto default_;
default_:
elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
sh2->is_slave ? 's' : 'm', op, pc - 2);
-#ifdef DRC_DEBUG_INTERP
- emit_move_r_imm32(SHR_PC, pc - 2);
- rcache_flush();
- emith_pass_arg_r(0, CONTEXT_REG);
- emith_pass_arg_imm(1, op);
- emith_call(sh2_do_op);
-#endif
break;
}
if (pending_branch_cond != -1 && drcf.delayed_op != 2)
{
u32 target_pc = pending_branch_pc;
+ int ctaken = drcf.delayed_op ? 1 : 2;
void *target;
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
- // handle cycles
FLUSH_CYCLES(sr);
- rcache_clean();
if (drcf.use_saved_t)
emith_tst_r_imm(sr, T_save);
else
emith_tst_r_imm(sr, T);
+ // handle cycles
+ emith_sub_r_imm_c(pending_branch_cond, sr, ctaken<<12);
+ rcache_clean();
+
#if LINK_BRANCHES
if (find_in_array(branch_target_pc, branch_target_count, target_pc) >= 0) {
// local branch
// override any overlay blocks as they become unreachable anyway
if (tcache_id != 0 || (this_block->addr & 0xc7fc0000) == 0x06000000)
{
- u16 *drc_ram_blk = NULL;
+ u16 *p, *drc_ram_blk = NULL;
u32 mask = 0, shift = 0;
if (tcache_id != 0) {
// data array, BIOS
drc_ram_blk = Pico32xMem->drcblk_da[sh2->is_slave];
shift = SH2_DRCBLK_DA_SHIFT;
- mask = 0xfff;
+ mask = 0xfff/2;
}
else if ((this_block->addr & 0xc7fc0000) == 0x06000000) {
// SDRAM
drc_ram_blk = Pico32xMem->drcblk_ram;
shift = SH2_DRCBLK_RAM_SHIFT;
- mask = 0x3ffff;
+ mask = 0x3ffff/2;
}
drc_ram_blk[(base_pc >> shift) & mask] = (blkid_main << 1) | 1;
- for (pc = base_pc + 2; pc < end_pc; pc += 2)
- drc_ram_blk[(pc >> shift) & mask] = blkid_main << 1;
+ for (pc = base_pc + 2; pc < end_pc; pc += 2) {
+ p = &drc_ram_blk[(pc >> shift) & mask];
+ if (*p && *p != (blkid_main << 1))
+ *p = BLOCKID_OVERLAP; // block intersection..
+ else
+ *p = blkid_main << 1;
+ }
- // mark subblocks
+ // mark block entries (used by dr_get_bd())
for (i = 0; i < branch_target_count; i++)
if (branch_target_blkid[i] != 0)
drc_ram_blk[(branch_target_pc[i] >> shift) & mask] =
// mark literals
for (i = 0; i < literal_addr_count; i++) {
tmp = literal_addr[i];
- drc_ram_blk[(tmp >> shift) & mask] = blkid_main << 1;
- if (!(tmp & 3)) // assume long
- drc_ram_blk[((tmp + 2) >> shift) & mask] = blkid_main << 1;
+ p = &drc_ram_blk[(tmp >> shift) & mask];
+ if (*p && *p != (blkid_main << 1))
+ *p = BLOCKID_OVERLAP;
+ else
+ *p = blkid_main << 1;
+ if (!(tmp & 3) && shift == 1)
+ p[1] = p[0]; // assume long
}
}
#endif
}
-static void *sh2_smc_rm_block_entry(block_desc *bd, int tcache_id)
+static void sh2_smc_rm_block_entry(block_desc *bd, int tcache_id)
{
void *tmp;
// XXX: kill links somehow?
- dbg(2, " killing entry %08x, blkid %d", bd->addr, bd - block_tables[tcache_id]);
+ dbg(2, " killing entry %08x-%08x, blkid %d,%d",
+ bd->addr, bd->end_addr, tcache_id, bd - block_tables[tcache_id]);
if (bd->addr == 0 || bd->tcache_ptr == NULL) {
dbg(1, " killing dead block!? %08x", bd->addr);
- return bd->tcache_ptr;
+ return;
}
// since we never reuse space of dead blocks,
emit_move_r_imm32(SHR_PC, bd->addr);
rcache_flush();
emith_jump(sh2_drc_dispatcher);
+
+ host_instructions_updated(bd->tcache_ptr, tcache_ptr);
tcache_ptr = tmp;
- bd->addr = 0;
- return bd->tcache_ptr;
+ bd->addr = bd->end_addr = 0;
}
static void sh2_smc_rm_block(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, u32 mask)
{
- //block_link *bl = block_links[tcache_id];
- //int bl_count = block_link_counts[tcache_id];
block_desc *btab = block_tables[tcache_id];
u16 *p = drc_ram_blk + ((a & mask) >> shift);
u16 *pmax = drc_ram_blk + (mask >> shift);
- void *tcache_min, *tcache_max;
- int zeros;
- u16 *pt;
-
- // Figure out what the main block is, as subblocks also have the flag set.
- // This relies on sub having single entry. It's possible that innocent
- // block might be hit, but that's not such a big deal.
- if ((p[0] >> 1) != (p[1] >> 1)) {
- for (; p > drc_ram_blk; p--)
- if (p[-1] == 0 || (p[-1] >> 1) == (*p >> 1))
- break;
+ u32 id = ~0, end_addr;
+ int max_zeros = MAX_LITERAL_OFFSET >> shift;
+ int i, zeros;
+
+ if (*p == 0 || (*p >> 1) >= BLOCKID_MAX) {
+ u32 from = ~0, to = 0;
+ dbg(1, "slow-remove blocks at @%08x", a);
+ for (i = 0; i < block_counts[tcache_id]; i++) {
+ if (btab[i].addr <= a && a < btab[i].end_addr) {
+ if (btab[i].addr < from)
+ from = btab[i].addr;
+ if (btab[i].end_addr > to)
+ to = btab[i].end_addr;
+ sh2_smc_rm_block_entry(&btab[i], tcache_id);
+ }
+ }
+ if (from < to) {
+ p = drc_ram_blk + ((from & mask) >> shift);
+ memset(p, 0, (to - from) >> (shift - 1));
+ }
+ return;
}
- pt = p;
- for (; p > drc_ram_blk; p--)
- if ((*p & 1))
- break;
+ // use end_addr to distinguish the same block
+ end_addr = btab[*p >> 1].end_addr;
- if (!(*p & 1)) {
- dbg(1, "smc rm: missing block start for %08x?", a);
- p = pt;
+ // go up to the start
+ for (zeros = 0; p > drc_ram_blk && zeros < max_zeros; p--) {
+ // there can be holes because games sometimes keep variables
+ // directly in literal pool and we don't inline them
+ // to avoid recompile (Star Wars Arcade)
+ if (p[-1] == 0) {
+ zeros++;
+ continue;
+ }
+ zeros = 0;
+ if ((p[-1] >> 1) >= BLOCKID_MAX)
+ break;
+ if (btab[p[-1] >> 1].end_addr != end_addr)
+ break;
}
- if (*p == 0)
- return;
-
- tcache_min = tcache_max = sh2_smc_rm_block_entry(&btab[*p >> 1], tcache_id);
- *p = 0;
+ if (!(*p & 1))
+ dbg(1, "smc rm: missing block start for %08x?", a);
- for (p++, zeros = 0; p < pmax && zeros < MAX_LITERAL_OFFSET / 2; p++) {
- int id = *p >> 1;
- if (id == 0) {
- // there can be holes because games sometimes keep variables
- // directly in literal pool and we don't inline them to avoid recompile
- // (Star Wars Arcade)
+ // now go down and kill everything
+ for (zeros = 0; p < pmax && zeros < max_zeros; p++) {
+ if (*p == 0) {
zeros++;
continue;
}
- if (*p & 1) {
- if (id == (p[1] >> 1))
- // hit other block
- break;
- tcache_max = sh2_smc_rm_block_entry(&btab[id], tcache_id);
+ zeros = 0;
+ if ((*p >> 1) >= BLOCKID_MAX)
+ break;
+ if ((*p >> 1) == id) {
+ *p = 0;
+ continue;
}
+ id = *p >> 1;
+ if (btab[id].end_addr != end_addr)
+ break;
*p = 0;
+ sh2_smc_rm_block_entry(&btab[id], tcache_id);
}
-
- host_instructions_updated(tcache_min, (void *)((char *)tcache_max + 4*4 + 4));
}
void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
int sh2_execute(SH2 *sh2c, int cycles)
{
int ret_cycles;
- sh2 = sh2c; // XXX
sh2c->cycles_timeslice = cycles;
// cycles are kept in SHR_SR unused bits (upper 20)
- // bit19 contains T saved for delay slot
+ // bit11 contains T saved for delay slot
// others are usual SH2 flags
sh2c->sr &= 0x3f3;
sh2c->sr |= cycles << 12;
}
}
-// vim:shiftwidth=2:expandtab
+#endif /* DRC_SH2 */
+
+static void *dr_get_pc_base(u32 pc, int is_slave)
+{
+ void *ret = NULL;
+ u32 mask = 0;
+
+ if ((pc & ~0x7ff) == 0) {
+ // BIOS
+ ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
+ mask = 0x7ff;
+ }
+ else if ((pc & 0xfffff000) == 0xc0000000) {
+ // data array
+ ret = Pico32xMem->data_array[is_slave];
+ mask = 0xfff;
+ }
+ else if ((pc & 0xc6000000) == 0x06000000) {
+ // SDRAM
+ ret = Pico32xMem->sdram;
+ mask = 0x03ffff;
+ }
+ else if ((pc & 0xc6000000) == 0x02000000) {
+ // ROM
+ ret = Pico.rom;
+ mask = 0x3fffff;
+ }
+
+ if (ret == NULL)
+ return (void *)-1; // NULL is valid value
+
+ return (char *)ret - (pc & ~mask);
+}
+
+void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc)
+{
+ u16 *dr_pc_base;
+ u32 pc, target, op;
+ int cycles;
+
+ memset(op_flags, 0, BLOCK_CYCLE_LIMIT);
+
+ dr_pc_base = dr_get_pc_base(base_pc, is_slave);
+
+ for (cycles = 0, pc = base_pc; cycles < BLOCK_CYCLE_LIMIT-1; cycles++, pc += 2) {
+ op = FETCH_OP(pc);
+ if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR
+ signed int offs = ((signed int)(op << 20) >> 19);
+ pc += 2;
+ OP_FLAGS(pc) |= OF_DELAY_OP;
+ target = pc + offs + 2;
+ if (base_pc <= target && target < base_pc + BLOCK_CYCLE_LIMIT * 2)
+ OP_FLAGS(target) |= OF_TARGET;
+ break;
+ }
+ if ((op & 0xf000) == 0) {
+ op &= 0xff;
+ if (op == 0x1b) // SLEEP
+ break;
+ // BRAF, BSRF, RTS, RTE
+ if (op == 0x23 || op == 0x03 || op == 0x0b || op == 0x2b) {
+ pc += 2;
+ OP_FLAGS(pc) |= OF_DELAY_OP;
+ break;
+ }
+ continue;
+ }
+ if ((op & 0xf0df) == 0x400b) { // JMP, JSR
+ pc += 2;
+ OP_FLAGS(pc) |= OF_DELAY_OP;
+ break;
+ }
+ if ((op & 0xf900) == 0x8900) { // BT(S), BF(S)
+ signed int offs = ((signed int)(op << 24) >> 23);
+ if (op & 0x0400)
+ OP_FLAGS(pc + 2) |= OF_DELAY_OP;
+ target = pc + offs + 4;
+ if (base_pc <= target && target < base_pc + BLOCK_CYCLE_LIMIT * 2)
+ OP_FLAGS(target) |= OF_TARGET;
+ }
+ if ((op & 0xff00) == 0xc300) // TRAPA
+ break;
+ }
+ *end_pc = pc;
+}
+
+// vim:shiftwidth=2:ts=2:expandtab
notaz.gp2x.de / picodrive.git / blobdiff