xSI,-1, -1, -1,
-1, -1, -1, -1,
-1, -1, -1, -1,
- -1, -1, -1, -1,
- -1, -1, -1, xDI,
- -1, -1, -1, -1,
+ -1, -1, -1, -1, // r12 .. sp
+ -1, -1, -1, xDI, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
+ -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
};
// ax, cx, dx are usually temporaries by convention
#include "../drc/emit_x86.c"
static const int reg_map_g2h[] = {
+#ifndef _WIN32
-1, -1, -1, -1,
-1, -1, -1, -1,
-1, -1, -1, -1,
+ -1, -1, -1, -1, // r12 .. sp
+ -1, -1, -1, xBX, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
+ -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
+#else
+ xDI,-1, -1, -1,
-1, -1, -1, -1,
- -1, -1, -1, xBX,
-1, -1, -1, -1,
+ -1, -1, -1, -1, // r12 .. sp
+ -1, -1, -1, xBX, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
+ -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
+#endif
};
// ax, cx, dx are usually temporaries by convention
{ xCX, },
{ xDX, },
{ xSI, },
+#ifndef _WIN32
{ xDI, },
+#endif
};
#else
emith_call(sh2_drc_log_entry);
rcache_invalidate();
#endif
- emith_tst_r_r(RET_REG, RET_REG);
+ emith_tst_r_r_ptr(RET_REG, RET_REG);
EMITH_SJMP_START(DCOND_EQ);
emith_jump_reg_c(DCOND_NE, RET_REG);
EMITH_SJMP_END(DCOND_EQ);
tcache_id, blkid_main,
tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
insns_compiled, host_insn_count, (float)host_insn_count / insns_compiled);
- if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
+ if ((sh2->pc & 0xc6000000) == 0x02000000) { // ROM
dbg(2, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
+ Pico32x.emu_flags |= P32XF_DRC_ROM_C;
+ }
/*
printf("~~~\n");
tcache_dsm_ptrs[tcache_id] = block_entry_ptr;
flush_tcache(0);
flush_tcache(1);
flush_tcache(2);
+ Pico32x.emu_flags &= ~P32XF_DRC_ROM_C;
}
void sh2_drc_mem_setup(SH2 *sh2)