drc: reload cycles after memhandlers

[picodrive.git] / cpu / sh2 / compiler.c

diff --git a/cpu/sh2/compiler.c b/cpu/sh2/compiler.c
index 5b52694..b55f3e5 100644 (file)
--- a/cpu/sh2/compiler.c
+++ b/cpu/sh2/compiler.c
@@ -166,9 +166,9 @@ static const int reg_map_g2h[] = {
    4,  5,  6,  7,
    8, -1, -1, -1,
   -1, -1, -1, -1,
-  -1, -1, -1,  9,
-  -1, -1, -1, 10,
-  -1, -1, -1, -1,
+  -1, -1, -1,  9, // r12 .. sp
+  -1, -1, -1, 10, // SHR_PC,  SHR_PPC, SHR_PR,   SHR_SR,
+  -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
 };
 
 static temp_reg_t reg_temp[] = {
@@ -983,6 +983,10 @@ static int emit_memhandler_read_(int size, int ram_check)
     }
   }
   rcache_invalidate();
+
+  if (reg_map_g2h[SHR_SR] != -1)
+    emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
+
   // assuming arg0 and retval reg matches
   return rcache_get_tmp_arg(0);
 }
@@ -1040,6 +1044,9 @@ static void emit_memhandler_write(int size, u32 pc, int delay)
 {
   int ctxr;
   host_arg2reg(ctxr, 2);
+  if (reg_map_g2h[SHR_SR] != -1)
+    emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
+
   switch (size) {
   case 0: // 8
     // XXX: consider inlining sh2_drc_write8
@@ -1065,6 +1072,9 @@ static void emit_memhandler_write(int size, u32 pc, int delay)
     emith_call(sh2_drc_write32);
     break;
   }
+
+  if (reg_map_g2h[SHR_SR] != -1)
+    emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
   rcache_invalidate();
 }
 
@@ -2986,7 +2996,7 @@ int sh2_execute(SH2 *sh2c, int cycles)
   sh2c->cycles_timeslice = cycles;
 
   // cycles are kept in SHR_SR unused bits (upper 20)
-  // bit19 contains T saved for delay slot
+  // bit11 contains T saved for delay slot
   // others are usual SH2 flags
   sh2c->sr &= 0x3f3;
   sh2c->sr |= cycles << 12;