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drc: split disassembly to separate pass
[picodrive.git] / cpu / sh2 / mame / sh2pico.c
diff --git a/cpu/sh2/mame/sh2pico.c b/cpu/sh2/mame/sh2pico.c
index 233e0a1..1a70d43 100644 (file)
--- a/cpu/sh2/mame/sh2pico.c
+++ b/cpu/sh2/mame/sh2pico.c
@@ -1,19 +1,24 @@
 #include "../sh2.h"
+#ifdef DRC_CMP
+#include "../compiler.c"
+#endif
 
 // MAME types
+#ifndef INT8
 typedef signed char  INT8;
 typedef signed short INT16;
 typedef signed int   INT32;
 typedef unsigned int   UINT32;
 typedef unsigned short UINT16;
 typedef unsigned char  UINT8;
+#endif
 
-#define RB(a) p32x_sh2_read8(a,sh2)
-#define RW(a) p32x_sh2_read16(a,sh2)
-#define RL(a) p32x_sh2_read32(a,sh2)
-#define WB(a,d) p32x_sh2_write8(a,d,sh2)
-#define WW(a,d) p32x_sh2_write16(a,d,sh2)
-#define WL(a,d) p32x_sh2_write32(a,d,sh2)
+#define RB(sh2, a) p32x_sh2_read8(a,sh2)
+#define RW(sh2, a) p32x_sh2_read16(a,sh2)
+#define RL(sh2, a) p32x_sh2_read32(a,sh2)
+#define WB(sh2, a, d) p32x_sh2_write8(a,d,sh2)
+#define WW(sh2, a, d) p32x_sh2_write16(a,d,sh2)
+#define WL(sh2, a, d) p32x_sh2_write32(a,d,sh2)
 
 // some stuff from sh2comn.h
 #define T      0x00000001
@@ -29,7 +34,10 @@ typedef unsigned char  UINT8;
 #define Rn     ((opcode>>8)&15)
 #define Rm     ((opcode>>4)&15)
 
-#define sh2_icount sh2->icount
+#define sh2_state SH2
+
+extern void lprintf(const char *fmt, ...);
+#define logerror lprintf
 
 #ifdef SH2_STATS
 static SH2 sh2_stats;
@@ -61,29 +69,51 @@ static unsigned int op_refs[0x10000];
 
 #ifndef DRC_SH2
 
-void sh2_execute(SH2 *sh2_, int cycles)
+int sh2_execute(SH2 *sh2, int cycles)
 {
-       sh2 = sh2_;
-       sh2->cycles_aim += cycles;
-       sh2->icount = cycles = sh2->cycles_aim - sh2->cycles_done;
+#ifdef DRC_CMP
+       unsigned int base_pc = 0, end_pc = 0;
+       unsigned char op_flags[BLOCK_INSN_LIMIT];
+#endif
+       UINT32 opcode;
+
+       sh2->icount = cycles;
 
        if (sh2->icount <= 0)
-               return;
+               return cycles;
+
+       sh2->cycles_timeslice = cycles;
 
        do
        {
-               UINT32 opcode;
+#ifdef DRC_CMP
+               if (!sh2->delay) {
+                       if (sh2->pc < base_pc || sh2->pc >= end_pc) {
+                               base_pc = sh2->pc;
+                               scan_block(base_pc, sh2->is_slave,
+                                       op_flags, &end_pc, NULL);
+                       }
+                       if ((op_flags[(sh2->pc - base_pc) / 2]
+                               & OF_BTARGET) || sh2->pc == base_pc)
+                       {
+                               if (sh2->icount < 0)
+                                       break;
+                       }
+
+                       do_sh2_trace(sh2, sh2->icount);
+               }
+#endif
 
                if (sh2->delay)
                {
                        sh2->ppc = sh2->delay;
-                       opcode = RW(sh2->delay);
+                       opcode = RW(sh2, sh2->delay);
                        sh2->pc -= 2;
                }
                else
                {
                        sh2->ppc = sh2->pc;
-                       opcode = RW(sh2->pc);
+                       opcode = RW(sh2, sh2->pc);
                }
 
                sh2->delay = 0;
@@ -91,22 +121,22 @@ void sh2_execute(SH2 *sh2_, int cycles)
 
                switch (opcode & ( 15 << 12))
                {
-               case  0<<12: op0000(opcode); break;
-               case  1<<12: op0001(opcode); break;
-               case  2<<12: op0010(opcode); break;
-               case  3<<12: op0011(opcode); break;
-               case  4<<12: op0100(opcode); break;
-               case  5<<12: op0101(opcode); break;
-               case  6<<12: op0110(opcode); break;
-               case  7<<12: op0111(opcode); break;
-               case  8<<12: op1000(opcode); break;
-               case  9<<12: op1001(opcode); break;
-               case 10<<12: op1010(opcode); break;
-               case 11<<12: op1011(opcode); break;
-               case 12<<12: op1100(opcode); break;
-               case 13<<12: op1101(opcode); break;
-               case 14<<12: op1110(opcode); break;
-               default: op1111(opcode); break;
+               case  0<<12: op0000(sh2, opcode); break;
+               case  1<<12: op0001(sh2, opcode); break;
+               case  2<<12: op0010(sh2, opcode); break;
+               case  3<<12: op0011(sh2, opcode); break;
+               case  4<<12: op0100(sh2, opcode); break;
+               case  5<<12: op0101(sh2, opcode); break;
+               case  6<<12: op0110(sh2, opcode); break;
+               case  7<<12: op0111(sh2, opcode); break;
+               case  8<<12: op1000(sh2, opcode); break;
+               case  9<<12: op1001(sh2, opcode); break;
+               case 10<<12: op1010(sh2, opcode); break;
+               case 11<<12: op1011(sh2, opcode); break;
+               case 12<<12: op1100(sh2, opcode); break;
+               case 13<<12: op1101(sh2, opcode); break;
+               case 14<<12: op1110(sh2, opcode); break;
+               default: op1111(sh2, opcode); break;
                }
 
                sh2->icount--;
@@ -120,47 +150,16 @@ void sh2_execute(SH2 *sh2_, int cycles)
                }
 
        }
+#ifndef DRC_CMP
        while (sh2->icount > 0 || sh2->delay);  /* can't interrupt before delay */
-
-       sh2->cycles_done += cycles - sh2->icount;
-}
-
-#else // DRC_SH2
-
-#ifdef __i386__
-#define REGPARM(x) __attribute__((regparm(x)))
 #else
-#define REGPARM(x)
+       while (1);
 #endif
 
-// drc debug
-void REGPARM(2) sh2_do_op(SH2 *sh2_, int opcode)
-{
-       sh2 = sh2_;
-       sh2->pc += 2;
-
-       switch (opcode & ( 15 << 12))
-       {
-               case  0<<12: op0000(opcode); break;
-               case  1<<12: op0001(opcode); break;
-               case  2<<12: op0010(opcode); break;
-               case  3<<12: op0011(opcode); break;
-               case  4<<12: op0100(opcode); break;
-               case  5<<12: op0101(opcode); break;
-               case  6<<12: op0110(opcode); break;
-               case  7<<12: op0111(opcode); break;
-               case  8<<12: op1000(opcode); break;
-               case  9<<12: op1001(opcode); break;
-               case 10<<12: op1010(opcode); break;
-               case 11<<12: op1011(opcode); break;
-               case 12<<12: op1100(opcode); break;
-               case 13<<12: op1101(opcode); break;
-               case 14<<12: op1110(opcode); break;
-               default: op1111(opcode); break;
-       }
+       return sh2->cycles_timeslice - sh2->icount;
 }
 
-#endif
+#endif // DRC_SH2
 
 #ifdef SH2_STATS
 #include <stdio.h>
fast MegaDrive/MegaCD/32X emulator