32x: drc: inline dispatcher and irq handling; do write-caused irqs

[picodrive.git] / cpu / sh2 / sh2.h

diff --git a/cpu/sh2/sh2.h b/cpu/sh2/sh2.h
index 975b077..074b142 100644 (file)
--- a/cpu/sh2/sh2.h
+++ b/cpu/sh2/sh2.h
@@ -1,17 +1,20 @@
 #ifndef __SH2_H__\r
 #define __SH2_H__\r
 \r
-// pico memhandlers\r
-// XXX: move somewhere else\r
-unsigned int p32x_sh2_read8(unsigned int a, int id);\r
-unsigned int p32x_sh2_read16(unsigned int a, int id);\r
-unsigned int p32x_sh2_read32(unsigned int a, int id);\r
-void p32x_sh2_write8(unsigned int a, unsigned int d, int id);\r
-void p32x_sh2_write16(unsigned int a, unsigned int d, int id);\r
-void p32x_sh2_write32(unsigned int a, unsigned int d, int id);\r
+#if !defined(REGPARM) && defined(__i386__) \r
+#define REGPARM(x) __attribute__((regparm(x)))\r
+#else\r
+#define REGPARM(x)\r
+#endif\r
 \r
+// registers - matches structure order\r
+typedef enum {\r
+  SHR_R0 = 0, SHR_SP = 15,\r
+  SHR_PC,  SHR_PPC, SHR_PR,   SHR_SR,\r
+  SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,\r
+} sh2_reg_e;\r
 \r
-typedef struct\r
+typedef struct SH2_\r
 {\r
        unsigned int    r[16];          // 00\r
        unsigned int    pc;             // 40\r
@@ -21,34 +24,51 @@ typedef struct
        unsigned int    gbr, vbr;       // 50\r
        unsigned int    mach, macl;     // 58\r
 \r
+       // common\r
+       const void      *read8_map;     // 60\r
+       const void      *read16_map;\r
+       const void      **write8_tab;\r
+       const void      **write16_tab;\r
+\r
+       // drc stuff\r
+       int             drc_tmp;        // 70\r
+       int             irq_cycles;\r
+\r
        // interpreter stuff\r
-       int             icount;         // 60 cycles left in current timeslice\r
+       int             icount;         // cycles left in current timeslice\r
        unsigned int    ea;\r
        unsigned int    delay;\r
        unsigned int    test_irq;\r
 \r
-       // drc stuff\r
-       void    **pc_hashtab;           // 70\r
-\r
-       // common\r
+       int     pending_level;          // MAX(pending_irl, pending_int_irq)\r
        int     pending_irl;\r
        int     pending_int_irq;        // internal irq\r
        int     pending_int_vector;\r
-       void    (*irq_callback)(int id, int level);\r
+       int     REGPARM(2) (*irq_callback)(struct SH2_ *sh2, int level);\r
        int     is_slave;\r
 \r
        unsigned int    cycles_aim;     // subtract sh2_icount to get global counter\r
        unsigned int    cycles_done;\r
 } SH2;\r
 \r
-extern SH2 *sh2; // active sh2\r
+extern SH2 *sh2; // active sh2. XXX: consider removing\r
 \r
 int  sh2_init(SH2 *sh2, int is_slave);\r
 void sh2_finish(SH2 *sh2);\r
 void sh2_reset(SH2 *sh2);\r
 void sh2_irl_irq(SH2 *sh2, int level);\r
 void sh2_internal_irq(SH2 *sh2, int level, int vector);\r
+void sh2_do_irq(SH2 *sh2, int level, int vector);\r
 \r
 void sh2_execute(SH2 *sh2, int cycles);\r
 \r
+// pico memhandlers\r
+// XXX: move somewhere else\r
+unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);\r
+unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);\r
+unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);\r
+int REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);\r
+int REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
+int REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
+\r
 #endif /* __SH2_H__ */\r