\r
unsigned int cycles_timeslice;\r
\r
+ struct SH2_ *other_sh2;\r
+\r
// we use 68k reference cycles for easier sync\r
unsigned int m68krcycles_done;\r
unsigned int mult_m68k_to_sh2;\r
unsigned int mult_sh2_to_m68k;\r
+\r
+ unsigned char data_array[0x1000]; // cache (can be used as RAM)\r
+ unsigned int peri_regs[0x200/4]; // periphereal regs\r
} SH2;\r
\r
#define CYCLE_MULT_SHIFT 10\r
#define C_SH2_TO_M68K(xsh2, c) \\r
((int)((c + 3) * (xsh2).mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)\r
\r
-int sh2_init(SH2 *sh2, int is_slave);\r
+int sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2);\r
void sh2_finish(SH2 *sh2);\r
void sh2_reset(SH2 *sh2);\r
int sh2_irl_irq(SH2 *sh2, int level, int nested_call);\r
unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);\r
unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);\r
unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);\r
-int REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);\r
-int REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
-int REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
+void REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);\r
+void REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
+void REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
\r
// debug\r
#ifdef DRC_CMP\r