#define LIGHTREC_IO_RAM 0x3
#define LIGHTREC_IO_BIOS 0x4
#define LIGHTREC_IO_SCRATCH 0x5
+#define LIGHTREC_IO_DIRECT_HW 0x6
#define LIGHTREC_IO_MASK LIGHTREC_IO_MODE(0x7)
#define LIGHTREC_FLAGS_GET_IO_MODE(x) \
(((x) & LIGHTREC_IO_MASK) >> LIGHTREC_IO_MODE_LSB)
OP_META_EXTC = 0x17,
OP_META_EXTS = 0x18,
+
+ OP_META_MULT2 = 0x19,
+ OP_META_MULTU2 = 0x1a,
};
enum special_opcodes {
enum cp2_opcodes {
OP_CP2_BASIC = 0x00,
+ OP_CP2_RTPS = 0x01,
+ OP_CP2_NCLIP = 0x06,
+ OP_CP2_OP = 0x0c,
+ OP_CP2_DPCS = 0x10,
+ OP_CP2_INTPL = 0x11,
+ OP_CP2_MVMVA = 0x12,
+ OP_CP2_NCDS = 0x13,
+ OP_CP2_CDP = 0x14,
+ OP_CP2_NCDT = 0x16,
+ OP_CP2_NCCS = 0x1b,
+ OP_CP2_CC = 0x1c,
+ OP_CP2_NCS = 0x1e,
+ OP_CP2_NCT = 0x20,
+ OP_CP2_SQR = 0x28,
+ OP_CP2_DCPL = 0x29,
+ OP_CP2_DPCT = 0x2a,
+ OP_CP2_AVSZ3 = 0x2d,
+ OP_CP2_AVSZ4 = 0x2e,
+ OP_CP2_RTPT = 0x30,
+ OP_CP2_GPF = 0x3d,
+ OP_CP2_GPL = 0x3e,
+ OP_CP2_NCCT = 0x3f,
};
enum cp2_basic_opcodes {
u32 flags;
};
+struct opcode_list {
+ u16 nb_ops;
+ struct opcode ops[];
+};
+
void lightrec_print_disassembly(const struct block *block, const u32 *code);
static inline _Bool op_flag_no_ds(u32 flags)