#ifndef FLAGLESS
+const unsigned char gte_cycletab[64] = {
+ /* 1 2 3 4 5 6 7 8 9 a b c d e f */
+ 0, 15, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 6, 0, 0, 0,
+ 8, 8, 8, 19, 13, 0, 44, 0, 0, 0, 0, 17, 11, 0, 14, 0,
+ 30, 0, 0, 0, 0, 0, 0, 0, 5, 8, 17, 0, 0, 5, 6, 0,
+ 23, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 5, 39,
+};
+
+// warning: called by the dynarec
+int gteCheckStallRaw(u32 op_cycles, psxRegisters *regs) {
+ u32 left = regs->gteBusyCycle - regs->cycle;
+ int stall = 0;
+
+ if (left <= 44) {
+ //printf("c %2u stall %2u %u\n", op_cycles, left, regs->cycle);
+ regs->cycle = regs->gteBusyCycle;
+ stall = left;
+ }
+ regs->gteBusyCycle = regs->cycle + op_cycles;
+ return stall;
+}
+
+void gteCheckStall(u32 op) {
+ gteCheckStallRaw(gte_cycletab[op], &psxRegs);
+}
+
static inline u32 MFC2(int reg) {
psxCP2Regs *regs = &psxRegs.CP2;
switch (reg) {
case 28:
gteIRGB = value;
- gteIR1 = (value & 0x1f) << 7;
- gteIR2 = (value & 0x3e0) << 2;
- gteIR3 = (value & 0x7c00) >> 3;
+ // not gteIR1 etc. just to be consistent with dynarec
+ regs->CP2D.n.ir1 = (value & 0x1f) << 7;
+ regs->CP2D.n.ir2 = (value & 0x3e0) << 2;
+ regs->CP2D.n.ir3 = (value & 0x7c00) >> 3;
break;
case 30:
psxMemWrite32(_oB_, MFC2(_Rt_));
}
+void gteLWC2_stall() {
+ gteCheckStall(0);
+ gteLWC2();
+}
+
+void gteSWC2_stall() {
+ gteCheckStall(0);
+ gteSWC2();
+}
+
#endif // FLAGLESS
#if 0