#include <lightrec.h>
+#include <errno.h>
#include <stdbool.h>
#include <stdio.h>
#include <unistd.h>
#include <signal.h>
+#include <assert.h>
+
+#if P_HAVE_MMAP
+#include <sys/mman.h>
+#endif
#include "../cdrom.h"
#include "../gpu.h"
#include "../psxhw.h"
#include "../psxmem.h"
#include "../r3000a.h"
+#include "../psxinterpreter.h"
+#include "../psxhle.h"
+#include "../psxevents.h"
#include "../frontend/main.h"
+#include "mem.h"
+#include "plugin.h"
+
+#if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
+#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
+#endif
+
#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
psxRegisters psxRegs;
Rcnt rcnts[4];
+void* code_buffer;
+
static struct lightrec_state *lightrec_state;
static char *name = "retroarch.exe";
static bool use_lightrec_interpreter;
static bool use_pcsx_interpreter;
-static bool lightrec_debug;
-static bool lightrec_very_debug;
-static bool booting;
-static u32 lightrec_begin_cycles;
+static bool block_stepping;
+
+extern u32 lightrec_hacks;
enum my_cp2_opcodes {
OP_CP2_RTPS = 0x01,
static bool has_interrupt(void)
{
+ struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
+
return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
- (psxRegs.CP0.n.Status & 0x401) == 0x401) ||
- (psxRegs.CP0.n.Status & psxRegs.CP0.n.Cause & 0x0300);
+ (regs->cp0[12] & 0x401) == 0x401) ||
+ (regs->cp0[12] & regs->cp0[13] & 0x0300);
+}
+
+static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
+{
+ psxRegs.cycle += lightrec_current_cycle_count(state) / 1024;
+ lightrec_reset_cycle_count(state, 0);
}
-static void lightrec_restore_state(struct lightrec_state *state)
+static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
{
- lightrec_reset_cycle_count(state, psxRegs.cycle);
+ s32 cycles_left = next_interupt - psxRegs.cycle;
- if (booting || has_interrupt())
+ if (block_stepping || cycles_left <= 0 || has_interrupt())
lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
- else
- lightrec_set_target_cycle_count(state, next_interupt);
+ else {
+ lightrec_set_target_cycle_count(state, cycles_left * 1024);
+ }
}
static void hw_write_byte(struct lightrec_state *state,
u32 op, void *host, u32 mem, u8 val)
{
- psxRegs.cycle = lightrec_current_cycle_count(state);
+ lightrec_tansition_to_pcsx(state);
psxHwWrite8(mem, val);
- lightrec_restore_state(state);
+ lightrec_tansition_from_pcsx(state);
}
static void hw_write_half(struct lightrec_state *state,
u32 op, void *host, u32 mem, u16 val)
{
- psxRegs.cycle = lightrec_current_cycle_count(state);
+ lightrec_tansition_to_pcsx(state);
psxHwWrite16(mem, val);
- lightrec_restore_state(state);
+ lightrec_tansition_from_pcsx(state);
}
static void hw_write_word(struct lightrec_state *state,
u32 op, void *host, u32 mem, u32 val)
{
- psxRegs.cycle = lightrec_current_cycle_count(state);
+ lightrec_tansition_to_pcsx(state);
psxHwWrite32(mem, val);
- lightrec_restore_state(state);
+ lightrec_tansition_from_pcsx(state);
}
static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
{
u8 val;
- psxRegs.cycle = lightrec_current_cycle_count(state);
+ lightrec_tansition_to_pcsx(state);
val = psxHwRead8(mem);
- lightrec_restore_state(state);
+ lightrec_tansition_from_pcsx(state);
return val;
}
{
u16 val;
- psxRegs.cycle = lightrec_current_cycle_count(state);
+ lightrec_tansition_to_pcsx(state);
val = psxHwRead16(mem);
- lightrec_restore_state(state);
+ lightrec_tansition_from_pcsx(state);
return val;
}
{
u32 val;
- psxRegs.cycle = lightrec_current_cycle_count(state);
+ lightrec_tansition_to_pcsx(state);
val = psxHwRead32(mem);
- lightrec_restore_state(state);
+ lightrec_tansition_from_pcsx(state);
return val;
}
[PSX_MAP_HW_REGISTERS] = {
/* Hardware registers */
.pc = 0x1f801000,
- .length = 0x2000,
+ .length = 0x8000,
.ops = &hw_regs_ops,
},
[PSX_MAP_CACHE_CONTROL] = {
.length = 0x200000,
.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
},
+
+ /* Mirror of the parallel port. Only used by the PS2/PS3 BIOS */
+ [PSX_MAP_PPORT_MIRROR] = {
+ .pc = 0x1fa00000,
+ .length = 0x10000,
+ .mirror_of = &lightrec_map[PSX_MAP_PARALLEL_PORT],
+ },
+
+ /* Code buffer */
+ [PSX_MAP_CODE_BUFFER] = {
+ .length = CODE_BUFFER_SIZE,
+ },
};
static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
memcpy(cache_buf, psxM, sizeof(cache_buf));
}
+static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
+{
+ switch (size) {
+ case 8:
+ switch (kaddr) {
+ case 0x1f801040:
+ case 0x1f801050:
+ case 0x1f801800:
+ case 0x1f801801:
+ case 0x1f801802:
+ case 0x1f801803:
+ return false;
+ default:
+ return true;
+ }
+ case 16:
+ switch (kaddr) {
+ case 0x1f801040:
+ case 0x1f801044:
+ case 0x1f801048:
+ case 0x1f80104a:
+ case 0x1f80104e:
+ case 0x1f801050:
+ case 0x1f801054:
+ case 0x1f80105a:
+ case 0x1f80105e:
+ case 0x1f801100:
+ case 0x1f801104:
+ case 0x1f801108:
+ case 0x1f801110:
+ case 0x1f801114:
+ case 0x1f801118:
+ case 0x1f801120:
+ case 0x1f801124:
+ case 0x1f801128:
+ return false;
+ case 0x1f801070:
+ case 0x1f801074:
+ return !is_write;
+ default:
+ return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
+ }
+ default:
+ switch (kaddr) {
+ case 0x1f801040:
+ case 0x1f801050:
+ case 0x1f801100:
+ case 0x1f801104:
+ case 0x1f801108:
+ case 0x1f801110:
+ case 0x1f801114:
+ case 0x1f801118:
+ case 0x1f801120:
+ case 0x1f801124:
+ case 0x1f801128:
+ case 0x1f801810:
+ case 0x1f801814:
+ case 0x1f801820:
+ case 0x1f801824:
+ return false;
+ case 0x1f801070:
+ case 0x1f801074:
+ case 0x1f801088:
+ case 0x1f801098:
+ case 0x1f8010a8:
+ case 0x1f8010b8:
+ case 0x1f8010c8:
+ case 0x1f8010e8:
+ case 0x1f8010f4:
+ return !is_write;
+ default:
+ return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
+ }
+ }
+}
+
+#if defined(HW_DOL) || defined(HW_RVL)
+static void lightrec_code_inv(void *ptr, uint32_t len)
+{
+ extern void DCFlushRange(void *ptr, u32 len);
+ extern void ICInvalidateRange(void *ptr, u32 len);
+
+ DCFlushRange(ptr, len);
+ ICInvalidateRange(ptr, len);
+}
+#elif defined(HW_WUP)
+static void lightrec_code_inv(void *ptr, uint32_t len)
+{
+ wiiu_clear_cache(ptr, (void *)((uintptr_t)ptr + len));
+}
+#endif
+
static const struct lightrec_ops lightrec_ops = {
.cop2_op = cop2_op,
.enable_ram = lightrec_enable_ram,
+ .hw_direct = lightrec_can_hw_direct,
+#if defined(HW_DOL) || defined(HW_RVL) || defined(HW_WUP)
+ .code_inv = lightrec_code_inv,
+#endif
};
static int lightrec_plugin_init(void)
lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
lightrec_map[PSX_MAP_BIOS].address = psxR;
lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
+ lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
- lightrec_debug = !!getenv("LIGHTREC_DEBUG");
- lightrec_very_debug = !!getenv("LIGHTREC_VERY_DEBUG");
+ if (!LIGHTREC_CUSTOM_MAP) {
+#if P_HAVE_MMAP
+ code_buffer = mmap(0, CODE_BUFFER_SIZE,
+ PROT_EXEC | PROT_READ | PROT_WRITE,
+ MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+ if (code_buffer == MAP_FAILED)
+ return -ENOMEM;
+#else
+ code_buffer = malloc(CODE_BUFFER_SIZE);
+ if (!code_buffer)
+ return -ENOMEM;
+#endif
+ }
+
+ if (LIGHTREC_CUSTOM_MAP) {
+ lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
+ lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
+ lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
+ }
+
+ lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
+
use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
- if (getenv("LIGHTREC_BEGIN_CYCLES"))
- lightrec_begin_cycles = (unsigned int) strtol(
- getenv("LIGHTREC_BEGIN_CYCLES"), NULL, 0);
lightrec_state = lightrec_init(name,
lightrec_map, ARRAY_SIZE(lightrec_map),
return 0;
}
-static u32 hash_calculate_le(const void *buffer, u32 count)
-{
- unsigned int i;
- u32 *data = (u32 *) buffer;
- u32 hash = 0xffffffff;
-
- count /= 4;
- for(i = 0; i < count; ++i) {
- hash += LE32TOH(data[i]);
- hash += (hash << 10);
- hash ^= (hash >> 6);
- }
-
- hash += (hash << 3);
- hash ^= (hash >> 11);
- hash += (hash << 15);
- return hash;
-}
-
-static u32 hash_calculate(const void *buffer, u32 count)
-{
- unsigned int i;
- u32 *data = (u32 *) buffer;
- u32 hash = 0xffffffff;
-
- count /= 4;
- for(i = 0; i < count; ++i) {
- hash += data[i];
- hash += (hash << 10);
- hash ^= (hash >> 6);
- }
-
- hash += (hash << 3);
- hash ^= (hash >> 11);
- hash += (hash << 15);
- return hash;
-}
-
-static const char * const mips_regs[] = {
- "zero",
- "at",
- "v0", "v1",
- "a0", "a1", "a2", "a3",
- "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
- "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
- "t8", "t9",
- "k0", "k1",
- "gp", "sp", "fp", "ra",
- "lo", "hi",
-};
-
-static void print_for_big_ass_debugger(void)
-{
- unsigned int i;
-
- printf("CYCLE 0x%08x PC 0x%08x", psxRegs.cycle, psxRegs.pc);
-
- if (lightrec_very_debug)
- printf(" RAM 0x%08x SCRATCH 0x%08x HW 0x%08x",
- hash_calculate_le(psxM, 0x200000),
- hash_calculate_le(psxH, 0x400),
- hash_calculate_le(psxH + 0x1000, 0x2000));
-
- printf(" CP0 0x%08x CP2D 0x%08x CP2C 0x%08x INT 0x%04x INTCYCLE 0x%08x GPU 0x%08x",
- hash_calculate(&psxRegs.CP0.r,
- sizeof(psxRegs.CP0.r)),
- hash_calculate(&psxRegs.CP2D.r,
- sizeof(psxRegs.CP2D.r)),
- hash_calculate(&psxRegs.CP2C.r,
- sizeof(psxRegs.CP2C.r)),
- psxRegs.interrupt,
- hash_calculate(psxRegs.intCycle,
- sizeof(psxRegs.intCycle)),
- LE32TOH(HW_GPU_STATUS));
-
- if (lightrec_very_debug)
- for (i = 0; i < 34; i++)
- printf(" %s 0x%08x", mips_regs[i], psxRegs.GPR.r[i]);
- else
- printf(" GPR 0x%08x", hash_calculate(&psxRegs.GPR.r,
- sizeof(psxRegs.GPR.r)));
- printf("\n");
-}
-
-static void lightrec_dump_regs(struct lightrec_state *state)
-{
- struct lightrec_registers *regs = lightrec_get_registers(state);
-
- if (unlikely(booting))
- memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
- psxRegs.CP0.n.Status = regs->cp0[12];
- psxRegs.CP0.n.Cause = regs->cp0[13];
-}
+static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2);
+static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2);
-static void lightrec_restore_regs(struct lightrec_state *state)
+static void lightrec_plugin_execute_internal(bool block_only)
{
- struct lightrec_registers *regs = lightrec_get_registers(state);
-
- if (unlikely(booting))
- memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
- regs->cp0[12] = psxRegs.CP0.n.Status;
- regs->cp0[13] = psxRegs.CP0.n.Cause;
- regs->cp0[14] = psxRegs.CP0.n.EPC;
-}
+ struct lightrec_registers *regs;
+ u32 flags, cycles_pcsx;
-extern void intExecuteBlock();
-extern void gen_interupt();
+ regs = lightrec_get_registers(lightrec_state);
+ gen_interupt((psxCP0Regs *)regs->cp0);
+ if (!block_only && stop)
+ return;
-static void lightrec_plugin_execute_block(void)
-{
- u32 old_pc = psxRegs.pc;
- u32 flags;
+ cycles_pcsx = next_interupt - psxRegs.cycle;
+ assert((s32)cycles_pcsx > 0);
- gen_interupt();
+ // step during early boot so that 0x80030000 fastboot hack works
+ block_stepping = block_only;
+ if (block_only)
+ cycles_pcsx = 0;
if (use_pcsx_interpreter) {
- intExecuteBlock();
+ intExecuteBlock(0);
} else {
- lightrec_reset_cycle_count(lightrec_state, psxRegs.cycle);
- lightrec_restore_regs(lightrec_state);
-
- if (unlikely(use_lightrec_interpreter))
+ u32 cycles_lightrec = cycles_pcsx * 1024;
+ if (unlikely(use_lightrec_interpreter)) {
psxRegs.pc = lightrec_run_interpreter(lightrec_state,
- psxRegs.pc);
- // step during early boot so that 0x80030000 fastboot hack works
- else if (unlikely(booting || lightrec_debug))
- psxRegs.pc = lightrec_execute_one(lightrec_state,
- psxRegs.pc);
- else
+ psxRegs.pc,
+ cycles_lightrec);
+ } else {
psxRegs.pc = lightrec_execute(lightrec_state,
- psxRegs.pc, next_interupt);
+ psxRegs.pc, cycles_lightrec);
+ }
- psxRegs.cycle = lightrec_current_cycle_count(lightrec_state);
+ lightrec_tansition_to_pcsx(lightrec_state);
- lightrec_dump_regs(lightrec_state);
flags = lightrec_exit_flags(lightrec_state);
if (flags & LIGHTREC_EXIT_SEGFAULT) {
}
if (flags & LIGHTREC_EXIT_SYSCALL)
- psxException(0x20, 0);
-
- if (booting && (psxRegs.pc & 0xff800000) == 0x80000000)
- booting = false;
+ psxException(R3000E_Syscall << 2, 0, (psxCP0Regs *)regs->cp0);
+ if (flags & LIGHTREC_EXIT_BREAK)
+ psxException(R3000E_Bp << 2, 0, (psxCP0Regs *)regs->cp0);
+ else if (flags & LIGHTREC_EXIT_UNKNOWN_OP) {
+ u32 op = intFakeFetch(psxRegs.pc);
+ u32 hlec = op & 0x03ffffff;
+ if ((op >> 26) == 0x3b && hlec < ARRAY_SIZE(psxHLEt) && Config.HLE) {
+ lightrec_plugin_sync_regs_to_pcsx(0);
+ psxHLEt[hlec]();
+ lightrec_plugin_sync_regs_from_pcsx(0);
+ }
+ else
+ psxException(R3000E_RI << 2, 0, (psxCP0Regs *)regs->cp0);
+ }
}
- if (lightrec_debug && psxRegs.cycle >= lightrec_begin_cycles
- && psxRegs.pc != old_pc)
- print_for_big_ass_debugger();
-
- if ((psxRegs.CP0.n.Cause & psxRegs.CP0.n.Status & 0x300) &&
- (psxRegs.CP0.n.Status & 0x1)) {
+ if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
/* Handle software interrupts */
- psxRegs.CP0.n.Cause &= ~0x7c;
- psxException(psxRegs.CP0.n.Cause, 0);
+ regs->cp0[13] &= ~0x7c;
+ psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
}
}
static void lightrec_plugin_execute(void)
{
- extern int stop;
-
while (!stop)
- lightrec_plugin_execute_block();
+ lightrec_plugin_execute_internal(false);
+}
+
+static void lightrec_plugin_execute_block(enum blockExecCaller caller)
+{
+ lightrec_plugin_execute_internal(true);
}
static void lightrec_plugin_clear(u32 addr, u32 size)
lightrec_invalidate(lightrec_state, addr, size * 4);
}
-static void lightrec_plugin_notify(int note, void *data)
+static void lightrec_plugin_notify(enum R3000Anote note, void *data)
{
- /*
- To change once proper icache emulation is emulated
switch (note)
{
- case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
- lightrec_plugin_clear(0, 0x200000/4);
- break;
- case R3000ACPU_NOTIFY_CACHE_ISOLATED:
- // Sent from psxDma3().
- case R3000ACPU_NOTIFY_DMA3_EXE_LOAD:
- default:
- break;
- }*/
+ case R3000ACPU_NOTIFY_CACHE_ISOLATED:
+ case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
+ /* not used, lightrec calls lightrec_enable_ram() instead */
+ break;
+ case R3000ACPU_NOTIFY_BEFORE_SAVE:
+ /* non-null 'data' means this is HLE related sync */
+ lightrec_plugin_sync_regs_to_pcsx(data == NULL);
+ break;
+ case R3000ACPU_NOTIFY_AFTER_LOAD:
+ lightrec_plugin_sync_regs_from_pcsx(data == NULL);
+ if (data == NULL)
+ lightrec_invalidate_all(lightrec_state);
+ break;
+ }
}
static void lightrec_plugin_apply_config()
{
+ u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
+ ? Config.cycle_multiplier_override : Config.cycle_multiplier;
+ assert(cycle_mult);
+
+ lightrec_set_cycles_per_opcode(lightrec_state, cycle_mult * 1024 / 100);
}
static void lightrec_plugin_shutdown(void)
{
lightrec_destroy(lightrec_state);
+
+ if (!LIGHTREC_CUSTOM_MAP) {
+#if P_HAVE_MMAP
+ munmap(code_buffer, CODE_BUFFER_SIZE);
+#else
+ free(code_buffer);
+#endif
+ }
}
static void lightrec_plugin_reset(void)
{
struct lightrec_registers *regs;
- lightrec_plugin_shutdown();
- lightrec_plugin_init();
-
regs = lightrec_get_registers(lightrec_state);
+ /* Invalidate all blocks */
+ lightrec_invalidate_all(lightrec_state);
+
+ /* Reset registers */
+ memset(regs, 0, sizeof(*regs));
+
regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
- booting = true;
+ lightrec_set_unsafe_opt_flags(lightrec_state, lightrec_hacks);
+}
+
+static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2)
+{
+ struct lightrec_registers *regs;
+
+ regs = lightrec_get_registers(lightrec_state);
+ memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
+ memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
+ if (need_cp2)
+ memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
+}
+
+static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2)
+{
+ struct lightrec_registers *regs;
+
+ regs = lightrec_get_registers(lightrec_state);
+ memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
+ memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
+ if (need_cp2)
+ memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
}
R3000Acpu psxRec =
notaz.gp2x.de / pcsx_rearmed.git / blobdiff