-#include <lightrec.h>
#include <errno.h>
#include <stdbool.h>
#include <stdio.h>
#include <sys/mman.h>
#endif
+#include "lightrec.h"
#include "../cdrom.h"
#include "../gpu.h"
#include "../gte.h"
#include "../psxmem.h"
#include "../r3000a.h"
#include "../psxinterpreter.h"
-#include "../new_dynarec/events.h"
+#include "../psxhle.h"
+#include "../psxevents.h"
#include "../frontend/main.h"
# define unlikely(x) (x)
#endif
+#ifndef LIGHTREC_PROG_NAME
+# ifdef __linux__
+# define LIGHTREC_PROG_NAME "/proc/self/exe"
+# else
+# define LIGHTREC_PROG_NAME "retroarch.exe"
+# endif
+#endif
+
+#ifndef GPUSTATUS_POLLING_THRESHOLD
+# define GPUSTATUS_POLLING_THRESHOLD 0
+#endif
+
psxRegisters psxRegs;
Rcnt rcnts[4];
static struct lightrec_state *lightrec_state;
-static char *name = "retroarch.exe";
-
static bool use_lightrec_interpreter;
-static bool use_pcsx_interpreter;
static bool block_stepping;
+//static bool use_pcsx_interpreter;
+#define use_pcsx_interpreter 0
+static bool ram_disabled;
+static bool lightrec_debug, lightrec_very_debug;
+static u32 lightrec_begin_cycles;
+
+extern u32 lightrec_hacks;
+
+static void lightrec_plugin_apply_config();
+extern void lightrec_code_inv(void *ptr, uint32_t len);
enum my_cp2_opcodes {
OP_CP2_RTPS = 0x01,
};
static void (*cp2_ops[])(struct psxCP2Regs *) = {
- [OP_CP2_RTPS] = gteRTPS,
[OP_CP2_RTPS] = gteRTPS,
[OP_CP2_NCLIP] = gteNCLIP,
[OP_CP2_OP] = gteOP,
static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
{
- s32 cycles_left = next_interupt - psxRegs.cycle;
+ s32 cycles_left = psxRegs.next_interupt - psxRegs.cycle;
if (block_stepping || cycles_left <= 0 || has_interrupt())
lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
}
static void hw_write_byte(struct lightrec_state *state,
- u32 op, void *host, u32 mem, u8 val)
+ u32 op, void *host, u32 mem, u32 val)
{
lightrec_tansition_to_pcsx(state);
}
static void hw_write_half(struct lightrec_state *state,
- u32 op, void *host, u32 mem, u16 val)
+ u32 op, void *host, u32 mem, u32 val)
{
lightrec_tansition_to_pcsx(state);
static u32 hw_read_word(struct lightrec_state *state,
u32 op, void *host, u32 mem)
{
- u32 val;
+ static u32 old_cycle, oldold_cycle, old_gpusr;
+ u32 val, diff;
lightrec_tansition_to_pcsx(state);
val = psxHwRead32(mem);
+ if (GPUSTATUS_POLLING_THRESHOLD > 0 && mem == 0x1f801814) {
+ diff = psxRegs.cycle - old_cycle;
+
+ if (diff > 0
+ && diff < GPUSTATUS_POLLING_THRESHOLD
+ && diff == old_cycle - oldold_cycle) {
+ while (psxRegs.next_interupt > psxRegs.cycle && val == old_gpusr) {
+ psxRegs.cycle += diff;
+ val = psxHwRead32(mem);
+ }
+ }
+
+ oldold_cycle = old_cycle;
+ old_cycle = psxRegs.cycle;
+ old_gpusr = val;
+ }
+
lightrec_tansition_from_pcsx(state);
return val;
memcpy(psxM, cache_buf, sizeof(cache_buf));
else
memcpy(cache_buf, psxM, sizeof(cache_buf));
+
+ ram_disabled = !enable;
}
static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
{
+ if (is_write && size != 32) {
+ // force32 so must go through handlers
+ if (0x1f801000 <= kaddr && kaddr < 0x1f801024)
+ return false;
+ if ((kaddr & 0x1fffff80) == 0x1f801080) // dma
+ return false;
+ }
+
switch (size) {
case 8:
switch (kaddr) {
}
}
-#if defined(HW_DOL) || defined(HW_RVL)
-static void lightrec_code_inv(void *ptr, uint32_t len)
-{
- extern void DCFlushRange(void *ptr, u32 len);
- extern void ICInvalidateRange(void *ptr, u32 len);
-
- DCFlushRange(ptr, len);
- ICInvalidateRange(ptr, len);
-}
-#elif defined(HW_WUP)
-static void lightrec_code_inv(void *ptr, uint32_t len)
-{
- wiiu_clear_cache(ptr, (void *)((uintptr_t)ptr + len));
-}
-#endif
-
static const struct lightrec_ops lightrec_ops = {
.cop2_op = cop2_op,
.enable_ram = lightrec_enable_ram,
.hw_direct = lightrec_can_hw_direct,
-#if defined(HW_DOL) || defined(HW_RVL) || defined(HW_WUP)
- .code_inv = lightrec_code_inv,
-#endif
+ .code_inv = LIGHTREC_CODE_INV ? lightrec_code_inv : NULL,
};
static int lightrec_plugin_init(void)
use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
- lightrec_state = lightrec_init(name,
+#ifdef LIGHTREC_DEBUG
+ char *cycles = getenv("LIGHTREC_BEGIN_CYCLES");
+
+ lightrec_very_debug = !!getenv("LIGHTREC_VERY_DEBUG");
+ lightrec_debug = lightrec_very_debug || !!getenv("LIGHTREC_DEBUG");
+
+ if (cycles)
+ lightrec_begin_cycles = (unsigned int) strtol(cycles, NULL, 0);
+#endif
+
+ lightrec_state = lightrec_init(LIGHTREC_PROG_NAME,
lightrec_map, ARRAY_SIZE(lightrec_map),
&lightrec_ops);
#ifndef _WIN32
signal(SIGPIPE, exit);
#endif
+ lightrec_plugin_apply_config();
return 0;
}
+static u32 do_calculate_hash(const void *buffer, u32 count, u32 needle, bool le)
+{
+ unsigned int i;
+ const u32 *data = (const u32 *) buffer;
+ u32 hash = needle;
+
+ count /= 4;
+ for(i = 0; i < count; ++i) {
+ hash += le ? LE32TOH(data[i]) : data[i];
+ hash += (hash << 10);
+ hash ^= (hash >> 6);
+ }
+
+ hash += (hash << 3);
+ hash ^= (hash >> 11);
+ hash += (hash << 15);
+
+ return hash;
+}
+
+static u32 hash_calculate_le(const void *buffer, u32 count)
+{
+ return do_calculate_hash(buffer, count, 0xffffffff, true);
+}
+
+u32 hash_calculate(const void *buffer, u32 count)
+{
+ return do_calculate_hash(buffer, count, 0xffffffff, false);
+}
+
+static u32 hash_calculate_ram(const void *buffer, u32 ram_size)
+{
+ u32 hash;
+
+ if (ram_disabled)
+ hash = hash_calculate_le(cache_buf, sizeof(cache_buf));
+ else
+ hash = hash_calculate_le(buffer, sizeof(cache_buf));
+
+ return do_calculate_hash(buffer + sizeof(cache_buf),
+ ram_size - sizeof(cache_buf),
+ hash, true);
+}
+
+static const char * const mips_regs[] = {
+ "zero",
+ "at",
+ "v0", "v1",
+ "a0", "a1", "a2", "a3",
+ "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
+ "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
+ "t8", "t9",
+ "k0", "k1",
+ "gp", "sp", "fp", "ra",
+ "lo", "hi",
+};
+
+static void print_for_big_ass_debugger(void)
+{
+ struct lightrec_registers *regs;
+ unsigned int i;
+
+ regs = lightrec_get_registers(lightrec_state);
+
+ printf("CYCLE 0x%08x PC 0x%08x", psxRegs.cycle, psxRegs.pc);
+
+ if (lightrec_very_debug)
+ printf(" RAM 0x%08x SCRATCH 0x%08x HW 0x%08x",
+ hash_calculate_ram(psxM, 0x200000),
+ hash_calculate_le(psxH, 0x400),
+ hash_calculate_le(psxH + 0x1000, 0x2000));
+
+ printf(" CP0 0x%08x CP2D 0x%08x CP2C 0x%08x INT 0x%04x INTCYCLE 0x%08x GPU 0x%08x",
+ hash_calculate(regs->cp0, sizeof(regs->cp0)),
+ hash_calculate(regs->cp2d, sizeof(regs->cp2d)),
+ hash_calculate(regs->cp2c, sizeof(regs->cp2c)),
+ psxRegs.interrupt,
+ hash_calculate(psxRegs.intCycle, sizeof(psxRegs.intCycle)),
+ LE32TOH(HW_GPU_STATUS));
+
+ if (lightrec_very_debug) {
+ for (i = 0; i < 32; i++)
+ printf(" CP2D%u 0x%08x", i, regs->cp2d[i]);
+ for (i = 0; i < 32; i++)
+ printf(" CP2C%u 0x%08x", i, regs->cp2c[i]);
+ }
+
+ if (lightrec_very_debug)
+ for (i = 0; i < 34; i++)
+ printf(" %s 0x%08x", mips_regs[i], regs->gpr[i]);
+ else
+ printf(" GPR 0x%08x",
+ hash_calculate(regs->gpr, sizeof(regs->gpr)));
+ printf("\n");
+
+ fflush(stdout);
+}
+
+static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2);
+static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2);
+
static void lightrec_plugin_execute_internal(bool block_only)
{
struct lightrec_registers *regs;
u32 flags, cycles_pcsx;
+ u32 old_pc = psxRegs.pc;
regs = lightrec_get_registers(lightrec_state);
gen_interupt((psxCP0Regs *)regs->cp0);
- cycles_pcsx = next_interupt - psxRegs.cycle;
+ if (!block_only && psxRegs.stop)
+ return;
+
+ cycles_pcsx = psxRegs.next_interupt - psxRegs.cycle;
assert((s32)cycles_pcsx > 0);
// step during early boot so that 0x80030000 fastboot hack works
cycles_pcsx = 0;
if (use_pcsx_interpreter) {
- intExecuteBlock(0);
+ psxInt.ExecuteBlock(&psxRegs, 0);
} else {
u32 cycles_lightrec = cycles_pcsx * 1024;
if (unlikely(use_lightrec_interpreter)) {
if (flags & LIGHTREC_EXIT_SEGFAULT) {
fprintf(stderr, "Exiting at cycle 0x%08x\n",
psxRegs.cycle);
+ if (lightrec_debug)
+ print_for_big_ass_debugger();
exit(1);
}
if (flags & LIGHTREC_EXIT_SYSCALL)
- psxException(0x20, 0, (psxCP0Regs *)regs->cp0);
+ psxException(R3000E_Syscall << 2, 0, (psxCP0Regs *)regs->cp0);
+ if (flags & LIGHTREC_EXIT_BREAK)
+ psxException(R3000E_Bp << 2, 0, (psxCP0Regs *)regs->cp0);
+ else if (flags & LIGHTREC_EXIT_UNKNOWN_OP) {
+ u32 op = intFakeFetch(psxRegs.pc);
+ u32 hlec = op & 0x03ffffff;
+ if ((op >> 26) == 0x3b && hlec < ARRAY_SIZE(psxHLEt) && Config.HLE) {
+ lightrec_plugin_sync_regs_to_pcsx(0);
+ psxHLEt[hlec]();
+ lightrec_plugin_sync_regs_from_pcsx(0);
+ }
+ else
+ psxException(R3000E_RI << 2, 0, (psxCP0Regs *)regs->cp0);
+ }
+ }
+
+ if (lightrec_debug && psxRegs.cycle >= lightrec_begin_cycles && psxRegs.pc != old_pc) {
+ print_for_big_ass_debugger();
}
if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
}
}
-static void lightrec_plugin_execute(void)
+static void lightrec_plugin_execute(psxRegisters *regs)
{
- extern int stop;
-
- while (!stop)
- lightrec_plugin_execute_internal(false);
+ while (!regs->stop)
+ lightrec_plugin_execute_internal(lightrec_very_debug);
}
-static void lightrec_plugin_execute_block(enum blockExecCaller caller)
+static void lightrec_plugin_execute_block(psxRegisters *regs,
+ enum blockExecCaller caller)
{
lightrec_plugin_execute_internal(true);
}
static void lightrec_plugin_clear(u32 addr, u32 size)
{
- if (addr == 0 && size == UINT32_MAX)
+ if ((addr == 0 && size == UINT32_MAX)
+ || (lightrec_hacks & LIGHTREC_OPT_INV_DMA_ONLY))
lightrec_invalidate_all(lightrec_state);
else
/* size * 4: PCSX uses DMA units */
lightrec_invalidate(lightrec_state, addr, size * 4);
}
-static void lightrec_plugin_sync_regs_to_pcsx(void);
-static void lightrec_plugin_sync_regs_from_pcsx(void);
-
static void lightrec_plugin_notify(enum R3000Anote note, void *data)
{
switch (note)
/* not used, lightrec calls lightrec_enable_ram() instead */
break;
case R3000ACPU_NOTIFY_BEFORE_SAVE:
- lightrec_plugin_sync_regs_to_pcsx();
+ /* non-null 'data' means this is HLE related sync */
+ lightrec_plugin_sync_regs_to_pcsx(data == NULL);
break;
case R3000ACPU_NOTIFY_AFTER_LOAD:
- lightrec_plugin_sync_regs_from_pcsx();
+ lightrec_plugin_sync_regs_from_pcsx(data == NULL);
+ if (data == NULL)
+ lightrec_invalidate_all(lightrec_state);
break;
}
}
static void lightrec_plugin_apply_config()
{
+ static u32 cycles_per_op_old;
u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
? Config.cycle_multiplier_override : Config.cycle_multiplier;
- assert(cycle_mult);
+ u32 cycles_per_op = cycle_mult * 1024 / 100;
+ assert(cycles_per_op);
+
+ if (cycles_per_op_old && cycles_per_op_old != cycles_per_op) {
+ SysPrintf("lightrec: reinit block cache for cycles_per_op %.2f\n",
+ cycles_per_op / 1024.f);
+ }
+ cycles_per_op_old = cycles_per_op;
+ lightrec_set_cycles_per_opcode(lightrec_state, cycles_per_op);
- lightrec_set_cycles_per_opcode(lightrec_state, cycle_mult * 1024 / 100);
+ lightrec_set_unsafe_opt_flags(lightrec_state, lightrec_hacks);
+ intApplyConfig();
}
static void lightrec_plugin_shutdown(void)
regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
}
-static void lightrec_plugin_sync_regs_from_pcsx(void)
+static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2)
{
struct lightrec_registers *regs;
regs = lightrec_get_registers(lightrec_state);
- memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
- memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
-
- lightrec_invalidate_all(lightrec_state);
+ memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
+ if (need_cp2)
+ memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
}
-static void lightrec_plugin_sync_regs_to_pcsx(void)
+static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2)
{
struct lightrec_registers *regs;
regs = lightrec_get_registers(lightrec_state);
- memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
- memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
+ memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
+ if (need_cp2)
+ memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
}
R3000Acpu psxRec =
notaz.gp2x.de / pcsx_rearmed.git / blobdiff