output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
}
+void emit_orrshl_imm(u_int rs,u_int imm,u_int rt)
+{
+ assert(rs<16);
+ assert(rt<16);
+ assert(imm<32);
+ assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs],imm);
+ output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|(imm<<7));
+}
+
void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
{
assert(rs<16);
assert(s>=0);
emit_writeword(s,(int)&readmem_dword);
wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
-#ifdef MUPEN64 /// FIXME
+#ifdef MUPEN64
emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
emit_movimm((source[i]>>11)&0x1f,1);
emit_writeword(0,(int)&PC);
emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
-#endif
-#ifdef PCSX
- emit_movimm(source[i],0);
- emit_writeword(0,(int)&psxRegs.code);
#endif
if(copr==9||copr==11||copr==12||copr==13) {
emit_readword((int)&last_count,ECX);
// The interrupt must be taken immediately, because a subsequent
// instruction might disable interrupts again.
if(copr==12||copr==13) {
+#ifdef PCSX
+ if (is_delayslot) {
+ // burn cycles to cause cc_interrupt, which will
+ // reschedule next_interupt. Relies on CCREG from above.
+ assem_debug("MTC0 DS %d\n", copr);
+ emit_writeword(HOST_CCREG,(int)&last_count);
+ emit_movimm(0,HOST_CCREG);
+ emit_storereg(CCREG,HOST_CCREG);
+ emit_movimm(copr,0);
+ emit_call((int)pcsx_mtc0_ds);
+ return;
+ }
+#endif
emit_movimm(start+i*4+4,0);
emit_movimm(0,1);
emit_writeword(0,(int)&pcaddr);
}
//else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
//else
+#ifdef PCSX
+ emit_movimm(copr,0);
+ emit_call((int)pcsx_mtc0);
+#else
emit_call((int)MTC0);
+#endif
if(copr==9||copr==11||copr==12||copr==13) {
emit_readword((int)&Count,HOST_CCREG);
emit_readword((int)&next_interupt,ECX);
emit_testimm(temp,0x8000); // do we need this?
emit_andimm(temp,0xf80,temp);
emit_andne_imm(temp,0,temp);
- emit_shr(temp,7,tl);
+ emit_shrimm(temp,7,tl);
emit_readword((int)®_cop2d[10],temp);
emit_testimm(temp,0x8000);
emit_andimm(temp,0xf80,temp);
emit_andne_imm(temp,0,temp);
- emit_orrshr(temp,2,tl);
+ emit_orrshr_imm(temp,2,tl);
emit_readword((int)®_cop2d[11],temp);
emit_testimm(temp,0x8000);
emit_andimm(temp,0xf80,temp);
emit_andne_imm(temp,0,temp);
- emit_orrshl(temp,3,tl);
+ emit_orrshl_imm(temp,3,tl);
emit_writeword(tl,(int)®_cop2d[copr]);
break;
default:
break;
case 28:
emit_andimm(sl,0x001f,temp);
- emit_shl(temp,7,temp);
+ emit_shlimm(temp,7,temp);
emit_writeword(temp,(int)®_cop2d[9]);
emit_andimm(sl,0x03e0,temp);
- emit_shl(temp,2,temp);
+ emit_shlimm(temp,2,temp);
emit_writeword(temp,(int)®_cop2d[10]);
emit_andimm(sl,0x7c00,temp);
- emit_shr(temp,3,temp);
+ emit_shrimm(temp,3,temp);
emit_writeword(temp,(int)®_cop2d[11]);
emit_writeword(sl,(int)®_cop2d[28]);
break;