next_interupt, next_interupt - psxRegs.cycle);
}
-void MTC0_()
+// from interpreter
+extern void MTC0(int reg, u32 val);
+
+void pcsx_mtc0(u32 reg)
{
- extern void psxMTC0();
+ evprintf("MTC0 %d #%x @%08x %u\n", reg, readmem_word, psxRegs.pc, psxRegs.cycle);
+ MTC0(reg, readmem_word);
+ gen_interupt();
+}
- evprintf("ari64 MTC0 %08x %08x %u\n", psxRegs.code, psxRegs.pc, psxRegs.cycle);
- psxMTC0();
- gen_interupt(); /* FIXME: checking pending irqs should be enough */
+void pcsx_mtc0_ds(u32 reg)
+{
+ evprintf("MTC0 %d #%x @%08x %u\n", reg, readmem_word, psxRegs.pc, psxRegs.cycle);
+ MTC0(reg, readmem_word);
}
void new_dyna_save(void)
pending_exception = 1;
}
-static void ari64_execute()
+// execute until predefined leave points
+// (HLE softcall exit and BIOS fastboot end)
+static void ari64_execute_until()
{
schedule_timeslice();
psxRegs.cycle, next_interupt, next_interupt - psxRegs.cycle);
}
+static void ari64_execute()
+{
+ while (!stop) {
+ ari64_execute_until();
+ evprintf("drc left @%08x\n", psxRegs.pc);
+ }
+}
+
static void ari64_clear(u32 addr, u32 size)
{
u32 start, end;
+ size *= 4; /* PCSX uses DMA units */
+
evprintf("ari64_clear %08x %04x\n", addr, size);
/* check for RAM mirrors */
ari64_reset,
#if defined(__arm__)
ari64_execute,
- ari64_execute,
+ ari64_execute_until,
#else
intExecuteT,
intExecuteBlockT,