drc: don't cache psxRegs.interrupt

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / linkage_arm64.S

diff --git a/libpcsxcore/new_dynarec/linkage_arm64.S b/libpcsxcore/new_dynarec/linkage_arm64.S
index 6f32fa3..b9ab726 100644 (file)
--- a/libpcsxcore/new_dynarec/linkage_arm64.S
+++ b/libpcsxcore/new_dynarec/linkage_arm64.S
@@ -52,7 +52,7 @@ DRC_VAR(pending_exception, 4)
 DRC_VAR(stop, 4)
 DRC_VAR(branch_target, 4)
 DRC_VAR(address, 4)
-#DRC_VAR(align0, 16) /* unused/alignment */
+DRC_VAR(hack_addr, 4)
 DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
 
 /* psxRegs */
@@ -77,7 +77,7 @@ DRC_VAR(psxH_ptr, 8)
 DRC_VAR(invc_ptr, 8)
 DRC_VAR(zeromem_ptr, 8)
 DRC_VAR(scratch_buf_ptr, 8)
-#DRC_VAR(align1, 16) /* unused/alignment */
+DRC_VAR(ram_offset, 8)
 DRC_VAR(mini_ht, 256)
 DRC_VAR(restore_candidate, 512)
 
@@ -253,10 +253,10 @@ FUNCTION(new_dyna_leave):
 .endm
 
 .macro memhandler_post
-       ldr     w2, [rFP, #LO_next_interupt]
-       ldr     w1, [rFP, #LO_cycle]
-       sub     w0, w1, w2
-       str     w2, [rFP, #LO_last_count]
+       ldr     w0, [rFP, #LO_next_interupt]
+       ldr     w2, [rFP, #LO_cycle]        // memhandlers can modify cc, like dma
+       str     w0, [rFP, #LO_last_count]
+       sub     w0, w2, w0
 .endm
 
 FUNCTION(do_memhandler_pre):
@@ -336,7 +336,7 @@ handler_write_end:
 FUNCTION(jump_handle_swl):
        /* w0 = address, w1 = data, w2 = cycles */
        ldr     x3, [rFP, #LO_mem_wtab]
-       mov     w4, w0, lsr #12
+       orr     w4, wzr, w0, lsr #12
        ldr     x3, [x3, w4, uxtw #3]
        adds    x3, x3, x3
        bcs     4f
@@ -371,7 +371,7 @@ FUNCTION(jump_handle_swl):
 FUNCTION(jump_handle_swr):
        /* w0 = address, w1 = data, w2 = cycles */
        ldr     x3, [rFP, #LO_mem_wtab]
-       mov     w4, w0, lsr #12
+       orr     w4, wzr, w0, lsr #12
        ldr     x3, [x3, w4, uxtw #3]
        adds    x3, x3, x3
        bcs     4f