hsn[RHASH]=1;
hsn[RHTBL]=1;
}
+ // due to the way JAL(R) is currently done we need DS not to evict $ra
+ if(i>0&&(itype[i-1]==RJUMP||itype[i-1]!=UJUMP)&&rt1[i-1]!=0) {
+ hsn[rt1[i-1]]=0;
+ }
// Coprocessor load/store needs FTEMP, even if not declared
if(itype[i]==C1LS||itype[i]==C2LS) {
hsn[FTEMP]=0;
int offset;
int jaddr=0;
int memtarget=0,c=0;
+ int fastload_reg_override=0;
u_int hr,reglist=0;
th=get_reg(i_regs->regmap,rt1[i]|64);
tl=get_reg(i_regs->regmap,rt1[i]);
if(sp_in_mirror&&rs1[i]==29) {
emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
+ fastload_reg_override=HOST_TEMPREG;
}
else
#endif
#else
if(!c) a=addr;
#endif
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(fastload_reg_override) a=fastload_reg_override;
+
emit_movsbl_indexed_tlb(x,a,map,tl);
}
}
#else
if(!c) a=addr;
#endif
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(fastload_reg_override) a=fastload_reg_override;
//#ifdef
//emit_movswl_indexed_tlb(x,tl,map,tl);
//else
if(!c||memtarget) {
if(!dummy) {
int a=addr;
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(fastload_reg_override) a=fastload_reg_override;
//emit_readword_indexed((int)rdram-0x80000000,addr,tl);
#ifdef HOST_IMM_ADDR32
if(c)
#else
if(!c) a=addr;
#endif
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(fastload_reg_override) a=fastload_reg_override;
+
emit_movzbl_indexed_tlb(x,a,map,tl);
}
}
#else
if(!c) a=addr;
#endif
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(fastload_reg_override) a=fastload_reg_override;
//#ifdef
//emit_movzwl_indexed_tlb(x,tl,map,tl);
//#else
if(!c||memtarget) {
if(!dummy) {
int a=addr;
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(fastload_reg_override) a=fastload_reg_override;
//emit_readword_indexed((int)rdram-0x80000000,addr,tl);
#ifdef HOST_IMM_ADDR32
if(c)
if(!c||memtarget) {
if(!dummy) {
int a=addr;
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(fastload_reg_override) a=fastload_reg_override;
//gen_tlb_addr_r(tl,map);
//if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
//emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
int jaddr=0,jaddr2,type;
int memtarget=0,c=0;
int agr=AGEN1+(i&1);
+ int faststore_reg_override=0;
u_int hr,reglist=0;
th=get_reg(i_regs->regmap,rs2[i]|64);
tl=get_reg(i_regs->regmap,rs2[i]);
if(sp_in_mirror&&rs1[i]==29) {
emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
+ faststore_reg_override=HOST_TEMPREG;
}
else
#endif
#else
if(!c) a=addr;
#endif
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(faststore_reg_override) a=faststore_reg_override;
//gen_tlb_addr_w(temp,map);
//emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
emit_writebyte_indexed_tlb(tl,x,a,map,a);
#else
if(!c) a=addr;
#endif
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(faststore_reg_override) a=faststore_reg_override;
//#ifdef
//emit_writehword_indexed_tlb(tl,x,temp,map,temp);
//#else
if (opcode[i]==0x2B) { // SW
if(!c||memtarget) {
int a=addr;
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(faststore_reg_override) a=faststore_reg_override;
//emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
emit_writeword_indexed_tlb(tl,0,a,map,temp);
}
if (opcode[i]==0x3F) { // SD
if(!c||memtarget) {
int a=addr;
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(faststore_reg_override) a=faststore_reg_override;
if(rs2[i]) {
assert(th>=0);
//emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
//if(opcode[i]==0x2B)
/*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
{
- //emit_pusha();
+ #ifdef __i386__
+ emit_pusha();
+ #endif
+ #ifdef __arm__
save_regs(0x100f);
+ #endif
emit_readword((int)&last_count,ECX);
#ifdef __i386__
if(get_reg(i_regs->regmap,CCREG)<0)
emit_writeword(0,(int)&Count);
#endif
emit_call((int)memdebug);
- //emit_popa();
+ #ifdef __i386__
+ emit_popa();
+ #endif
+ #ifdef __arm__
restore_regs(0x100f);
+ #endif
}/**/
}
if(rh>=0) do_preload_rhash(rh);
}
#endif
- ds_assemble(i+1,i_regs);
- uint64_t bc_unneeded=branch_regs[i].u;
- uint64_t bc_unneeded_upper=branch_regs[i].uu;
- bc_unneeded|=1|(1LL<<rt1[i]);
- bc_unneeded_upper|=1|(1LL<<rt1[i]);
- bc_unneeded&=~(1LL<<rs1[i]);
- wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
- bc_unneeded,bc_unneeded_upper);
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
if(rt1[i]!=0) {
int rt,return_address;
assert(rt1[i+1]!=rt1[i]);
emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
#endif
}
+ ds_assemble(i+1,i_regs);
+ uint64_t bc_unneeded=branch_regs[i].u;
+ uint64_t bc_unneeded_upper=branch_regs[i].uu;
+ bc_unneeded|=1|(1LL<<rt1[i]);
+ bc_unneeded_upper|=1|(1LL<<rt1[i]);
+ bc_unneeded&=~(1LL<<rs1[i]);
+ wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
+ bc_unneeded,bc_unneeded_upper);
+ load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
cc=get_reg(branch_regs[i].regmap,CCREG);
assert(cc==HOST_CCREG);
#ifdef USE_MINI_HT
case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
+#ifndef FORCE32
case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
+#endif
case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
clear_const(¤t,rt1[i]);
alloc_cc(¤t,i);
dirty_reg(¤t,CCREG);
- ooo[i]=1;
- delayslot_alloc(¤t,i+1);
if (rt1[i]==31) {
alloc_reg(¤t,i,31);
dirty_reg(¤t,31);
#endif
//current.is32|=1LL<<rt1[i];
}
+ ooo[i]=1;
+ delayslot_alloc(¤t,i+1);
//current.isconst=0; // DEBUG
ds=1;
//printf("i=%d, isconst=%x\n",i,current.isconst);
#ifdef PCSX
if (start == 0x80030000) {
// nasty hack for fastbios thing
+ // override block entry to this code
instr_addr0_override=(u_int)out;
emit_movimm(start,0);
- emit_readword((int)&pcaddr,1);
+ // abuse io address var as a flag that we
+ // have already returned here once
+ emit_readword((int)&address,1);
emit_writeword(0,(int)&pcaddr);
+ emit_writeword(0,(int)&address);
emit_cmp(0,1);
emit_jne((int)new_dyna_leave);
}