if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
{
alloc_reg(current,i,rs1[i]);
- if (rt1[i]==31) {
- alloc_reg(current,i,31);
- dirty_reg(current,31);
+ if (rt1[i]!=0) {
+ alloc_reg(current,i,rt1[i]);
+ dirty_reg(current,rt1[i]);
}
}
if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
assert(ccreg==HOST_CCREG);
assert(!is_delayslot);
emit_movimm(start+i*4+4,0); // Get PC
- emit_movimm(source[i],1); // opcode
+ emit_movimm((int)psxHLEt[source[i]&7],1);
emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
- emit_jmp((int)jump_hlecall); // XXX
+ emit_jmp((int)jump_hlecall);
}
void ds_assemble(int i,struct regstat *i_regs)
wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
bc_unneeded,bc_unneeded_upper);
load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
- if(rt1[i]==31) {
+ if(rt1[i]!=0) {
int rt,return_address;
- assert(rt1[i+1]!=31);
- assert(rt2[i+1]!=31);
- rt=get_reg(branch_regs[i].regmap,31);
+ assert(rt1[i+1]!=rt1[i]);
+ assert(rt2[i+1]!=rt1[i]);
+ rt=get_reg(branch_regs[i].regmap,rt1[i]);
assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
assert(rt>=0);
return_address=start+i*4+8;
emit_mov(s1l,addr);
if(opcode2[i]==9) // JALR
{
- int rt=get_reg(i_regs->regmap,31);
+ int rt=get_reg(i_regs->regmap,rt1[i]);
emit_movimm(start+i*4+8,rt);
}
}
// Save it
unneeded_reg[i]=u;
unneeded_reg_upper[i]=uu;
-#ifdef FORCE32
- unneeded_reg_upper[i]=-1LL;
-#endif
/*
printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
printf("U:");
}
printf("\n");*/
}
+#ifdef FORCE32
+ for (i=iend;i>=istart;i--)
+ {
+ unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
+ }
+#endif
}
// Identify registers which are likely to contain 32-bit values
case FJUMP:
printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
case RJUMP:
- printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);break;
+ if (rt1[i]!=31)
+ printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
+ else
+ printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
+ break;
case SPAN:
printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
case IMM16:
#ifdef PCSX
if (Config.HLE && start == 0x80001000) {
// XXX: is this enough? Maybe check hleSoftCall?
+ u_int beginning=(u_int)out;
u_int page=get_page(start);
ll_add(jump_in+page,start,out);
invalid_code[start>>12]=0;
emit_movimm(start,0);
emit_writeword(0,(int)&pcaddr);
- emit_jmp((int)new_dyna_leave); // enough??
+ emit_jmp((int)new_dyna_leave);
+#ifdef __arm__
+ __clear_cache((void *)beginning,out);
+#endif
return 0;
}
else if ((u_int)addr < 0x00200000) {
rs2[i]=0;
rt1[i]=0;
rt2[i]=0;
- // The JALR instruction writes to r31.
+ // The JALR instruction writes to rd.
if (op2&1) {
- rt1[i]=31;
+ rt1[i]=(source[i]>>11)&0x1f;
}
rs2[i]=CCREG;
break;
else ba[i]=-1;
/* Is this the end of the block? */
if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
- if(rt1[i-1]!=31) { // Continue past subroutine call (JAL)
+ if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
done=1;
// Does the block continue due to a branch?
for(j=i-1;j>=0;j--)
dirty_reg(¤t,CCREG);
if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
alloc_reg(¤t,i,rs1[i]);
- if (rt1[i]==31) {
- alloc_reg(¤t,i,31);
- dirty_reg(¤t,31);
+ if (rt1[i]!=0) {
+ alloc_reg(¤t,i,rt1[i]);
+ dirty_reg(¤t,rt1[i]);
assert(rs1[i+1]!=31&&rs2[i+1]!=31);
#ifdef REG_PREFETCH
alloc_reg(¤t,i,PTEMP);
alloc_cc(&branch_regs[i-1],i-1);
dirty_reg(&branch_regs[i-1],CCREG);
alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
- if(rt1[i-1]==31) { // JALR
- alloc_reg(&branch_regs[i-1],i-1,31);
- dirty_reg(&branch_regs[i-1],31);
- branch_regs[i-1].is32|=1LL<<31;
+ if(rt1[i-1]!=0) { // JALR
+ alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
+ dirty_reg(&branch_regs[i-1],rt1[i-1]);
+ branch_regs[i-1].is32|=1LL<<rt1[i-1];
}
#ifdef USE_MINI_HT
if(rs1[i-1]==31) { // JALR