clear_const(current,dops[i].rs2);
alloc_cc(current,i); // for stalls
dirty_reg(current,CCREG);
- if(dops[i].rs1&&dops[i].rs2)
+ current->u &= ~(1ull << HIREG);
+ current->u &= ~(1ull << LOREG);
+ alloc_reg(current, i, HIREG);
+ alloc_reg(current, i, LOREG);
+ dirty_reg(current, HIREG);
+ dirty_reg(current, LOREG);
+ if ((dops[i].opcode2 & 0x3e) == 0x1a || (dops[i].rs1 && dops[i].rs2)) // div(u)
{
- current->u&=~(1LL<<HIREG);
- current->u&=~(1LL<<LOREG);
- alloc_reg(current,i,HIREG);
- alloc_reg(current,i,LOREG);
- alloc_reg(current,i,dops[i].rs1);
- alloc_reg(current,i,dops[i].rs2);
- dirty_reg(current,HIREG);
- dirty_reg(current,LOREG);
- }
- else
- {
- // Multiply by zero is zero.
- // MIPS does not have a divide by zero exception.
- alloc_reg(current,i,HIREG);
- alloc_reg(current,i,LOREG);
- dirty_reg(current,HIREG);
- dirty_reg(current,LOREG);
- if (dops[i].rs1 && ((dops[i].opcode2 & 0x3e) == 0x1a)) // div(u) 0
- alloc_reg(current, i, dops[i].rs1);
+ alloc_reg(current, i, dops[i].rs1);
+ alloc_reg(current, i, dops[i].rs2);
}
+ // else multiply by zero is zero
}
#endif
static void do_invstub(int n)
{
literal_pool(20);
- assem_debug("do_invstub\n");
+ assem_debug("do_invstub %x\n", start + stubs[n].e*4);
u_int reglist = stubs[n].a;
u_int addrr = stubs[n].b;
int ofs_start = stubs[n].c;
imm_min -= cinfo[i].imm;
imm_max -= cinfo[i].imm;
add_stub(INVCODE_STUB, jaddr, out, reglist|(1<<HOST_CCREG),
- addr, imm_min, imm_max, 0);
+ addr, imm_min, imm_max, i);
}
+// determines if code overwrite checking is needed only
+// (also true non-existent 0x20000000 mirror that shouldn't matter)
+#define is_ram_addr(a) !((a) & 0x5f800000)
+
static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
{
int s,tl;
int memtarget=0,c=0;
int offset_reg = -1;
int fastio_reg_override = -1;
+ u_int addr_const = ~0;
u_int reglist=get_host_reglist(i_regs->regmap);
tl=get_reg(i_regs->regmap,dops[i].rs2);
s=get_reg(i_regs->regmap,dops[i].rs1);
offset=cinfo[i].imm;
if(s>=0) {
c=(i_regs->wasconst>>s)&1;
- if(c) {
- memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
+ if (c) {
+ addr_const = constmap[i][s] + offset;
+ memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
}
}
assert(tl>=0);
assert(addr >= 0);
if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
+ reglist |= 1u << addr;
if (!c) {
jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
&offset_reg, &fastio_reg_override, ccadj_);
}
if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
host_tempreg_release();
- if(jaddr) {
+ if (jaddr) {
// PCSX store handlers don't check invcode again
- reglist|=1<<addr;
add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
- jaddr=0;
- }
- {
- if(!c||memtarget) {
- do_store_smc_check(i, i_regs, reglist, addr);
- }
- }
- u_int addr_val=constmap[i][s]+offset;
- if(jaddr) {
- add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
- } else if(c&&!memtarget) {
- inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
}
+ if (!c || is_ram_addr(addr_const))
+ do_store_smc_check(i, i_regs, reglist, addr);
+ if (c && !memtarget)
+ inline_writestub(type, i, addr_const, i_regs->regmap, dops[i].rs2, ccadj_, reglist);
// basic current block modification detection..
// not looking back as that should be in mips cache already
// (see Spyro2 title->attract mode)
- if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
- SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
+ if (start + i*4 < addr_const && addr_const < start + slen*4) {
+ SysPrintf("write to %08x hits block %08x, pc=%08x\n", addr_const, start, start+i*4);
assert(i_regs->regmap==regs[i].regmap); // not delay slot
if(i_regs->regmap==regs[i].regmap) {
load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
void *done0, *done1, *done2;
int memtarget=0,c=0;
int offset_reg = -1;
- u_int reglist=get_host_reglist(i_regs->regmap);
+ u_int addr_const = ~0;
+ u_int reglist = get_host_reglist(i_regs->regmap);
tl=get_reg(i_regs->regmap,dops[i].rs2);
s=get_reg(i_regs->regmap,dops[i].rs1);
offset=cinfo[i].imm;
if(s>=0) {
- c=(i_regs->isconst>>s)&1;
- if(c) {
- memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
+ c = (i_regs->isconst >> s) & 1;
+ if (c) {
+ addr_const = constmap[i][s] + offset;
+ memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
}
}
assert(tl>=0);
assert(addr >= 0);
+ reglist |= 1u << addr;
if(!c) {
emit_cmpimm(addr, RAM_SIZE);
jaddr=out;
if (dops[i].opcode == 0x2A) { // SWL
// Write two msb into two least significant bytes
if (dops[i].rs2) emit_rorimm(tl, 16, tl);
- do_store_hword(addr, -1, tl, offset_reg, 0);
+ do_store_hword(addr, -1, tl, offset_reg, 1);
if (dops[i].rs2) emit_rorimm(tl, 16, tl);
}
else if (dops[i].opcode == 0x2E) { // SWR
// Write 3 lsb into three most significant bytes
do_store_byte(addr, tl, offset_reg);
if (dops[i].rs2) emit_rorimm(tl, 8, tl);
- do_store_hword(addr, 1, tl, offset_reg, 0);
+ do_store_hword(addr, 1, tl, offset_reg, 1);
if (dops[i].rs2) emit_rorimm(tl, 24, tl);
}
done1=out;
// 3
set_jump_target(case3, out);
if (dops[i].opcode == 0x2A) { // SWL
- do_store_word(addr, -3, tl, offset_reg, 0);
+ do_store_word(addr, -3, tl, offset_reg, 1);
}
else if (dops[i].opcode == 0x2E) { // SWR
do_store_byte(addr, tl, offset_reg);
set_jump_target(done2, out);
if (offset_reg == HOST_TEMPREG)
host_tempreg_release();
- if(!c||!memtarget)
+ if (!c || !memtarget)
add_stub_r(STORELR_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
- do_store_smc_check(i, i_regs, reglist, addr);
+ if (!c || is_ram_addr(addr_const))
+ do_store_smc_check(i, i_regs, reglist, addr);
}
static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
enum stub_type type;
int offset_reg = -1;
int fastio_reg_override = -1;
+ u_int addr_const = ~0;
u_int reglist=get_host_reglist(i_regs->regmap);
u_int copr=(source[i]>>16)&0x1f;
s=get_reg(i_regs->regmap,dops[i].rs1);
if (dops[i].opcode==0x3a) { // SWC2
reglist |= 1<<ar;
}
- if(s>=0) c=(i_regs->wasconst>>s)&1;
- memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
+ if (s >= 0) {
+ c = (i_regs->isconst >> s) & 1;
+ if (c) {
+ addr_const = constmap[i][s] + offset;
+ memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
+ }
+ }
cop2_do_stall_check(0, i, i_regs, reglist);
host_tempreg_release();
if(jaddr2)
add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
- if(dops[i].opcode==0x3a) // SWC2
+ if (dops[i].opcode == 0x3a && (!c || is_ram_addr(addr_const))) // SWC2
do_store_smc_check(i, i_regs, reglist, ar);
- if (dops[i].opcode==0x32) { // LWC2
+ if (dops[i].opcode == 0x32) { // LWC2
host_tempreg_acquire();
cop2_put_dreg(copr,tl,HOST_TEMPREG);
host_tempreg_release();
cinfo[i].addr = rs;
add_offset = 0;
}
- else if (dops[i].itype == STORELR) { // overwrites addr
- assert(ra >= 0);
- assert(rs != ra);
- emit_mov(rs, ra);
- cinfo[i].addr = ra;
- }
else
cinfo[i].addr = rs;
if (add_offset) {
if(i==0||dops[i].bt)
regs[i].loadedconst=0;
else {
- for(hr=0;hr<HOST_REGS;hr++) {
- if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
- &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
+ for (hr = 0; hr < HOST_REGS; hr++) {
+ if (hr == EXCLUDE_REG || regmap[hr] < 0 || pre[hr] != regmap[hr])
+ continue;
+ if ((((regs[i-1].isconst & regs[i-1].loadedconst) >> hr) & 1)
+ && regmap[hr] == regs[i-1].regmap[hr])
{
- regs[i].loadedconst|=1<<hr;
+ regs[i].loadedconst |= 1u << hr;
}
}
}
emit_storereg(reg, 0);
}
}
+ if (dops[i].opcode == 0x0f) { // LUI
+ emit_movimm(cinfo[i].imm << 16, 0);
+ emit_storereg(dops[i].rt1, 0);
+ }
emit_movimm(start+i*4,0);
emit_writeword(0,&pcaddr);
int cc = get_reg(regs[i].regmap_entry, CCREG);
restore_regs(reglist);
assem_debug("\\\\do_insn_cmp\n");
}
+static void drc_dbg_emit_wb_dirtys(int i, const struct regstat *i_regs)
+{
+ // write-out non-consts, consts are likely different because of get_final_value()
+ if (i_regs->dirty & ~i_regs->loadedconst) {
+ assem_debug("/ drc_dbg_wb\n");
+ wb_dirtys(i_regs->regmap, i_regs->dirty & ~i_regs->loadedconst);
+ assem_debug("\\ drc_dbg_wb\n");
+ }
+}
#else
#define drc_dbg_emit_do_cmp(x,y)
+#define drc_dbg_emit_wb_dirtys(x,y)
#endif
// Used when a branch jumps into the delay slot of another branch
load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
ds_assemble(i+1,&branch_regs[i]);
+ drc_dbg_emit_wb_dirtys(i+1, &branch_regs[i]);
cc=get_reg(branch_regs[i].regmap,CCREG);
if(cc==-1) {
emit_loadreg(CCREG,cc=HOST_CCREG);
*limit = (addr & 0xa0600000) + 0x00200000;
return (u_int *)(psxM + (addr & 0x1fffff));
}
- else if (!Config.HLE && (
+ else if (
/* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
- (0xbfc00000 <= addr && addr < 0xbfc80000)))
+ (0xbfc00000 <= addr && addr < 0xbfc80000))
{
// BIOS. The multiplier should be much higher as it's uncached 8bit mem,
// but timings in PCSX are too tied to the interpreter's 2-per-insn assumption
done = 1;
}
if (dops[i].itype == HLECALL)
- stop = 1;
+ done = 1;
else if (dops[i].itype == INTCALL)
- stop = 2;
+ done = 2;
else if (dops[i].is_exception)
done = stop_after_jal ? 1 : 2;
if (done == 2) {
regs[i+2].wasdirty&=~(1<<hr);
}
assert(hr>=0);
+ #if 0 // what is this for? double allocs $0 in ps1_rom.bin
if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
{
regs[i].regmap[hr]=dops[i+1].rs1;
regs[i+1].wasdirty&=~(1<<hr);
regs[i].dirty&=~(1<<hr);
}
+ #endif
}
}
if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) { // LWC2
new_dynarec_did_compile=1;
if (Config.HLE && start == 0x80001000) // hlecall
{
- // XXX: is this enough? Maybe check hleSoftCall?
void *beginning = start_block();
emit_movimm(start,0);
ds = assemble(i, ®s[i], cinfo[i].ccadj);
+ drc_dbg_emit_wb_dirtys(i, ®s[i]);
if (dops[i].is_ujump)
literal_pool(1024);
else