//assert(adj==0);
emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
+#ifdef PCSX
+ if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
+ // special case for RFE
+ emit_jmp(0);
+ else
+#endif
emit_jns(0);
//load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
#ifdef USE_MINI_HT
rs2[i]=0;
rt1[i]=0;
rt2[i]=0;
- gte_rt[i]=1ll<<63; // every op changes flags
- // TODO: other regs?
+ gte_rs[i]=gte_reg_reads[source[i]&0x3f];
+ gte_rt[i]=gte_reg_writes[source[i]&0x3f];
+ gte_rt[i]|=1ll<<63; // every op changes flags
break;
case FLOAT:
case FCONV:
cc=0;
}
#ifdef PCSX
+ else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2)
+ {
+ // GTE runs in parallel until accessed, divide by 2 for a rough guess
+ cc+=gte_cycletab[source[i]&0x3f]/2;
+ }
else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
{
cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)