setup spu r8 handlers

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / pcsxmem.c

diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c
index 87aa17c..fc19494 100644 (file)
--- a/libpcsxcore/new_dynarec/pcsxmem.c
+++ b/libpcsxcore/new_dynarec/pcsxmem.c
@@ -101,7 +101,11 @@ static void io_write_sio32(u32 value)
 
 static void map_rcnt_rcount0(u32 mode)
 {
-       if (mode & 0x100) { // pixel clock
+       if (mode & 0x001) { // sync mode
+               map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1);
+               map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1);
+       }
+       else if (mode & 0x100) { // pixel clock
                map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
                map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
        }
@@ -113,7 +117,11 @@ static void map_rcnt_rcount0(u32 mode)
 
 static void map_rcnt_rcount1(u32 mode)
 {
-       if (mode & 0x100) { // hcnt
+       if (mode & 0x001) { // sync mode
+               map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1);
+               map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1);
+       }
+       else if (mode & 0x100) { // hcnt
                map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
                map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
        }
@@ -125,7 +133,7 @@ static void map_rcnt_rcount1(u32 mode)
 
 static void map_rcnt_rcount2(u32 mode)
 {
-       if (mode & 0x01) { // gate
+       if ((mode & 7) == 1 || (mode & 7) == 7) { // sync mode
                map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
                map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
        }
@@ -146,7 +154,6 @@ static void map_rcnt_rcount2(u32 mode)
 #endif
 
 #define make_rcnt_funcs(i) \
-static u32 io_rcnt_read_count##i()  { return psxRcntRcount(i); } \
 static u32 io_rcnt_read_mode##i()   { return psxRcntRmode(i); } \
 static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
 static void io_rcnt_write_count##i(u32 val)  { psxRcntWcount(i, val & 0xffff); } \
@@ -173,6 +180,29 @@ make_dma_func(3)
 make_dma_func(4)
 make_dma_func(6)
 
+static u32 io_spu_read8_even(u32 addr)
+{
+       return SPU_readRegister(addr, psxRegs.cycle) & 0xff;
+}
+
+static u32 io_spu_read8_odd(u32 addr)
+{
+       return SPU_readRegister(addr, psxRegs.cycle) >> 8;
+}
+
+static u32 io_spu_read16(u32 addr)
+{
+       return SPU_readRegister(addr, psxRegs.cycle);
+}
+
+static u32 io_spu_read32(u32 addr)
+{
+       u32 ret;
+       ret  = SPU_readRegister(addr, psxRegs.cycle);
+       ret |= SPU_readRegister(addr + 2, psxRegs.cycle) << 16;
+       return ret;
+}
+
 static void io_spu_write16(u32 value)
 {
        // meh
@@ -237,9 +267,6 @@ static u32 read_biu(u32 addr)
        if (addr != 0xfffe0130)
                return read_mem_dummy(addr);
 
- FILE *f = fopen("/tmp/psxbiu.bin", "wb");
- fwrite(psxM, 1, 0x200000, f);
- fclose(f);
        memprintf("read_biu  %08x @%08x %u\n",
                psxRegs.biuReg, psxRegs.pc, psxRegs.cycle);
        return psxRegs.biuReg;
@@ -348,14 +375,13 @@ void new_dyna_pcsx_mem_init(void)
        }
 
        map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
-       map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
-       map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1);
+       map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1);
        map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
        map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
-       map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1);
+       map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1);
        map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
        map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
-       map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1);
+       map_item(&mem_iortab[IOMEM32(0x1120)], psxRcntRcount2, 1);
        map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
        map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
 //     map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
@@ -368,13 +394,13 @@ void new_dyna_pcsx_mem_init(void)
        map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
        map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
        map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
-       map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1);
+       map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1);
        map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
        map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
-       map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1);
+       map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1);
        map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
        map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
-       map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1);
+       map_item(&mem_iortab[IOMEM16(0x1120)], psxRcntRcount2, 1);
        map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
        map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);
 
@@ -384,6 +410,13 @@ void new_dyna_pcsx_mem_init(void)
        map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
        map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
 
+       for (i = 0x1c00; i < 0x2000; i += 2) {
+               map_item(&mem_iortab[IOMEM8(i)], io_spu_read8_even, 1);
+               map_item(&mem_iortab[IOMEM8(i+1)], io_spu_read8_odd, 1);
+               map_item(&mem_iortab[IOMEM16(i)], io_spu_read16, 1);
+               map_item(&mem_iortab[IOMEM32(i)], io_spu_read32, 1);
+       }
+
        // write(u32 data)
        map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
        map_item(&mem_iowtab[IOMEM32(0x1070)], psxHwWriteIstat, 1);
@@ -453,14 +486,8 @@ void new_dyna_pcsx_mem_init(void)
 
 void new_dyna_pcsx_mem_reset(void)
 {
-       int i;
-
        // plugins might change so update the pointers
        map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
-
-       for (i = 0x1c00; i < 0x2000; i += 2)
-               map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);
-
        map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
 }