unbreak some old savestates

[pcsx_rearmed.git] / libpcsxcore / psxdma.c

diff --git a/libpcsxcore/psxdma.c b/libpcsxcore/psxdma.c
index 42fb3ba..0ffec81 100644 (file)
--- a/libpcsxcore/psxdma.c
+++ b/libpcsxcore/psxdma.c
@@ -64,6 +64,9 @@ void psxDma4(u32 madr, u32 bcr, u32 chcr) { // SPU
                                break;
                        SPU_writeDMAMem(ptr, words_copy * 2, psxRegs.cycle);
                        HW_DMA4_MADR = SWAPu32(madr + words_copy * 2);
+                       // This should be much slower, like 12+ cycles/byte, it's like
+                       // that because the CPU runs too fast and fifo is not emulated.
+                       // See also set_dma_end().
                        SPUDMA_INT(words * 4);
                        return;
 
@@ -153,6 +156,8 @@ void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
 
                        HW_DMA2_MADR = SWAPu32(madr + words_copy * 4);
 
+                       // careful: gpu_state_change() also messes with this
+                       HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
                        // already 32-bit word size ((size * 4) / 4)
                        GPUDMA_INT(words / 4);
                        return;
@@ -174,6 +179,8 @@ void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
 
                        HW_DMA2_MADR = SWAPu32(madr);
 
+                       // careful: gpu_state_change() also messes with this
+                       HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
                        // already 32-bit word size ((size * 4) / 4)
                        GPUDMA_INT(words / 4);
                        return;
@@ -211,6 +218,8 @@ void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
        DMA_INTERRUPT(2);
 }
 
+// note: this is also (ab)used for non-dma prim command
+// to delay gpu returning to idle state, see gpu_state_change()
 void gpuInterrupt() {
        if (HW_DMA2_CHCR == SWAP32(0x01000401) && !(HW_DMA2_MADR & SWAP32(0x800000)))
        {