void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
u32 *ptr, madr_next, *madr_next_p;
u32 words, words_left, words_max, words_copy;
- int cycles_sum, cycles_last_cmd = 0, do_walking;
+ s32 cycles_last_cmd = 0;
+ int do_walking;
+ long cycles_sum;
madr &= ~3;
switch (chcr) {
psxRegs.gpuIdleAfter = psxRegs.cycle + cycles_sum + cycles_last_cmd;
set_event(PSXINT_GPUDMA, cycles_sum);
- //printf("%u dma2cf: %d,%d %08x\n", psxRegs.cycle, cycles_sum,
- // cycles_last_cmd, HW_DMA2_MADR);
+ //printf("%u dma2cf: %6d,%4d %08x %08x %08x %08x\n", psxRegs.cycle,
+ // cycles_sum, cycles_last_cmd, madr, bcr, chcr, HW_DMA2_MADR);
return;
default:
if (HW_DMA2_CHCR == SWAP32(0x01000401) && !(HW_DMA2_MADR & SWAP32(0x800000)))
{
u32 madr_next = 0xffffff, madr = SWAPu32(HW_DMA2_MADR);
- int cycles_sum, cycles_last_cmd = 0;
+ s32 cycles_last_cmd = 0;
+ long cycles_sum;
+
cycles_sum = GPU_dmaChain((u32 *)psxM, madr & 0x1fffff,
&madr_next, &cycles_last_cmd);
HW_DMA2_MADR = SWAPu32(madr_next);
cycles_sum += psxRegs.gpuIdleAfter - psxRegs.cycle;
psxRegs.gpuIdleAfter = psxRegs.cycle + cycles_sum + cycles_last_cmd;
set_event(PSXINT_GPUDMA, cycles_sum);
- //printf("%u dma2cn: %d,%d %08x\n", psxRegs.cycle, cycles_sum,
+ //printf("%u dma2cn: %6d,%4d %08x\n", psxRegs.cycle, cycles_sum,
// cycles_last_cmd, HW_DMA2_MADR);
return;
}
}
}
+void psxAbortDma2() {
+ psxRegs.gpuIdleAfter = psxRegs.cycle + 32;
+}
+
void psxDma6(u32 madr, u32 bcr, u32 chcr) {
u32 words, words_max;
u32 *mem;