*/
#include "psxhw.h"
+#include "psxevents.h"
#include "mdec.h"
#include "cdrom.h"
#include "gpu.h"
//#undef PSXHW_LOG
//#define PSXHW_LOG printf
+#ifndef PAD_LOG
+#define PAD_LOG(...)
+#endif
-void psxHwReset() {
- if (Config.Sio) psxHu32ref(0x1070) |= SWAP32(0x80);
- if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAP32(0x200);
+static u32 (*psxHwReadGpuSRptr)(void) = psxHwReadGpuSR;
+void psxHwReset() {
memset(psxH, 0, 0x10000);
mdecInit(); // initialize mdec decoder
cdrReset();
psxRcntInit();
- HW_GPU_STATUS = 0x14802000;
+ HW_GPU_STATUS = SWAP32(0x14802000);
+ psxHwReadGpuSRptr = Config.hacks.gpu_busy_hack
+ ? psxHwReadGpuSRbusyHack : psxHwReadGpuSR;
+}
+
+void psxHwWriteIstat(u32 value)
+{
+ u32 stat = psxHu16(0x1070) & value;
+ psxHu16ref(0x1070) = SWAPu16(stat);
+
+ psxRegs.CP0.n.Cause &= ~0x400;
+ if (stat & psxHu16(0x1074))
+ psxRegs.CP0.n.Cause |= 0x400;
+}
+
+void psxHwWriteImask(u32 value)
+{
+ u32 stat = psxHu16(0x1070);
+ psxHu16ref(0x1074) = SWAPu16(value);
+ if (stat & value) {
+ //if ((psxRegs.CP0.n.SR & 0x401) == 0x401)
+ // log_unhandled("irq on unmask @%08x\n", psxRegs.pc);
+ set_event(PSXINT_NEWDRC_CHECK, 1);
+ }
+ psxRegs.CP0.n.Cause &= ~0x400;
+ if (stat & value)
+ psxRegs.CP0.n.Cause |= 0x400;
+}
+
+void psxHwWriteDmaIcr32(u32 value)
+{
+ u32 tmp = value & 0x00ff803f;
+ tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
+ if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
+ || tmp & HW_DMA_ICR_BUS_ERROR) {
+ if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
+ psxHu32ref(0x1070) |= SWAP32(8);
+ tmp |= HW_DMA_ICR_IRQ_SENT;
+ }
+ HW_DMA_ICR = SWAPu32(tmp);
+}
+
+void psxHwWriteGpuSR(u32 value)
+{
+ GPU_writeStatus(value);
+ gpuSyncPluginSR();
+}
+
+u32 psxHwReadGpuSR(void)
+{
+ u32 v;
+
+ // meh2, syncing for img bit, might want to avoid it..
+ gpuSyncPluginSR();
+ v = SWAP32(HW_GPU_STATUS);
+
+ // XXX: because of large timeslices can't use hSyncCount, using rough
+ // approximization instead. Perhaps better use hcounter code here or something.
+ if (hSyncCount < 240 && (v & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
+ v |= PSXGPU_LCF & (psxRegs.cycle << 20);
+ return v;
+}
+
+// a hack due to poor timing of gpu idle bit
+// to get rid of this, GPU draw times, DMAs, cpu timing has to fall within
+// certain timing window or else games like "ToHeart" softlock
+u32 psxHwReadGpuSRbusyHack(void)
+{
+ u32 v = psxHwReadGpuSR();
+ static u32 hack;
+ if (!(hack++ & 3))
+ v &= ~PSXGPU_nBUSY;
+ return v;
}
u8 psxHwRead8(u32 add) {
unsigned char hard;
- switch (add) {
- case 0x1f801040: hard = sioRead8();break; \r
-#ifdef ENABLE_SIO1API
- case 0x1f801050: hard = SIO1_readData8(); break;\r
-#endif
+ switch (add & 0x1fffffff) {
+ case 0x1f801040: hard = sioRead8(); break;
case 0x1f801800: hard = cdrRead0(); break;
case 0x1f801801: hard = cdrRead1(); break;
case 0x1f801802: hard = cdrRead2(); break;
case 0x1f801803: hard = cdrRead3(); break;
+
+ case 0x1f801041: case 0x1f801042: case 0x1f801043:
+ case 0x1f801044: case 0x1f801045:
+ case 0x1f801046: case 0x1f801047:
+ case 0x1f801048: case 0x1f801049:
+ case 0x1f80104a: case 0x1f80104b:
+ case 0x1f80104c: case 0x1f80104d:
+ case 0x1f80104e: case 0x1f80104f:
+ case 0x1f801050: case 0x1f801051:
+ case 0x1f801054: case 0x1f801055:
+ case 0x1f801058: case 0x1f801059:
+ case 0x1f80105a: case 0x1f80105b:
+ case 0x1f80105c: case 0x1f80105d:
+ case 0x1f801100: case 0x1f801101:
+ case 0x1f801104: case 0x1f801105:
+ case 0x1f801108: case 0x1f801109:
+ case 0x1f801110: case 0x1f801111:
+ case 0x1f801114: case 0x1f801115:
+ case 0x1f801118: case 0x1f801119:
+ case 0x1f801120: case 0x1f801121:
+ case 0x1f801124: case 0x1f801125:
+ case 0x1f801128: case 0x1f801129:
+ case 0x1f801810: case 0x1f801811:
+ case 0x1f801812: case 0x1f801813:
+ case 0x1f801814: case 0x1f801815:
+ case 0x1f801816: case 0x1f801817:
+ case 0x1f801820: case 0x1f801821:
+ case 0x1f801822: case 0x1f801823:
+ case 0x1f801824: case 0x1f801825:
+ case 0x1f801826: case 0x1f801827:
+ log_unhandled("unhandled r8 %08x @%08x\n", add, psxRegs.pc);
+ // falthrough
default:
+ if (0x1f801c00 <= add && add < 0x1f802000) {
+ u16 val = SPU_readRegister(add & ~1, psxRegs.cycle);
+ hard = (add & 1) ? val >> 8 : val;
+ break;
+ }
hard = psxHu8(add);
#ifdef PSXHW_LOG
PSXHW_LOG("*Unkwnown 8bit read at address %x\n", add);
u16 psxHwRead16(u32 add) {
unsigned short hard;
- switch (add) {
+ switch (add & 0x1fffffff) {
#ifdef PSXHW_LOG
case 0x1f801070: PSXHW_LOG("IREG 16bit read %x\n", psxHu16(0x1070));
return psxHu16(0x1070);
-#endif
-#ifdef PSXHW_LOG
case 0x1f801074: PSXHW_LOG("IMASK 16bit read %x\n", psxHu16(0x1074));
return psxHu16(0x1074);
#endif
-
case 0x1f801040:
hard = sioRead8();
hard|= sioRead8() << 8;
-#ifdef PAD_LOG
PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
-#endif
return hard;
case 0x1f801044:
hard = sioReadStat16();
-#ifdef PAD_LOG
PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
-#endif
return hard;
case 0x1f801048:
hard = sioReadMode16();
-#ifdef PAD_LOG
PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
-#endif
return hard;
case 0x1f80104a:
hard = sioReadCtrl16();
-#ifdef PAD_LOG
PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
-#endif
return hard;
case 0x1f80104e:
hard = sioReadBaud16();
-#ifdef PAD_LOG
PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
-#endif
- return hard;\r
-#ifdef ENABLE_SIO1API
- case 0x1f801050:
- hard = SIO1_readData16();
return hard;
+
+ /* Fixes Armored Core misdetecting the Link cable being detected.
+ * We want to turn that thing off and force it to do local multiplayer instead.
+ * Thanks Sony for the fix, they fixed it in their PS Classic fork.
+ */
case 0x1f801054:
- hard = SIO1_readStat16();
- return hard;
- case 0x1f80105a:
- hard = SIO1_readCtrl16();
- return hard;
- case 0x1f80105e:
- hard = SIO1_readBaud16();
- return hard;\r
-#endif
+ return 0x80;\r
+
case 0x1f801100:
- hard = psxRcntRcount(0);
+ hard = psxRcntRcount0();
#ifdef PSXHW_LOG
PSXHW_LOG("T0 count read16: %x\n", hard);
#endif
#endif
return hard;
case 0x1f801110:
- hard = psxRcntRcount(1);
+ hard = psxRcntRcount1();
#ifdef PSXHW_LOG
PSXHW_LOG("T1 count read16: %x\n", hard);
#endif
#endif
return hard;
case 0x1f801120:
- hard = psxRcntRcount(2);
+ hard = psxRcntRcount2();
#ifdef PSXHW_LOG
PSXHW_LOG("T2 count read16: %x\n", hard);
#endif
//case 0x1f802030: hard = //int_2000????
//case 0x1f802040: hard =//dip switches...??
+ case 0x1f801042:
+ case 0x1f801046:
+ case 0x1f80104c:
+ case 0x1f801050:
+ case 0x1f801058:
+ case 0x1f80105a:
+ case 0x1f80105c:
+ case 0x1f801800:
+ case 0x1f801802:
+ case 0x1f801810:
+ case 0x1f801812:
+ case 0x1f801814:
+ case 0x1f801816:
+ case 0x1f801820:
+ case 0x1f801822:
+ case 0x1f801824:
+ case 0x1f801826:
+ log_unhandled("unhandled r16 %08x @%08x\n", add, psxRegs.pc);
+ // falthrough
default:
- if (add >= 0x1f801c00 && add < 0x1f801e00) {
- hard = SPU_readRegister(add);
- } else {
- hard = psxHu16(add);
+ if (0x1f801c00 <= add && add < 0x1f802000)
+ return SPU_readRegister(add, psxRegs.cycle);
+ hard = psxHu16(add);
#ifdef PSXHW_LOG
- PSXHW_LOG("*Unkwnown 16bit read at address %x\n", add);
+ PSXHW_LOG("*Unkwnown 16bit read at address %x\n", add);
#endif
- }
- return hard;
+ return hard;
}
#ifdef PSXHW_LOG
u32 psxHwRead32(u32 add) {
u32 hard;
- switch (add) {
+ switch (add & 0x1fffffff) {
case 0x1f801040:
hard = sioRead8();
hard |= sioRead8() << 8;
hard |= sioRead8() << 16;
hard |= sioRead8() << 24;
-#ifdef PAD_LOG
PAD_LOG("sio read32 ;ret = %x\n", hard);
-#endif
- return hard;\r
-#ifdef ENABLE_SIO1API
- case 0x1f801050:
- hard = SIO1_readData32();
- return hard;\r
-#endif
+ return hard;
+ case 0x1f801044:
+ hard = sioReadStat16();
+ PAD_LOG("sio read32 %x; ret = %x\n", add&0xf, hard);
+ return hard;
#ifdef PSXHW_LOG
case 0x1f801060:
PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060));
return psxHu32(0x1060);
-#endif
-#ifdef PSXHW_LOG
case 0x1f801070: PSXHW_LOG("IREG 32bit read %x\n", psxHu32(0x1070));
return psxHu32(0x1070);
-#endif
-#ifdef PSXHW_LOG
case 0x1f801074: PSXHW_LOG("IMASK 32bit read %x\n", psxHu32(0x1074));
return psxHu32(0x1074);
#endif
#endif
return hard;
case 0x1f801814:
- gpuSyncPluginSR();
- hard = HW_GPU_STATUS;
- if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
- hard |= PSXGPU_LCF & (psxRegs.cycle << 20);
+ hard = psxHwReadGpuSRptr();
#ifdef PSXHW_LOG
PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
#endif
// time for rootcounters :)
case 0x1f801100:
- hard = psxRcntRcount(0);
+ hard = psxRcntRcount0();
#ifdef PSXHW_LOG
PSXHW_LOG("T0 count read32: %x\n", hard);
#endif
#endif
return hard;
case 0x1f801110:
- hard = psxRcntRcount(1);
+ hard = psxRcntRcount1();
#ifdef PSXHW_LOG
PSXHW_LOG("T1 count read32: %x\n", hard);
#endif
#endif
return hard;
case 0x1f801120:
- hard = psxRcntRcount(2);
+ hard = psxRcntRcount2();
#ifdef PSXHW_LOG
PSXHW_LOG("T2 count read32: %x\n", hard);
#endif
#endif
return hard;
+ case 0x1f801048:
+ case 0x1f80104c:
+ case 0x1f801050:
+ case 0x1f801054:
+ case 0x1f801058:
+ case 0x1f80105c:
+ case 0x1f801800:
+ log_unhandled("unhandled r32 %08x @%08x\n", add, psxRegs.pc);
+ // falthrough
default:
- hard = psxHu32(add);
+ if (0x1f801c00 <= add && add < 0x1f802000) {
+ hard = SPU_readRegister(add, psxRegs.cycle);
+ hard |= SPU_readRegister(add + 2, psxRegs.cycle) << 16;
+ return hard;
+ }
+ hard = psxHu32(add);
#ifdef PSXHW_LOG
PSXHW_LOG("*Unkwnown 32bit read at address %x\n", add);
#endif
}
void psxHwWrite8(u32 add, u8 value) {
- switch (add) {
+ switch (add & 0x1fffffff) {
case 0x1f801040: sioWrite8(value); break;\r
-#ifdef ENABLE_SIO1API
- case 0x1f801050: SIO1_writeData8(value); break;\r
-#endif
case 0x1f801800: cdrWrite0(value); break;
case 0x1f801801: cdrWrite1(value); break;
case 0x1f801802: cdrWrite2(value); break;
case 0x1f801803: cdrWrite3(value); break;
+ case 0x1f801041: case 0x1f801042: case 0x1f801043:
+ case 0x1f801044: case 0x1f801045:
+ case 0x1f801046: case 0x1f801047:
+ case 0x1f801048: case 0x1f801049:
+ case 0x1f80104a: case 0x1f80104b:
+ case 0x1f80104c: case 0x1f80104d:
+ case 0x1f80104e: case 0x1f80104f:
+ case 0x1f801050: case 0x1f801051:
+ case 0x1f801054: case 0x1f801055:
+ case 0x1f801058: case 0x1f801059:
+ case 0x1f80105a: case 0x1f80105b:
+ case 0x1f80105c: case 0x1f80105d:
+ case 0x1f801100: case 0x1f801101:
+ case 0x1f801104: case 0x1f801105:
+ case 0x1f801108: case 0x1f801109:
+ case 0x1f801110: case 0x1f801111:
+ case 0x1f801114: case 0x1f801115:
+ case 0x1f801118: case 0x1f801119:
+ case 0x1f801120: case 0x1f801121:
+ case 0x1f801124: case 0x1f801125:
+ case 0x1f801128: case 0x1f801129:
+ case 0x1f801810: case 0x1f801811:
+ case 0x1f801812: case 0x1f801813:
+ case 0x1f801814: case 0x1f801815:
+ case 0x1f801816: case 0x1f801817:
+ case 0x1f801820: case 0x1f801821:
+ case 0x1f801822: case 0x1f801823:
+ case 0x1f801824: case 0x1f801825:
+ case 0x1f801826: case 0x1f801827:
+ log_unhandled("unhandled w8 %08x @%08x\n", add, psxRegs.pc);
+ // falthrough
default:
+ if (0x1f801c00 <= add && add < 0x1f802000) {
+ log_unhandled("spu w8 %02x @%08x\n", value, psxRegs.pc);
+ if (!(add & 1))
+ SPU_writeRegister(add, value, psxRegs.cycle);
+ return;
+ }
+
psxHu8(add) = value;
#ifdef PSXHW_LOG
PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
}
void psxHwWrite16(u32 add, u16 value) {
- switch (add) {
+ switch (add & 0x1fffffff) {
case 0x1f801040:
sioWrite8((unsigned char)value);
sioWrite8((unsigned char)(value>>8));
-#ifdef PAD_LOG
PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
-#endif
return;
case 0x1f801044:
sioWriteStat16(value);
-#ifdef PAD_LOG
PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
-#endif
return;
case 0x1f801048:
- sioWriteMode16(value);
-#ifdef PAD_LOG
+ sioWriteMode16(value);
PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
-#endif
return;
case 0x1f80104a: // control register
sioWriteCtrl16(value);
-#ifdef PAD_LOG
PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
-#endif
return;
case 0x1f80104e: // baudrate register
- sioWriteBaud16(value);
-#ifdef PAD_LOG
+ sioWriteBaud16(value);
PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
-#endif
- return;\r
-#ifdef ENABLE_SIO1API
- case 0x1f801050:
- SIO1_writeData16(value);
- return;
- case 0x1f801054:
- SIO1_writeStat16(value);
- return;
- case 0x1f80105a:
- SIO1_writeCtrl16(value);
return;
- case 0x1f80105e:
- SIO1_writeBaud16(value);
- return;\r
-#endif
case 0x1f801070:
#ifdef PSXHW_LOG
PSXHW_LOG("IREG 16bit write %x\n", value);
#endif
- if (Config.Sio) psxHu16ref(0x1070) |= SWAPu16(0x80);
- if (Config.SpuIrq) psxHu16ref(0x1070) |= SWAPu16(0x200);
- psxHu16ref(0x1070) &= SWAPu16((psxHu16(0x1074) & value));
+ psxHwWriteIstat(value);
return;
case 0x1f801074:
#ifdef PSXHW_LOG
PSXHW_LOG("IMASK 16bit write %x\n", value);
#endif
- psxHu16ref(0x1074) = SWAPu16(value);
- if (psxHu16ref(0x1070) & value)
- new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
+ psxHwWriteImask(value);
return;
case 0x1f801100:
#endif
psxRcntWtarget(2, value); return;
+ case 0x1f801042:
+ case 0x1f801046:
+ case 0x1f80104c:
+ case 0x1f801050:
+ case 0x1f801054:
+ case 0x1f801058:
+ case 0x1f80105a:
+ case 0x1f80105c:
+ case 0x1f801800:
+ case 0x1f801802:
+ case 0x1f801810:
+ case 0x1f801812:
+ case 0x1f801814:
+ case 0x1f801816:
+ case 0x1f801820:
+ case 0x1f801822:
+ case 0x1f801824:
+ case 0x1f801826:
+ log_unhandled("unhandled w16 %08x @%08x\n", add, psxRegs.pc);
+ // falthrough
default:
- if (add>=0x1f801c00 && add<0x1f801e00) {
- SPU_writeRegister(add, value);
+ if (0x1f801c00 <= add && add < 0x1f802000) {
+ SPU_writeRegister(add, value, psxRegs.cycle);
return;
}
}
#define DmaExec(n) { \
+ if (value & SWAPu32(HW_DMA##n##_CHCR) & 0x01000000) \
+ log_unhandled("dma" #n " %08x -> %08x\n", HW_DMA##n##_CHCR, value); \
HW_DMA##n##_CHCR = SWAPu32(value); \
\
if (SWAPu32(HW_DMA##n##_CHCR) & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8 << (n * 4))) { \
}
void psxHwWrite32(u32 add, u32 value) {
- switch (add) {
+ switch (add & 0x1fffffff) {
case 0x1f801040:
sioWrite8((unsigned char)value);
sioWrite8((unsigned char)((value&0xff) >> 8));
sioWrite8((unsigned char)((value&0xff) >> 16));
sioWrite8((unsigned char)((value&0xff) >> 24));
-#ifdef PAD_LOG
PAD_LOG("sio write32 %x\n", value);
-#endif
- return;\r
-#ifdef ENABLE_SIO1API
- case 0x1f801050:
- SIO1_writeData32(value);
- return;\r
-#endif
+ return;
#ifdef PSXHW_LOG
case 0x1f801060:
PSXHW_LOG("RAM size write %x\n", value);
#ifdef PSXHW_LOG
PSXHW_LOG("IREG 32bit write %x\n", value);
#endif
- if (Config.Sio) psxHu32ref(0x1070) |= SWAPu32(0x80);
- if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAPu32(0x200);
- psxHu32ref(0x1070) &= SWAPu32((psxHu32(0x1074) & value));
+ psxHwWriteIstat(value);
return;
case 0x1f801074:
#ifdef PSXHW_LOG
PSXHW_LOG("IMASK 32bit write %x\n", value);
#endif
- psxHu32ref(0x1074) = SWAPu32(value);
- if (psxHu32ref(0x1070) & value)
- new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
+ psxHwWriteImask(value);
return;
#ifdef PSXHW_LOG
#ifdef PSXHW_LOG
PSXHW_LOG("DMA ICR 32bit write %x\n", value);
#endif
- {
- u32 tmp = value & 0x00ff803f;
- tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
- if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
- || tmp & HW_DMA_ICR_BUS_ERROR) {
- if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
- psxHu32ref(0x1070) |= SWAP32(8);
- tmp |= HW_DMA_ICR_IRQ_SENT;
- }
- HW_DMA_ICR = SWAPu32(tmp);
+ psxHwWriteDmaIcr32(value);
return;
- }
case 0x1f801810:
#ifdef PSXHW_LOG
#ifdef PSXHW_LOG
PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
#endif
- GPU_writeStatus(value);
- gpuSyncPluginSR();
+ psxHwWriteGpuSR(value);
return;
case 0x1f801820:
#endif
psxRcntWtarget(2, value & 0xffff); return;
+ case 0x1f801044:
+ case 0x1f801048:
+ case 0x1f80104c:
+ case 0x1f801050:
+ case 0x1f801054:
+ case 0x1f801058:
+ case 0x1f80105c:
+ case 0x1f801800:
+ log_unhandled("unhandled w32 %08x @%08x\n", add, psxRegs.pc);
+ // falthrough
default:
// Dukes of Hazard 2 - car engine noise
- if (add>=0x1f801c00 && add<0x1f801e00) {
- SPU_writeRegister(add, value&0xffff);
- SPU_writeRegister(add + 2, value>>16);
+ if (0x1f801c00 <= add && add < 0x1f802000) {
+ SPU_writeRegister(add, value&0xffff, psxRegs.cycle);
+ SPU_writeRegister(add + 2, value>>16, psxRegs.cycle);
return;
}