static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
{
if (sh2->pending_irl > sh2->pending_int_irq) {
- elprintf(EL_32X, "%csh2 ack/irl %d @ %08x",
- sh2->is_slave ? 's' : 'm', level, sh2->pc);
+ elprintf_sh2(sh2, EL_32X, "ack/irl %d @ %08x",
+ level, sh2_pc(sh2));
return 64 + sh2->pending_irl / 2;
} else {
- elprintf(EL_32X, "%csh2 ack/int %d/%d @ %08x",
- sh2->is_slave ? 's' : 'm', level, sh2->pending_int_vector, sh2->pc);
+ elprintf_sh2(sh2, EL_32X, "ack/int %d/%d @ %08x",
+ level, sh2->pending_int_vector, sh2_pc(sh2));
sh2->pending_int_irq = 0; // auto-clear
sh2->pending_level = sh2->pending_irl;
return sh2->pending_int_vector;
}
}
-// if !nested_call, must sync CPUs before calling this
-void p32x_update_irls(SH2 *active_sh2)
+// MUST specify active_sh2 when called from sh2 memhandlers
+void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
{
int irqs, mlvl = 0, slvl = 0;
- int m68k_cycles = 0;
int mrun, srun;
if (active_sh2 != NULL)
slvl++;
slvl *= 2;
- mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 != NULL);
- if (mrun)
+ mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 == &msh2);
+ if (mrun) {
p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles);
+ if (active_sh2 == &msh2)
+ sh2_end_run(active_sh2, 1);
+ }
- srun = sh2_irl_irq(&ssh2, slvl, active_sh2 != NULL);
- if (srun)
+ srun = sh2_irl_irq(&ssh2, slvl, active_sh2 == &ssh2);
+ if (srun) {
p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles);
+ if (active_sh2 == &ssh2)
+ sh2_end_run(active_sh2, 1);
+ }
elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
}
// TODO: OOM handling
PicoAHW |= PAHW_32X;
- sh2_init(&msh2, 0);
+ sh2_init(&msh2, 0, &ssh2);
msh2.irq_callback = sh2_irq_cb;
- sh2_init(&ssh2, 1);
+ sh2_init(&ssh2, 1, &msh2);
ssh2.irq_callback = sh2_irq_cb;
PicoMemSetup32x();
if (!Pico.m.pal)
Pico32x.vdp_regs[0] |= P32XV_nPAL;
- PREG8(Pico32xMem->sh2_peri_regs[0], 4) =
- PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR
-
rendstatus_old = -1;
emu_32x_startup();
sh2_reset(&msh2);
sh2_reset(&ssh2);
+ sh2_peripheral_reset(&msh2);
+ sh2_peripheral_reset(&ssh2);
// if we don't have BIOS set, perform it's work here.
// MSH2
memset(&Pico32x, 0, sizeof(Pico32x));
Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified
- Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN;
+ Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_PEN;
Pico32x.sh2_regs[0] = P32XS2_ADEN;
}
void PicoReset32x(void)
{
if (PicoAHW & PAHW_32X) {
+ msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT();
Pico32x.sh2irqs |= P32XI_VRES;
- p32x_update_irls(NULL);
+ p32x_update_irls(NULL, SekCyclesDoneT2());
p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
p32x_pwm_ctl_changed();
}
Pico32x.sh2irqs |= P32XI_VINT;
- p32x_update_irls(NULL);
+ p32x_update_irls(NULL, SekCyclesDoneT2());
p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
}
+void p32x_schedule_hint(SH2 *sh2, int m68k_cycles)
+{
+ // rather rough, 32x hint is useless in practice
+ int after;
+
+ if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 4))
+ return; // nobody cares
+ // note: when Pico.m.scanline is 224, SH2s might
+ // still be at scanline 93 (or so)
+ if (!(Pico32x.sh2_regs[0] & 0x80) && Pico.m.scanline > 224)
+ return;
+
+ after = (Pico32x.sh2_regs[4 / 2] + 1) * 488;
+ if (sh2 != NULL)
+ p32x_event_schedule_sh2(sh2, P32X_EVENT_HINT, after);
+ else
+ p32x_event_schedule(m68k_cycles, P32X_EVENT_HINT, after);
+}
+
// compare cycles, handling overflows
// check if a > b
#define CYCLES_GT(a, b) \
p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, now);
}
+static void hint_event(unsigned int now)
+{
+ Pico32x.sh2irqs |= P32XI_HINT;
+ p32x_update_irls(NULL, now);
+ p32x_schedule_hint(NULL, now);
+}
+
typedef void (event_cb)(unsigned int now);
unsigned int event_times[P32X_EVENT_COUNT];
static event_cb *event_cbs[] = {
[P32X_EVENT_PWM] = p32x_pwm_irq_event,
[P32X_EVENT_FILLEND] = fillend_event,
+ [P32X_EVENT_HINT] = hint_event,
};
// schedule event at some time 'after', in m68k clocks
p32x_event_schedule(now, event, after);
left_to_next = (event_time_next - now) * 3;
- if (sh2_cycles_left(sh2) > left_to_next)
- sh2_end_run(sh2, left_to_next);
+ sh2_end_run(sh2, left_to_next);
}
static void run_events(unsigned int until)
pevt_log_sh2_o(sh2, EVT_RUN_START);
sh2->state |= SH2_STATE_RUN;
cycles = C_M68K_TO_SH2(*sh2, m68k_cycles);
- elprintf(EL_32X, "%csh2 +run %u %d",
- sh2->is_slave?'s':'m', sh2->m68krcycles_done, cycles);
+ elprintf_sh2(sh2, EL_32X, "+run %u %d @%08x",
+ sh2->m68krcycles_done, cycles, sh2->pc);
done = sh2_execute(sh2, cycles);
sh2->m68krcycles_done += C_SH2_TO_M68K(*sh2, done);
sh2->state &= ~SH2_STATE_RUN;
pevt_log_sh2_o(sh2, EVT_RUN_END);
- elprintf(EL_32X, "%csh2 -run %u %d",
- sh2->is_slave?'s':'m', sh2->m68krcycles_done, done);
+ elprintf_sh2(sh2, EL_32X, "-run %u %d",
+ sh2->m68krcycles_done, done);
}
// sync other sh2 to this one
// note: recursive call
void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
{
- SH2 *osh2 = &sh2s[sh2->is_slave ^ 1];
+ SH2 *osh2 = sh2->other_sh2;
int left_to_event;
int m68k_cycles;
return;
}
- elprintf(EL_32X, "%csh2 sync to %u %d",
- osh2->is_slave?'s':'m', m68k_target, m68k_cycles);
+ elprintf_sh2(osh2, EL_32X, "sync to %u %d",
+ m68k_target, m68k_cycles);
run_sh2(osh2, m68k_cycles);
void PicoFrame32x(void)
{
+ Pico.m.scanline = 0;
+
Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank
if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking
Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
+ if (!(Pico32x.sh2_regs[0] & 0x80))
+ p32x_schedule_hint(NULL, SekCyclesDoneT2());
p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
SekCycleCnt = 0;
sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCycleCntT;
- p32x_update_irls(NULL);
+ p32x_update_irls(NULL, SekCycleCntT);
p32x_pwm_state_loaded();
run_events(SekCycleCntT);
}
notaz.gp2x.de / picodrive.git / blobdiff