/*
- * SH2 addr lines:
- * iii. .cc. ..xx * // Internal, Cs, x
+ * PicoDrive
+ * (C) notaz, 2009,2010,2013
+ *
+ * This work is licensed under the terms of MAME license.
+ * See COPYING file in the top-level directory.
*
* Register map:
* a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
* a1511e ? ? 401e
* a15120 (16 bytes comm) 2020
* a15130 (PWM) 2030
+ *
+ * SH2 addr lines:
+ * iii. .cc. ..xx * // Internal, Cs, x
+ *
+ * sh2 map, wait/bus cycles (from docs):
+ * r w
+ * rom 0000000-0003fff 1 -
+ * sys reg 0004000-00040ff 1 1
+ * vdp reg 0004100-00041ff 5 5
+ * vdp pal 0004200-00043ff 5 5
+ * rom 2000000-23fffff 6-15
+ * dram/fb 4000000-401ffff 5-12 1-3
+ * fb ovr 4020000-403ffff
+ * sdram 6000000-603ffff 12 2 (cycles)
+ * d.a. c0000000-?
*/
#include "../pico_int.h"
#include "../memory.h"
-#ifdef DRC_SH2
#include "../../cpu/sh2/compiler.h"
-#endif
#if 0
#undef ash2_end_run
// SH2 faking
//#define FAKE_SH2
-int p32x_csum_faked;
#ifdef FAKE_SH2
+static int p32x_csum_faked;
static const u16 comm_fakevals[] = {
0x4d5f, 0x4f4b, // M_OK
0x535f, 0x4f4b, // S_OK
{
a &= 0x3e;
- if (a == 2) // INTM, INTS
- return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
#if 0
if ((a & 0x30) == 0x20)
return sh2_comm_faker(a);
#else
if ((a & 0x30) == 0x20) {
- // evil X-Men proto polls in a dbra loop and expects it to expire..
static u32 dr2 = 0;
+ unsigned int cycles = SekCyclesDoneT();
+ int comreg = 1 << (a & 0x0f) / 2;
+
+ // evil X-Men proto polls in a dbra loop and expects it to expire..
if (SekDar(2) != dr2)
m68k_poll.cnt = 0;
dr2 = SekDar(2);
- if (p32x_poll_detect(&m68k_poll, a, SekCyclesDoneT(), 0)) {
+ if (cycles - msh2.m68krcycles_done > 500)
+ p32x_sync_sh2s(cycles);
+ if (Pico32x.comm_dirty_sh2 & comreg)
+ Pico32x.comm_dirty_sh2 &= ~comreg;
+ else if (p32x_poll_detect(&m68k_poll, a, cycles, 0)) {
SekSetStop(1);
SekEndTimeslice(16);
}
dr2 = SekDar(2);
+ goto out;
}
#endif
+ if (a == 2) { // INTM, INTS
+ unsigned int cycles = SekCyclesDoneT();
+ if (cycles - msh2.m68krcycles_done > 64)
+ p32x_sync_sh2s(cycles);
+ return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
+ }
+
if ((a & 0x30) == 0x30)
return p32x_pwm_read16(a);
+out:
return Pico32x.regs[a / 2];
}
return;
case 3: // irq ctl
if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
+ p32x_sync_sh2s(SekCyclesDoneT());
Pico32x.sh2irqi[0] |= P32XI_CMD;
p32x_update_irls(0);
- SekEndRun(16);
}
if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
+ p32x_sync_sh2s(SekCyclesDoneT());
Pico32x.sh2irqi[1] |= P32XI_CMD;
p32x_update_irls(0);
- SekEndRun(16);
}
return;
case 5: // bank
if ((a & 0x30) == 0x20) {
u8 *r8 = (u8 *)r;
+ int cycles = SekCyclesDoneT();
+ int comreg;
+
+ if (r8[a ^ 1] == d)
+ return;
+
+ comreg = 1 << (a & 0x0f) / 2;
+ if (Pico32x.comm_dirty_68k & comreg)
+ p32x_sync_sh2s(cycles);
+
r8[a ^ 1] = d;
p32x_poll_undetect(&sh2_poll[0], 0);
p32x_poll_undetect(&sh2_poll[1], 0);
- // if some SH2 is busy waiting, it needs to see the result ASAP
- if (SekCyclesLeftNoMCD > 32)
- SekEndRun(32);
+ Pico32x.comm_dirty_68k |= comreg;
+
+ if (cycles - (int)msh2.m68krcycles_done > 120)
+ p32x_sync_sh2s(cycles);
return;
}
}
return;
}
// comm port
- else if ((a & 0x30) == 0x20 && r[a / 2] != d) {
+ else if ((a & 0x30) == 0x20) {
+ int cycles = SekCyclesDoneT();
+ int comreg;
+
+ if (r[a / 2] == d)
+ return;
+
+ comreg = 1 << (a & 0x0f) / 2;
+ if (Pico32x.comm_dirty_68k & comreg)
+ p32x_sync_sh2s(cycles);
+
r[a / 2] = d;
p32x_poll_undetect(&sh2_poll[0], 0);
p32x_poll_undetect(&sh2_poll[1], 0);
- // same as for w8
- if (SekCyclesLeftNoMCD > 32)
- SekEndRun(32);
+ Pico32x.comm_dirty_68k |= comreg;
+
+ if (cycles - (int)msh2.m68krcycles_done > 120)
+ p32x_sync_sh2s(cycles);
return;
}
// PWM
}
}
-static void p32x_vdp_write16(u32 a, u32 d)
+static void p32x_vdp_write16(u32 a, u32 d, u32 cycles)
{
a &= 0x0e;
if (a == 6) { // fill start
if (a == 8) { // fill data
u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
int len = Pico32x.vdp_regs[4 / 2] + 1;
+ int len1 = len;
a = Pico32x.vdp_regs[6 / 2];
- while (len--) {
+ while (len1--) {
dram[a] = d;
a = (a & 0xff00) | ((a + 1) & 0xff);
}
- Pico32x.vdp_regs[6 / 2] = a;
- Pico32x.vdp_regs[8 / 2] = d;
+ Pico32x.vdp_regs[0x06 / 2] = a;
+ Pico32x.vdp_regs[0x08 / 2] = d;
+ if (cycles > 0) {
+ Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
+ p32x_event_schedule(P32X_EVENT_FILLEND, cycles, len);
+ }
return;
}
case 0x00: // adapter/irq ctl
return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
case 0x04: // H count (often as comm too)
- if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
- ash2_end_run(8);
+ if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(&sh2s[cpuid]), 0))
+ ash2_end_run(&sh2s[cpuid], 8);
return Pico32x.sh2_regs[4 / 2];
case 0x10: // DREQ len
return r[a / 2];
return r[a / 2];
// comm port
if ((a & 0x30) == 0x20) {
- if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
- ash2_end_run(8);
+ int comreg = 1 << (a & 0x0f) / 2;
+ if (Pico32x.comm_dirty_68k & comreg)
+ Pico32x.comm_dirty_68k &= ~comreg;
+ else if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(&sh2s[cpuid]), 0))
+ ash2_end_run(&sh2s[cpuid], 8);
return r[a / 2];
}
if ((a & 0x30) == 0x30) {
Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
Pico32x.sh2_regs[0] &= ~0x80;
Pico32x.sh2_regs[0] |= d & 0x80;
+ if (d & 1)
+ p32x_pwm_schedule(sh2s[cpuid].m68krcycles_done); // XXX: timing?
p32x_update_irls(1);
return;
case 5: // H count
if ((a & 0x30) == 0x20) {
u8 *r8 = (u8 *)Pico32x.regs;
+ int comreg;
+ if (r8[a ^ 1] == d)
+ return;
+
r8[a ^ 1] = d;
if (p32x_poll_undetect(&m68k_poll, 0))
SekSetStop(0);
p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
+ comreg = 1 << (a & 0x0f) / 2;
+ Pico32x.comm_dirty_sh2 |= comreg;
return;
}
}
a &= 0xfe;
// comm
- if ((a & 0x30) == 0x20 && Pico32x.regs[a/2] != d) {
+ if ((a & 0x30) == 0x20) {
+ int comreg;
+ if (Pico32x.regs[a / 2] == d)
+ return;
+
Pico32x.regs[a / 2] = d;
if (p32x_poll_undetect(&m68k_poll, 0))
SekSetStop(0);
p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
+ comreg = 1 << (a & 0x0f) / 2;
+ Pico32x.comm_dirty_sh2 |= comreg;
return;
}
// PWM
case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
case 0x1c:
Pico32x.sh2irqs &= ~P32XI_PWM;
- p32x_timers_do(0);
+ if (!(Pico32x.emu_flags & P32XF_PWM_PEND))
+ p32x_pwm_schedule(sh2s[cpuid].m68krcycles_done); // timing?
goto irls;
}
dmac0->tcr0 &= 0xffffff;
// HACK: assume 68k starts writing soon and end the timeslice
- ash2_end_run(16);
+ ash2_end_run(&sh2s[id], 16);
// DREQ is only sent after first 4 words are written.
// we do multiple of 4 words to avoid messing up alignment
}
if ((a & 0xfff0) == 0x5180) { // a15180
- p32x_vdp_write16(a, d);
+ p32x_vdp_write16(a, d, 0); // FIXME?
return;
}
#ifdef EMU_F68K
// setup FAME fetchmap
for (rs = 0x90; rs < 0xa0; rs++)
- PicoCpuFM68k.Fetch[rs] = (u32)Pico.rom + bank - 0x900000;
+ PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom + bank - 0x900000;
#endif
}
if ((a & 0x3ff00) == 0x4100) {
d = p32x_vdp_read16(a);
- if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
- ash2_end_run(8);
+ if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(&sh2s[id]), 1))
+ ash2_end_run(&sh2s[id], 8);
goto out_16to8;
}
if ((a & 0x3ff00) == 0x4100) {
d = p32x_vdp_read16(a);
- if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
- ash2_end_run(8);
+ if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(&sh2s[id]), 1))
+ ash2_end_run(&sh2s[id], 8);
goto out;
}
if ((a & 0x3ff00) == 0x4100) {
sh2_poll[id].cnt = 0; // for poll before VDP accesses
- p32x_vdp_write16(a, d);
+ p32x_vdp_write16(a, d, sh2s[id].m68krcycles_done);
return 0;
}
}
-typedef struct {
- uptr addr; // stores (membase >> 1) or ((handler >> 1) | (1<<31))
- u32 mask;
-} sh2_memmap;
-
typedef u32 (sh2_read_handler)(u32 a, int id);
typedef int REGPARM(3) (sh2_write_handler)(u32 a, u32 d, int id);
cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
#ifdef EMU_F68K
// setup FAME fetchmap
- PicoCpuFM68k.Fetch[0] = (u32)Pico32xMem->m68k_rom;
+ PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom;
for (rs = 0x88; rs < 0x90; rs++)
- PicoCpuFM68k.Fetch[rs] = (u32)Pico.rom - 0x880000;
+ PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000;
#endif
// 32X ROM (banked)
sh2_poll[1].flag = P32XF_SSH2POLL;
sh2_poll[1].cyc_max = 16;
-#ifdef DRC_SH2
sh2_drc_mem_setup(&msh2);
sh2_drc_mem_setup(&ssh2);
-#endif
}
-void Pico32xStateLoaded(void)
+void Pico32xMemStateLoaded(void)
{
bank_switch(Pico32x.regs[4 / 2]);
Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
- p32x_poll_event(3, 0);
- Pico32x.dirty_pal = 1;
memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
-#ifdef DRC_SH2
+ Pico32x.dirty_pal = 1;
+
sh2_drc_flush_all();
-#endif
}
-// vim:shiftwidth=2:expandtab
+// vim:shiftwidth=2:ts=2:expandtab
notaz.gp2x.de / picodrive.git / blobdiff