unsigned short *dest;\r
unsigned char *src;\r
\r
- if (Pico_mcd->cdc.DBC.N <= (CDC_DMA_SPEED * 2))\r
+ if (1) //Pico_mcd->cdc.DBC.N <= (CDC_DMA_SPEED * 2))\r
{\r
length = (Pico_mcd->cdc.DBC.N + 1) >> 1;\r
Pico_mcd->scd.Status_CDC &= ~0x08; // Last transfer\r
{\r
Pico_mcd->cdc.IFSTAT &= ~0x40;\r
\r
- if (Pico_mcd->s68k_regs[0x33] & (1<<5))\r
+ if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN5)\r
{\r
elprintf(EL_INTS, "cdc DTE irq 5");\r
SekInterruptS68k(5);\r
cdprintf("************** Starting Data Transfer ***********");\r
cdprintf("RS0 = %.4X DAC = %.4X DBC = %.4X DMA adr = %.4X\n\n", Pico_mcd->s68k_regs[4]<<8,\r
Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N, (Pico_mcd->s68k_regs[0xA]<<8) | Pico_mcd->s68k_regs[0xB]);\r
+\r
+ // tmp\r
+ {\r
+ int ddx = Pico_mcd->s68k_regs[4] & 7;\r
+ if (ddx < 2) break; // invalid\r
+ if (ddx < 4) {\r
+ Pico_mcd->s68k_regs[4] |= 0x40; // Data set ready in host port\r
+ break;\r
+ }\r
+ if (ddx == 6) break; // invalid\r
+\r
+ pcd_event_schedule_s68k(PCD_EVENT_DMA, Pico_mcd->cdc.DBC.N / 2);\r
+ }\r
}\r
break;\r
\r
\r
Pico_mcd->s68k_regs[0x37] &= 3; // CDD.Control\r
\r
- if (Pico_mcd->s68k_regs[0x33] & (1<<4))\r
+ if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN4)\r
{\r
elprintf(EL_INTS, "cdd export irq 4");\r
SekInterruptS68k(4);\r