Pico_mcd->m.state_flags = PCD_ST_S68K_RST;
Pico_mcd->m.busreq = 2; // busreq on, s68k in reset
Pico_mcd->s68k_regs[3] = 1; // 2M word RAM mode, m68k access
- Pico_mcd->s68k_regs[6] = 0xff;
- Pico_mcd->s68k_regs[7] = 0xff;
memset(Pico_mcd->bios + 0x70, 0xff, 4);
}
if ((cyc_do = SekCycleAimS68k - SekCycleCntS68k) <= 0)
return;
+ if (SekShouldInterrupt())
+ Pico_mcd->m.s68k_poll_a = 0;
+
SekCycleCntS68k += cyc_do;
#if defined(EMU_C68K)
PicoCpuCS68k.cycles = cyc_do;
Pico_mcd->s68k_regs[0x31] * 384);
}
-static void pcd_gfx_event(unsigned int now)
-{
- // update gfx chip
- if (Pico_mcd->rot_comp.Reg_58 & 0x8000) {
- Pico_mcd->rot_comp.Reg_58 &= 0x7fff;
- Pico_mcd->rot_comp.Reg_64 = 0;
- if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN1) {
- elprintf(EL_INTS |EL_CD, "s68k: gfx_cd irq 1");
- SekInterruptS68k(1);
- }
- }
-}
-
static void pcd_dma_event(unsigned int now)
{
int ddx = Pico_mcd->s68k_regs[4] & 7;
static event_cb *pcd_event_cbs[PCD_EVENT_COUNT] = {
[PCD_EVENT_CDC] = pcd_cdc_event,
[PCD_EVENT_TIMER3] = pcd_int3_timer_event,
- [PCD_EVENT_GFX] = pcd_gfx_event,
+ [PCD_EVENT_GFX] = gfx_cd_update,
[PCD_EVENT_DMA] = pcd_dma_event,
};
static void SekSyncM68k(void);
-static inline void pcd_run_cpus_normal(int m68k_cycles)
+void pcd_run_cpus_normal(int m68k_cycles)
{
SekCycleAim += m68k_cycles;
- if (Pico_mcd->m.m68k_poll_cnt >= 16 && !SekShouldInterrupt()) {
+ if (SekShouldInterrupt() || Pico_mcd->m.m68k_poll_cnt < 12)
+ Pico_mcd->m.m68k_poll_cnt = 0;
+ else if (Pico_mcd->m.m68k_poll_cnt >= 16) {
int s68k_left = pcd_sync_s68k(SekCycleAim, 1);
if (s68k_left <= 0) {
elprintf(EL_CDPOLL, "m68k poll [%02x] x%d @%06x",
SekSyncM68k();
}
-static inline void pcd_run_cpus_lockstep(int m68k_cycles)
+void pcd_run_cpus_lockstep(int m68k_cycles)
{
unsigned int target = SekCycleAim + m68k_cycles;
do {
SekSyncM68k();
pcd_sync_s68k(SekCycleAim, 0);
} while (CYCLES_GT(target, SekCycleAim));
+
+ SekCycleAim = target;
}
#define PICO_CD