PICO_INTERNAL void PicoInitMCD(void)
{
SekInitS68k();
- Init_CD_Driver();
- gfx_init();
}
PICO_INTERNAL void PicoExitMCD(void)
{
- End_CD_Driver();
}
PICO_INTERNAL void PicoPowerMCD(void)
{
+ int fmt_size;
SekCycleCntS68k = SekCycleAimS68k = 0;
- int fmt_size = sizeof(formatted_bram);
+ fmt_size = sizeof(formatted_bram);
memset(Pico_mcd->prg_ram, 0, sizeof(Pico_mcd->prg_ram));
memset(Pico_mcd->word_ram2M, 0, sizeof(Pico_mcd->word_ram2M));
memset(Pico_mcd->pcm_ram, 0, sizeof(Pico_mcd->pcm_ram));
memset(&Pico_mcd->pcm, 0, sizeof(Pico_mcd->pcm));
memset(&Pico_mcd->m, 0, sizeof(Pico_mcd->m));
- Reset_CD();
+ cdc_init();
+ gfx_init();
// cold reset state (tested)
Pico_mcd->m.state_flags = PCD_ST_S68K_RST;
void pcd_soft_reset(void)
{
- // Reset_CD(); // breaks Fahrenheit CD swap
+ elprintf(EL_CD, "cd: soft reset");
- LC89510_Reset();
+ Pico_mcd->m.s68k_pend_ints = 0;
+ cdc_reset();
+ cdd_reset();
#ifdef _ASM_CD_MEMORY_C
//PicoMemResetCDdecode(1); // don't have to call this in 2M mode
#endif
+ memset(&Pico_mcd->s68k_regs[0x38], 0, 9);
+ Pico_mcd->s68k_regs[0x38+9] = 0x0f; // default checksum
+
pcd_event_schedule_s68k(PCD_EVENT_CDC, 12500000/75);
// TODO: test if register state/timers change
return 0;
}
-static __inline void SekRunS68k(unsigned int to)
+static void SekRunM68kOnce(void)
+{
+ int cyc_do;
+ pevt_log_m68k_o(EVT_RUN_START);
+
+ if ((cyc_do = SekCycleAim - SekCycleCnt) > 0) {
+ SekCycleCnt += cyc_do;
+
+#if defined(EMU_C68K)
+ PicoCpuCM68k.cycles = cyc_do;
+ CycloneRun(&PicoCpuCM68k);
+ SekCycleCnt -= PicoCpuCM68k.cycles;
+#elif defined(EMU_M68K)
+ SekCycleCnt += m68k_execute(cyc_do) - cyc_do;
+#elif defined(EMU_F68K)
+ SekCycleCnt += fm68k_emulate(cyc_do, 0) - cyc_do;
+#endif
+ }
+
+ SekCyclesLeft = 0;
+
+ SekTrace(0);
+ pevt_log_m68k_o(EVT_RUN_END);
+}
+
+static void SekRunS68k(unsigned int to)
{
int cyc_do;
static void pcd_cdc_event(unsigned int now)
{
// 75Hz CDC update
- Check_CD_Command();
+ cdd_update();
+
+ /* check if a new CDD command has been processed */
+ if (!(Pico_mcd->s68k_regs[0x4b] & 0xf0))
+ {
+ /* reset CDD command wait flag */
+ Pico_mcd->s68k_regs[0x4b] = 0xf0;
+
+ if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN4) {
+ elprintf(EL_INTS|EL_CD, "s68k: cdd irq 4");
+ SekInterruptS68k(4);
+ }
+ }
+
pcd_event_schedule(now, PCD_EVENT_CDC, 12500000/75);
}
static void pcd_dma_event(unsigned int now)
{
- int ddx = Pico_mcd->s68k_regs[4] & 7;
- Update_CDC_TRansfer(ddx);
+ cdc_dma_update();
}
typedef void (event_cb)(unsigned int now);
unsigned int pcd_event_times[PCD_EVENT_COUNT];
static unsigned int event_time_next;
static event_cb *pcd_event_cbs[PCD_EVENT_COUNT] = {
- [PCD_EVENT_CDC] = pcd_cdc_event,
- [PCD_EVENT_TIMER3] = pcd_int3_timer_event,
- [PCD_EVENT_GFX] = gfx_update,
- [PCD_EVENT_DMA] = pcd_dma_event,
+ pcd_cdc_event,
+ pcd_int3_timer_event,
+ gfx_update,
+ pcd_dma_event,
};
void pcd_event_schedule(unsigned int now, enum pcd_event event, int after)
SekCycleCnt = SekCycleAim - (s68k_left * 40220 >> 16);
}
- SekSyncM68k();
+ while (CYCLES_GT(SekCycleAim, SekCycleCnt)) {
+ SekRunM68kOnce();
+ if (Pico_mcd->m.need_sync) {
+ Pico_mcd->m.need_sync = 0;
+ pcd_sync_s68k(SekCycleCnt, 0);
+ }
+ }
}
void pcd_run_cpus_lockstep(int m68k_cycles)
if (Pico_mcd->s68k_regs[0x31])
pcd_event_schedule(SekCycleAimS68k, PCD_EVENT_TIMER3,
Pico_mcd->s68k_regs[0x31] * 384);
-
- if (Pico_mcd->scd.Status_CDC & 0x08)
- Update_CDC_TRansfer(Pico_mcd->s68k_regs[4] & 7);
}
diff = cycles - Pico_mcd->pcm.update_cycles;