\r
// main68k map (BIOS mapped by PicoMemSetup()):\r
// RAM cart\r
- if (PicoOpt & POPT_EN_MCD_RAMCART) {\r
+ if (PicoIn.opt & POPT_EN_MCD_RAMCART) {\r
cpu68k_map_set(m68k_read8_map, 0x400000, 0x7fffff, PicoReadM68k8_ramc, 1);\r
cpu68k_map_set(m68k_read16_map, 0x400000, 0x7fffff, PicoReadM68k16_ramc, 1);\r
cpu68k_map_set(m68k_write8_map, 0x400000, 0x7fffff, PicoWriteM68k8_ramc, 1);\r
\r
// setup FAME fetchmap\r
{\r
+#ifdef __clang__\r
+ volatile // prevent strange relocs from clang\r
+#endif\r
+ unsigned long ptr_ram = (uptr)PicoMem.ram;\r
int i;\r
+\r
// M68k\r
// by default, point everything to fitst 64k of ROM (BIOS)\r
for (i = 0; i < M68K_FETCHBANK1; i++)\r
- PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.rom - (i<<(24-FAMEC_FETCHBITS));\r
+ PicoCpuFM68k.Fetch[i] = (uptr)Pico.rom - (i<<(24-FAMEC_FETCHBITS));\r
// now real ROM (BIOS)\r
for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)\r
- PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.rom;\r
+ PicoCpuFM68k.Fetch[i] = (uptr)Pico.rom;\r
// .. and RAM\r
for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++)\r
- PicoCpuFM68k.Fetch[i] = (unsigned long)PicoMem.ram - (i<<(24-FAMEC_FETCHBITS));\r
+ PicoCpuFM68k.Fetch[i] = ptr_ram - (i<<(24-FAMEC_FETCHBITS));\r
// S68k\r
// PRG RAM is default\r
for (i = 0; i < M68K_FETCHBANK1; i++)\r
- PicoCpuFS68k.Fetch[i] = (unsigned long)Pico_mcd->prg_ram - (i<<(24-FAMEC_FETCHBITS));\r
+ PicoCpuFS68k.Fetch[i] = (uptr)Pico_mcd->prg_ram - (i<<(24-FAMEC_FETCHBITS));\r
// real PRG RAM\r
for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < 0x80000; i++)\r
- PicoCpuFS68k.Fetch[i] = (unsigned long)Pico_mcd->prg_ram;\r
+ PicoCpuFS68k.Fetch[i] = (uptr)Pico_mcd->prg_ram;\r
// WORD RAM 2M area\r
for (i = M68K_FETCHBANK1*0x08/0x100; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < 0xc0000; i++)\r
- PicoCpuFS68k.Fetch[i] = (unsigned long)Pico_mcd->word_ram2M - 0x80000;\r
+ PicoCpuFS68k.Fetch[i] = (uptr)Pico_mcd->word_ram2M - 0x80000;\r
// remap_word_ram() will setup word ram for both\r
}\r
#endif\r