sprintf(dstrp, "mode set 4: %02x\n", (r=reg[0xC])); MVP;
sprintf(dstrp, "interlace: %i%i, cells: %i, shadow: %i\n", bit(r,2), bit(r,1), (r&0x80) ? 40 : 32, bit(r,3)); MVP;
sprintf(dstrp, "scroll size: w: %i, h: %i SRAM: %i; eeprom: %i (%i)\n", reg[0x10]&3, (reg[0x10]&0x30)>>4,
- bit(Pico.m.sram_reg, 4), bit(Pico.m.sram_reg, 2), SRam.eeprom_type); MVP;
+ !!(SRam.flags & SRF_ENABLED), !!(SRam.flags & SRF_EEPROM), SRam.eeprom_type); MVP;
sprintf(dstrp, "sram range: %06x-%06x, reg: %02x\n", SRam.start, SRam.end, Pico.m.sram_reg); MVP;
sprintf(dstrp, "pend int: v:%i, h:%i, vdp status: %04x\n", bit(pv->pending_ints,5), bit(pv->pending_ints,4), pv->status); MVP;
sprintf(dstrp, "pal: %i, hw: %02x, frame#: %i\n", Pico.m.pal, Pico.m.hardware, Pico.m.frame_count); MVP;
return dstr;
}
+char *PDebug32x(void)
+{
+ char *dstrp = dstr;
+ unsigned short *r;
+ int i;
+
+ r = Pico32x.regs;
+ sprintf(dstrp, "regs:\n"); MVP;
+ for (i = 0; i < 0x40/2; i += 8) {
+ sprintf(dstrp, "%02x: %04x %04x %04x %04x %04x %04x %04x %04x\n",
+ i*2, r[i+0], r[i+1], r[i+2], r[i+3], r[i+4], r[i+5], r[i+6], r[i+7]); MVP;
+ }
+
+ i = 0;
+ r = Pico32x.vdp_regs;
+ sprintf(dstrp, "VDP regs:\n"); MVP;
+ sprintf(dstrp, "%02x: %04x %04x %04x %04x %04x %04x %04x %04x\n",
+ i*2, r[i+0], r[i+1], r[i+2], r[i+3], r[i+4], r[i+5], r[i+6], r[i+7]); MVP;
+
+ sprintf(dstrp, " mSH2 sSH2\n"); MVP;
+ sprintf(dstrp, "PC: %08x %08x\n", msh2_pc(), ssh2_pc()); MVP;
+ for (i = 0; i < 16/2; i++) {
+ sprintf(dstrp, "R%d,%2d %08x,%08x %08x,%08x\n", i, i + 8,
+ msh2_reg(i), msh2_reg(i+8), ssh2_reg(i), ssh2_reg(i+8)); MVP;
+ }
+
+ return dstr;
+}
+
char *PDebugSpriteList(void)
{
struct PicoVideo *pvid=&Pico.video;
void PDebugDumpMem(void)
{
- dump_ram(Pico.ram, "dumps/ram.bin");
dump_ram_noswab(Pico.zram, "dumps/zram.bin");
- dump_ram(Pico.vram, "dumps/vram.bin");
dump_ram(Pico.cram, "dumps/cram.bin");
- dump_ram(Pico.vsram,"dumps/vsram.bin");
+
+ if (PicoAHW & PAHW_SMS)
+ {
+ dump_ram_noswab(Pico.vramb, "dumps/vram.bin");
+ }
+ else
+ {
+ dump_ram(Pico.ram, "dumps/ram.bin");
+ dump_ram(Pico.vram, "dumps/vram.bin");
+ dump_ram(Pico.vsram,"dumps/vsram.bin");
+ }
if (PicoAHW & PAHW_MCD)
{
dump_ram_noswab(Pico_mcd->pcm_ram,"dumps/pcm_ram.bin");
dump_ram_noswab(Pico_mcd->bram, "dumps/bram.bin");
}
+
+ if (PicoAHW & PAHW_32X)
+ {
+ dump_ram(Pico32xMem->sdram, "dumps/sdram.bin");
+ dump_ram(Pico32xMem->dram[0], "dumps/dram0.bin");
+ dump_ram(Pico32xMem->dram[1], "dumps/dram1.bin");
+ dump_ram(Pico32xMem->pal, "dumps/pal32x.bin");
+ }
}
void PDebugZ80Frame(void)
{
int lines, line_sample;
+ if (PicoAHW & PAHW_SMS)
+ return;
+
if (Pico.m.pal) {
lines = 312;
line_sample = 68;
timers_cycle();
}
+void PDebugCPUStep(void)
+{
+ if (PicoAHW & PAHW_SMS)
+ z80_run_nr(1);
+ else
+ SekStepM68k();
+}
+