32x: improved lockstep mode, allows compatibility over 50%

[picodrive.git] / pico / debug.c

diff --git a/pico/debug.c b/pico/debug.c
index d6b91bd..ac8f120 100644 (file)
--- a/pico/debug.c
+++ b/pico/debug.c
@@ -35,7 +35,7 @@ char *PDebugMain(void)
   sprintf(dstrp, "mode set 4: %02x\n", (r=reg[0xC])); MVP;
   sprintf(dstrp, "interlace: %i%i, cells: %i, shadow: %i\n", bit(r,2), bit(r,1), (r&0x80) ? 40 : 32, bit(r,3)); MVP;
   sprintf(dstrp, "scroll size: w: %i, h: %i  SRAM: %i; eeprom: %i (%i)\n", reg[0x10]&3, (reg[0x10]&0x30)>>4,
-       bit(Pico.m.sram_reg, 4), bit(Pico.m.sram_reg, 2), SRam.eeprom_type); MVP;
+       !!(SRam.flags & SRF_ENABLED), !!(SRam.flags & SRF_EEPROM), SRam.eeprom_type); MVP;
   sprintf(dstrp, "sram range: %06x-%06x, reg: %02x\n", SRam.start, SRam.end, Pico.m.sram_reg); MVP;
   sprintf(dstrp, "pend int: v:%i, h:%i, vdp status: %04x\n", bit(pv->pending_ints,5), bit(pv->pending_ints,4), pv->status); MVP;
   sprintf(dstrp, "pal: %i, hw: %02x, frame#: %i\n", Pico.m.pal, Pico.m.hardware, Pico.m.frame_count); MVP;
@@ -59,6 +59,40 @@ char *PDebugMain(void)
   return dstr;
 }
 
+char *PDebug32x(void)
+{
+  char *dstrp = dstr;
+  unsigned short *r;
+  int i;
+
+  r = Pico32x.regs;
+  sprintf(dstrp, "regs:\n"); MVP;
+  for (i = 0; i < 0x40/2; i += 8) {
+    sprintf(dstrp, "%02x: %04x %04x %04x %04x %04x %04x %04x %04x\n",
+      i*2, r[i+0], r[i+1], r[i+2], r[i+3], r[i+4], r[i+5], r[i+6], r[i+7]); MVP;
+  }
+  r = Pico32x.sh2_regs;
+  sprintf(dstrp, "SH: %04x %04x %04x      IRQs: %02x\n", r[0], r[1], r[2], Pico32x.sh2irqs); MVP;
+
+  i = 0;
+  r = Pico32x.vdp_regs;
+  sprintf(dstrp, "VDP regs:\n"); MVP;
+  sprintf(dstrp, "%02x: %04x %04x %04x %04x %04x %04x %04x %04x\n",
+    i*2, r[i+0], r[i+1], r[i+2], r[i+3], r[i+4], r[i+5], r[i+6], r[i+7]); MVP;
+
+  sprintf(dstrp, "                   mSH2              sSH2\n"); MVP;
+  sprintf(dstrp, "PC,SR %08x,     %03x %08x,     %03x\n", sh2_pc(0), sh2_sr(0), sh2_pc(1), sh2_sr(1)); MVP;
+  for (i = 0; i < 16/2; i++) {
+    sprintf(dstrp, "R%d,%2d %08x,%08x %08x,%08x\n", i, i + 8,
+      sh2_reg(0,i), sh2_reg(0,i+8), sh2_reg(1,i), sh2_reg(1,i+8)); MVP;
+  }
+  sprintf(dstrp, "gb,vb %08x,%08x %08x,%08x\n", sh2_gbr(0), sh2_vbr(0), sh2_gbr(1), sh2_vbr(1)); MVP;
+  sprintf(dstrp, "IRQs/mask:        %02x/%02x             %02x/%02x\n",
+    Pico32x.sh2irqi[0], Pico32x.sh2irq_mask[0], Pico32x.sh2irqi[1], Pico32x.sh2irq_mask[1]); MVP;
+
+  return dstr;
+}
+
 char *PDebugSpriteList(void)
 {
   struct PicoVideo *pvid=&Pico.video;
@@ -298,6 +332,16 @@ void PDebugDumpMem(void)
     dump_ram_noswab(Pico_mcd->pcm_ram,"dumps/pcm_ram.bin");
     dump_ram_noswab(Pico_mcd->bram,   "dumps/bram.bin");
   }
+
+  if (PicoAHW & PAHW_32X)
+  {
+    dump_ram(Pico32xMem->sdram, "dumps/sdram.bin");
+    dump_ram(Pico32xMem->dram[0], "dumps/dram0.bin");
+    dump_ram(Pico32xMem->dram[1], "dumps/dram1.bin");
+    dump_ram(Pico32xMem->pal, "dumps/pal32x.bin");
+    dump_ram(Pico32xMem->data_array[0], "dumps/data_array0.bin");
+    dump_ram(Pico32xMem->data_array[1], "dumps/data_array1.bin");
+  }
 }
 
 void PDebugZ80Frame(void)
@@ -346,7 +390,7 @@ void PDebugZ80Frame(void)
 void PDebugCPUStep(void)
 {
   if (PicoAHW & PAHW_SMS)
-    z80_run(1);
+    z80_run_nr(1);
   else
     SekStepM68k();
 }