sprintf(dstrp, "mode set 4: %02x\n", (r=reg[0xC])); MVP;
sprintf(dstrp, "interlace: %i%i, cells: %i, shadow: %i\n", bit(r,2), bit(r,1), (r&0x80) ? 40 : 32, bit(r,3)); MVP;
sprintf(dstrp, "scroll size: w: %i, h: %i SRAM: %i; eeprom: %i (%i)\n", reg[0x10]&3, (reg[0x10]&0x30)>>4,
- bit(Pico.m.sram_reg, 4), bit(Pico.m.sram_reg, 2), SRam.eeprom_type); MVP;
+ !!(SRam.flags & SRF_ENABLED), !!(SRam.flags & SRF_EEPROM), SRam.eeprom_type); MVP;
sprintf(dstrp, "sram range: %06x-%06x, reg: %02x\n", SRam.start, SRam.end, Pico.m.sram_reg); MVP;
sprintf(dstrp, "pend int: v:%i, h:%i, vdp status: %04x\n", bit(pv->pending_ints,5), bit(pv->pending_ints,4), pv->status); MVP;
sprintf(dstrp, "pal: %i, hw: %02x, frame#: %i\n", Pico.m.pal, Pico.m.hardware, Pico.m.frame_count); MVP;
void PDebugDumpMem(void)
{
- dump_ram(Pico.ram, "dumps/ram.bin");
dump_ram_noswab(Pico.zram, "dumps/zram.bin");
- dump_ram(Pico.vram, "dumps/vram.bin");
dump_ram(Pico.cram, "dumps/cram.bin");
- dump_ram(Pico.vsram,"dumps/vsram.bin");
+
+ if (PicoAHW & PAHW_SMS)
+ {
+ dump_ram_noswab(Pico.vramb, "dumps/vram.bin");
+ }
+ else
+ {
+ dump_ram(Pico.ram, "dumps/ram.bin");
+ dump_ram(Pico.vram, "dumps/vram.bin");
+ dump_ram(Pico.vsram,"dumps/vsram.bin");
+ }
if (PicoAHW & PAHW_MCD)
{
{
int lines, line_sample;
+ if (PicoAHW & PAHW_SMS)
+ return;
+
if (Pico.m.pal) {
lines = 312;
line_sample = 68;
timers_cycle();
}
+void PDebugCPUStep(void)
+{
+ if (PicoAHW & PAHW_SMS)
+ z80_run_nr(1);
+ else
+ SekStepM68k();
+}
+