--- /dev/null
+@ vim:filetype=armasm\r
+\r
+@ memory handlers with banking support for SSF II - The New Challengers\r
+@ mostly based on Gens code\r
+\r
+@ (c) Copyright 2006-2007, Grazvydas "notaz" Ignotas\r
+@ All Rights Reserved\r
+\r
+\r
+.include "port_config.s"\r
+\r
+.text\r
+.align 4\r
+\r
+@ default jump tables\r
+\r
+m_read8_def_table:\r
+ .long m_read8_rom0 @ 0x000000 - 0x07FFFF\r
+ .long m_read8_rom1 @ 0x080000 - 0x0FFFFF\r
+ .long m_read8_rom2 @ 0x100000 - 0x17FFFF\r
+ .long m_read8_rom3 @ 0x180000 - 0x1FFFFF\r
+ .long m_read8_rom4 @ 0x200000 - 0x27FFFF\r
+ .long m_read8_rom5 @ 0x280000 - 0x2FFFFF\r
+ .long m_read8_rom6 @ 0x300000 - 0x37FFFF\r
+ .long m_read8_rom7 @ 0x380000 - 0x3FFFFF\r
+ .long m_read8_rom8 @ 0x400000 - 0x47FFFF - for all those large ROM hacks\r
+ .long m_read8_rom9 @ 0x480000 - 0x4FFFFF\r
+ .long m_read8_romA @ 0x500000 - 0x57FFFF\r
+ .long m_read8_romB @ 0x580000 - 0x5FFFFF\r
+ .long m_read8_romC @ 0x600000 - 0x67FFFF\r
+ .long m_read8_romD @ 0x680000 - 0x6FFFFF\r
+ .long m_read8_romE @ 0x700000 - 0x77FFFF\r
+ .long m_read8_romF @ 0x780000 - 0x7FFFFF\r
+ .long m_read8_rom10 @ 0x800000 - 0x87FFFF\r
+ .long m_read8_rom11 @ 0x880000 - 0x8FFFFF\r
+ .long m_read8_rom12 @ 0x900000 - 0x97FFFF\r
+ .long m_read8_rom13 @ 0x980000 - 0x9FFFFF\r
+ .long m_read8_misc @ 0xA00000 - 0xA7FFFF\r
+ .long m_read_null @ 0xA80000 - 0xAFFFFF\r
+ .long m_read_null @ 0xB00000 - 0xB7FFFF\r
+ .long m_read_null @ 0xB80000 - 0xBFFFFF\r
+ .long m_read8_vdp @ 0xC00000 - 0xC7FFFF\r
+ .long m_read8_vdp @ 0xC80000 - 0xCFFFFF\r
+ .long m_read8_vdp @ 0xD00000 - 0xD7FFFF\r
+ .long m_read8_vdp @ 0xD80000 - 0xDFFFFF\r
+ .long m_read8_ram @ 0xE00000 - 0xE7FFFF\r
+ .long m_read8_ram @ 0xE80000 - 0xEFFFFF\r
+ .long m_read8_ram @ 0xF00000 - 0xF7FFFF\r
+ .long m_read8_ram @ 0xF80000 - 0xFFFFFF\r
+\r
+m_read16_def_table:\r
+ .long m_read16_rom0 @ 0x000000 - 0x07FFFF\r
+ .long m_read16_rom1 @ 0x080000 - 0x0FFFFF\r
+ .long m_read16_rom2 @ 0x100000 - 0x17FFFF\r
+ .long m_read16_rom3 @ 0x180000 - 0x1FFFFF\r
+ .long m_read16_rom4 @ 0x200000 - 0x27FFFF\r
+ .long m_read16_rom5 @ 0x280000 - 0x2FFFFF\r
+ .long m_read16_rom6 @ 0x300000 - 0x37FFFF\r
+ .long m_read16_rom7 @ 0x380000 - 0x3FFFFF\r
+ .long m_read16_rom8 @ 0x400000 - 0x47FFFF\r
+ .long m_read16_rom9 @ 0x480000 - 0x4FFFFF\r
+ .long m_read16_romA @ 0x500000 - 0x57FFFF\r
+ .long m_read16_romB @ 0x580000 - 0x5FFFFF\r
+ .long m_read16_romC @ 0x600000 - 0x67FFFF\r
+ .long m_read16_romD @ 0x680000 - 0x6FFFFF\r
+ .long m_read16_romE @ 0x700000 - 0x77FFFF\r
+ .long m_read16_romF @ 0x780000 - 0x7FFFFF\r
+ .long m_read16_rom10 @ 0x800000 - 0x87FFFF\r
+ .long m_read16_rom11 @ 0x880000 - 0x8FFFFF\r
+ .long m_read16_rom12 @ 0x900000 - 0x97FFFF\r
+ .long m_read16_rom13 @ 0x980000 - 0x9FFFFF\r
+ .long m_read16_misc @ 0xA00000 - 0xA7FFFF\r
+ .long m_read_null @ 0xA80000 - 0xAFFFFF\r
+ .long m_read_null @ 0xB00000 - 0xB7FFFF\r
+ .long m_read_null @ 0xB80000 - 0xBFFFFF\r
+ .long m_read16_vdp @ 0xC00000 - 0xC7FFFF\r
+ .long m_read16_vdp @ 0xC80000 - 0xCFFFFF\r
+ .long m_read16_vdp @ 0xD00000 - 0xD7FFFF\r
+ .long m_read16_vdp @ 0xD80000 - 0xDFFFFF\r
+ .long m_read16_ram @ 0xE00000 - 0xE7FFFF\r
+ .long m_read16_ram @ 0xE80000 - 0xEFFFFF\r
+ .long m_read16_ram @ 0xF00000 - 0xF7FFFF\r
+ .long m_read16_ram @ 0xF80000 - 0xFFFFFF\r
+\r
+m_read32_def_table:\r
+ .long m_read32_rom0 @ 0x000000 - 0x07FFFF\r
+ .long m_read32_rom1 @ 0x080000 - 0x0FFFFF\r
+ .long m_read32_rom2 @ 0x100000 - 0x17FFFF\r
+ .long m_read32_rom3 @ 0x180000 - 0x1FFFFF\r
+ .long m_read32_rom4 @ 0x200000 - 0x27FFFF\r
+ .long m_read32_rom5 @ 0x280000 - 0x2FFFFF\r
+ .long m_read32_rom6 @ 0x300000 - 0x37FFFF\r
+ .long m_read32_rom7 @ 0x380000 - 0x3FFFFF\r
+ .long m_read32_rom8 @ 0x400000 - 0x47FFFF\r
+ .long m_read32_rom9 @ 0x480000 - 0x4FFFFF\r
+ .long m_read32_romA @ 0x500000 - 0x57FFFF\r
+ .long m_read32_romB @ 0x580000 - 0x5FFFFF\r
+ .long m_read32_romC @ 0x600000 - 0x67FFFF\r
+ .long m_read32_romD @ 0x680000 - 0x6FFFFF\r
+ .long m_read32_romE @ 0x700000 - 0x77FFFF\r
+ .long m_read32_romF @ 0x780000 - 0x7FFFFF\r
+ .long m_read32_rom10 @ 0x800000 - 0x87FFFF\r
+ .long m_read32_rom11 @ 0x880000 - 0x8FFFFF\r
+ .long m_read32_rom12 @ 0x900000 - 0x97FFFF\r
+ .long m_read32_rom13 @ 0x980000 - 0x9FFFFF\r
+ .long m_read32_misc @ 0xA00000 - 0xA7FFFF\r
+ .long m_read_null @ 0xA80000 - 0xAFFFFF\r
+ .long m_read_null @ 0xB00000 - 0xB7FFFF\r
+ .long m_read_null @ 0xB80000 - 0xBFFFFF\r
+ .long m_read32_vdp @ 0xC00000 - 0xC7FFFF\r
+ .long m_read32_vdp @ 0xC80000 - 0xCFFFFF\r
+ .long m_read32_vdp @ 0xD00000 - 0xD7FFFF\r
+ .long m_read32_vdp @ 0xD80000 - 0xDFFFFF\r
+ .long m_read32_ram @ 0xE00000 - 0xE7FFFF\r
+ .long m_read32_ram @ 0xE80000 - 0xEFFFFF\r
+ .long m_read32_ram @ 0xF00000 - 0xF7FFFF\r
+ .long m_read32_ram @ 0xF80000 - 0xFFFFFF\r
+\r
+\r
+@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+\r
+.bss\r
+.align 4\r
+@.section .bss, "brw"\r
+@.data\r
+\r
+@ used tables\r
+m_read8_table:\r
+ .skip 32*4\r
+\r
+m_read16_table:\r
+ .skip 32*4\r
+\r
+m_read32_table:\r
+ .skip 32*4\r
+\r
+\r
+@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+\r
+.text\r
+.align 4\r
+\r
+.global PicoMemReset\r
+.global PicoRead8\r
+.global PicoRead16\r
+.global PicoRead32\r
+.global PicoWrite8\r
+.global PicoWriteRomHW_SSF2\r
+.global m_m68k_read8_misc\r
+.global m_m68k_write8_misc\r
+\r
+\r
+PicoMemReset:\r
+ ldr r12,=(Pico+0x22204)\r
+ ldr r12,[r12] @ romsize\r
+ add r12,r12,#0x80000\r
+ sub r12,r12,#1\r
+ mov r12,r12,lsr #19\r
+\r
+ ldr r0, =m_read8_table\r
+ ldr r1, =m_read8_def_table\r
+ mov r2, #32\r
+1:\r
+ ldr r3, [r1], #4\r
+ str r3, [r0], #4\r
+ subs r2, r2, #1\r
+ bne 1b\r
+\r
+ ldr r0, =m_read16_table\r
+ ldr r1, =m_read16_def_table\r
+ mov r2, #32\r
+1:\r
+ subs r2, r2, #1\r
+ ldr r3, [r1], #4\r
+ str r3, [r0], #4\r
+ bne 1b\r
+\r
+ ldr r0, =m_read32_table\r
+ ldr r1, =m_read32_def_table\r
+ mov r2, #32\r
+1:\r
+ subs r2, r2, #1\r
+ ldr r3, [r1], #4\r
+ str r3, [r0], #4\r
+ bne 1b\r
+\r
+ @ update memhandlers according to ROM size\r
+ ldr r1, =m_read8_above_rom\r
+ ldr r0, =m_read8_table\r
+ mov r2, #20\r
+1:\r
+ sub r2, r2, #1\r
+ cmp r2, r12\r
+ blt 2f\r
+ cmp r2, #4\r
+ beq 1b @ do not touch the SRAM area\r
+ str r1, [r0, r2, lsl #2]\r
+ b 1b\r
+2:\r
+ ldr r1, =m_read16_above_rom\r
+ ldr r0, =m_read16_table\r
+ mov r2, #20\r
+1:\r
+ sub r2, r2, #1\r
+ cmp r2, r12\r
+ blt 2f\r
+ cmp r2, #4\r
+ beq 1b\r
+ str r1, [r0, r2, lsl #2]\r
+ b 1b\r
+2:\r
+ ldr r1, =m_read32_above_rom\r
+ ldr r0, =m_read32_table\r
+ mov r2, #20\r
+1:\r
+ sub r2, r2, #1\r
+ cmp r2, r12\r
+ blt 2f\r
+ cmp r2, #4\r
+ beq 1b\r
+ str r1, [r0, r2, lsl #2]\r
+ b 1b\r
+2:\r
+ bx lr\r
+\r
+.pool\r
+\r
+@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+\r
+PicoRead8: @ u32 a\r
+ ldr r2, =m_read8_table\r
+ bic r0, r0, #0xff000000\r
+ and r1, r0, #0x00f80000\r
+ ldr pc, [r2, r1, lsr #17]\r
+\r
+PicoRead16: @ u32 a\r
+ ldr r2, =m_read16_table\r
+ bic r0, r0, #0xff000000\r
+ and r1, r0, #0x00f80000\r
+ ldr pc, [r2, r1, lsr #17]\r
+\r
+PicoRead32: @ u32 a\r
+ ldr r2, =m_read32_table\r
+ bic r0, r0, #0xff000000\r
+ and r1, r0, #0x00f80000\r
+ ldr pc, [r2, r1, lsr #17]\r
+\r
+.pool\r
+\r
+@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+\r
+m_read_null:\r
+ mov r0, #0\r
+ bx lr\r
+\r
+\r
+.macro m_read8_rom sect\r
+ ldr r1, =(Pico+0x22200)\r
+ bic r0, r0, #0xf80000\r
+ ldr r1, [r1]\r
+.if \sect\r
+ orr r0, r0, #0x080000*\sect\r
+.endif\r
+ eor r0, r0, #1\r
+ ldrb r0, [r1, r0]\r
+ bx lr\r
+.endm\r
+\r
+\r
+m_read8_rom0: @ 0x000000 - 0x07ffff\r
+ m_read8_rom 0\r
+\r
+m_read8_rom1: @ 0x080000 - 0x0fffff\r
+ m_read8_rom 1\r
+\r
+m_read8_rom2: @ 0x100000 - 0x17ffff\r
+ m_read8_rom 2\r
+\r
+m_read8_rom3: @ 0x180000 - 0x1fffff\r
+ m_read8_rom 3\r
+\r
+m_read8_rom4: @ 0x200000 - 0x27ffff, SRAM area\r
+ ldr r2, =(SRam)\r
+ ldr r3, =(Pico+0x22200)\r
+ ldr r1, [r2, #8] @ SRam.end\r
+ bic r0, r0, #0xf80000\r
+ orr r0, r0, #0x200000\r
+ cmp r0, r1\r
+ bgt m_read8_nosram\r
+ ldr r1, [r2, #4] @ SRam.start\r
+ cmp r0, r1\r
+ blt m_read8_nosram\r
+ ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
+ tst r1, #5\r
+ bne SRAMRead\r
+m_read8_nosram:\r
+ ldr r1, [r3, #4] @ romsize\r
+ cmp r0, r1\r
+ movgt r0, #0\r
+ bxgt lr @ bad location\r
+ ldr r1, [r3]\r
+ eor r0, r0, #1\r
+ ldrb r0, [r1, r0]\r
+ bx lr\r
+\r
+m_read8_rom5: @ 0x280000 - 0x2fffff\r
+ m_read8_rom 5\r
+\r
+m_read8_rom6: @ 0x300000 - 0x37ffff\r
+ m_read8_rom 6\r
+\r
+m_read8_rom7: @ 0x380000 - 0x3fffff\r
+ m_read8_rom 7\r
+\r
+m_read8_rom8: @ 0x400000 - 0x47ffff\r
+ m_read8_rom 8\r
+\r
+m_read8_rom9: @ 0x480000 - 0x4fffff\r
+ m_read8_rom 9\r
+\r
+m_read8_romA: @ 0x500000 - 0x57ffff\r
+ m_read8_rom 0xA\r
+\r
+m_read8_romB: @ 0x580000 - 0x5fffff\r
+ m_read8_rom 0xB\r
+\r
+m_read8_romC: @ 0x600000 - 0x67ffff\r
+ m_read8_rom 0xC\r
+\r
+m_read8_romD: @ 0x680000 - 0x6fffff\r
+ m_read8_rom 0xD\r
+\r
+m_read8_romE: @ 0x700000 - 0x77ffff\r
+ m_read8_rom 0xE\r
+\r
+m_read8_romF: @ 0x780000 - 0x7fffff\r
+ m_read8_rom 0xF\r
+\r
+m_read8_rom10: @ 0x800000 - 0x87ffff\r
+ m_read8_rom 0x10\r
+\r
+m_read8_rom11: @ 0x880000 - 0x8fffff\r
+ m_read8_rom 0x11\r
+\r
+m_read8_rom12: @ 0x900000 - 0x97ffff\r
+ m_read8_rom 0x12\r
+\r
+m_read8_rom13: @ 0x980000 - 0x9fffff\r
+ m_read8_rom 0x13\r
+\r
+\r
+m_m68k_read8_misc:\r
+m_read8_misc:\r
+ bic r2, r0, #0x001f @ most commonly we get i/o port read,\r
+ cmp r2, #0xa10000 @ so check for it first\r
+ bne m_read8_misc2\r
+m_read8_misc_io:\r
+ ands r0, r0, #0x1e\r
+ beq m_read8_misc_hwreg\r
+ cmp r0, #4\r
+ movlt r0, #0\r
+ moveq r0, #1\r
+ ble PadRead\r
+ ldr r3, =(Pico+0x22000)\r
+ mov r0, r0, lsr #1 @ other IO ports (Pico.ioports[a])\r
+ ldrb r0, [r3, r0]\r
+ bx lr\r
+\r
+m_read8_misc_hwreg:\r
+ ldr r3, =(Pico+0x22200)\r
+ ldrb r0, [r3, #0x0f] @ Pico.m.hardware\r
+ bx lr\r
+\r
+m_read8_misc2:\r
+ mov r2, #0xa10000 @ games also like to poll busreq,\r
+ orr r2, r2, #0x001100 @ so we'll try it now\r
+ cmp r0, r2\r
+ beq z80ReadBusReq\r
+\r
+ and r2, r0, #0xff0000 @ finally it might be\r
+ cmp r2, #0xa00000 @ z80 area\r
+ bne m_read8_misc3\r
+ tst r0, #0x4000\r
+ beq z80Read8 @ z80 RAM\r
+ and r2, r0, #0x6000\r
+ cmp r2, #0x4000\r
+ mvnne r0, #0\r
+ bxne lr @ invalid\r
+ b ym2612_read_local_68k\r
+\r
+m_read8_fake_ym2612:\r
+ ldr r3, =(Pico+0x22200)\r
+ ldrb r0, [r3, #8] @ Pico.m.rotate\r
+ add r1, r0, #1\r
+ strb r1, [r3, #8]\r
+ and r0, r0, #3\r
+ bx lr\r
+\r
+m_read8_misc3:\r
+ @ if everything else fails, use generic handler\r
+ stmfd sp!,{r0,lr}\r
+ bic r0, r0, #1\r
+ mov r1, #8\r
+ bl OtherRead16\r
+ ldmfd sp!,{r1,lr}\r
+ tst r1, #1\r
+ moveq r0, r0, lsr #8\r
+ bx lr\r
+\r
+\r
+m_read8_vdp:\r
+ tst r0, #0x70000\r
+ tsteq r0, #0x000e0\r
+ bxne lr @ invalid read\r
+ b PicoVideoRead8\r
+\r
+m_read8_ram:\r
+ ldr r1, =Pico\r
+ bic r0, r0, #0xff0000\r
+ eor r0, r0, #1\r
+ ldrb r0, [r1, r0]\r
+ bx lr\r
+\r
+m_read8_above_rom:\r
+ @ might still be SRam (Micro Machines, HardBall '95)\r
+ ldr r2, =(SRam)\r
+ ldr r3, =(Pico+0x22200)\r
+ ldr r1, [r2, #8] @ SRam.end\r
+ cmp r0, r1\r
+ bgt m_read8_ar_nosram\r
+ ldr r1, [r2, #4] @ SRam.start\r
+ cmp r0, r1\r
+ blt m_read8_ar_nosram\r
+ ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
+ tst r1, #5\r
+ bne SRAMRead\r
+m_read8_ar_nosram:\r
+ ldr r2, =PicoRead16Hook\r
+ stmfd sp!,{r0,lr}\r
+ ldr r2, [r2]\r
+ bic r0, r0, #1\r
+ mov r1, #8\r
+ mov lr, pc\r
+ bx r2\r
+ ldmfd sp!,{r1,lr}\r
+ tst r1, #1\r
+ moveq r0, r0, lsr #8\r
+ bx lr\r
+\r
+.pool\r
+\r
+@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+\r
+.macro m_read16_rom sect\r
+ ldr r1, =(Pico+0x22200)\r
+ bic r0, r0, #0xf80000\r
+ ldr r1, [r1]\r
+ bic r0, r0, #1\r
+.if \sect\r
+ orr r0, r0, #0x080000*\sect\r
+.endif\r
+ ldrh r0, [r1, r0]\r
+ bx lr\r
+.endm\r
+\r
+\r
+m_read16_rom0: @ 0x000000 - 0x07ffff\r
+ m_read16_rom 0\r
+\r
+m_read16_rom1: @ 0x080000 - 0x0fffff\r
+ m_read16_rom 1\r
+\r
+m_read16_rom2: @ 0x100000 - 0x17ffff\r
+ m_read16_rom 2\r
+\r
+m_read16_rom3: @ 0x180000 - 0x1fffff\r
+ m_read16_rom 3\r
+\r
+m_read16_rom4: @ 0x200000 - 0x27ffff, SRAM area (NBA Live 95)\r
+ ldr r2, =(SRam)\r
+ ldr r3, =(Pico+0x22200)\r
+ ldr r1, [r2, #8] @ SRam.end\r
+ bic r0, r0, #0xf80000\r
+ bic r0, r0, #1\r
+ orr r0, r0, #0x200000\r
+ cmp r0, r1\r
+ bgt m_read16_nosram\r
+ ldr r1, [r2, #4] @ SRam.start\r
+ cmp r0, r1\r
+ blt m_read16_nosram\r
+ ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
+ tst r1, #5\r
+ beq m_read16_nosram\r
+ stmfd sp!,{lr}\r
+ bl SRAMRead16\r
+ ldmfd sp!,{pc}\r
+m_read16_nosram:\r
+ ldr r1, [r3, #4] @ romsize\r
+ cmp r0, r1\r
+ movgt r0, #0\r
+ bxgt lr @ bad location\r
+ ldr r1, [r3] @ 1ci\r
+ ldrh r0, [r1, r0]\r
+ bx lr\r
+\r
+m_read16_rom5: @ 0x280000 - 0x2fffff\r
+ m_read16_rom 5\r
+\r
+m_read16_rom6: @ 0x300000 - 0x37ffff\r
+ m_read16_rom 6\r
+\r
+m_read16_rom7: @ 0x380000 - 0x3fffff\r
+ m_read16_rom 7\r
+\r
+m_read16_rom8: @ 0x400000 - 0x47ffff\r
+ m_read16_rom 8\r
+\r
+m_read16_rom9: @ 0x480000 - 0x4fffff\r
+ m_read16_rom 9\r
+\r
+m_read16_romA: @ 0x500000 - 0x57ffff\r
+ m_read16_rom 0xA\r
+\r
+m_read16_romB: @ 0x580000 - 0x5fffff\r
+ m_read16_rom 0xB\r
+\r
+m_read16_romC: @ 0x600000 - 0x67ffff\r
+ m_read16_rom 0xC\r
+\r
+m_read16_romD: @ 0x680000 - 0x6fffff\r
+ m_read16_rom 0xD\r
+\r
+m_read16_romE: @ 0x700000 - 0x77ffff\r
+ m_read16_rom 0xE\r
+\r
+m_read16_romF: @ 0x780000 - 0x7fffff\r
+ m_read16_rom 0xF\r
+\r
+m_read16_rom10: @ 0x800000 - 0x87ffff\r
+ m_read16_rom 0x10\r
+\r
+m_read16_rom11: @ 0x880000 - 0x8fffff\r
+ m_read16_rom 0x11\r
+\r
+m_read16_rom12: @ 0x900000 - 0x97ffff\r
+ m_read16_rom 0x12\r
+\r
+m_read16_rom13: @ 0x980000 - 0x9fffff\r
+ m_read16_rom 0x13\r
+\r
+m_read16_misc:\r
+ bic r0, r0, #1\r
+ mov r1, #16\r
+ b OtherRead16\r
+\r
+m_read16_vdp:\r
+ tst r0, #0x70000 @ if ((a&0xe700e0)==0xc00000)\r
+ tsteq r0, #0x000e0\r
+ bxne lr @ invalid read\r
+ bic r0, r0, #1\r
+ b PicoVideoRead\r
+\r
+m_read16_ram:\r
+ ldr r1, =Pico\r
+ bic r0, r0, #0xff0000\r
+ bic r0, r0, #1\r
+ ldrh r0, [r1, r0]\r
+ bx lr\r
+\r
+m_read16_above_rom:\r
+ @ might still be SRam\r
+ ldr r2, =(SRam)\r
+ ldr r3, =(Pico+0x22200)\r
+ ldr r1, [r2, #8] @ SRam.end\r
+ bic r0, r0, #1\r
+ cmp r0, r1\r
+ bgt m_read16_ar_nosram\r
+ ldr r1, [r2, #4] @ SRam.start\r
+ cmp r0, r1\r
+ blt m_read16_ar_nosram\r
+ ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
+ tst r1, #5\r
+ beq m_read16_ar_nosram\r
+ stmfd sp!,{lr}\r
+ bl SRAMRead16\r
+ ldmfd sp!,{pc}\r
+m_read16_ar_nosram:\r
+ ldr r2, =PicoRead16Hook\r
+ ldr r2, [r2]\r
+ mov r1, #16\r
+ bx r2\r
+\r
+.pool\r
+\r
+@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+\r
+.macro m_read32_rom sect\r
+ ldr r1, =(Pico+0x22200)\r
+ bic r0, r0, #0xf80000\r
+ ldr r1, [r1]\r
+ bic r0, r0, #1\r
+.if \sect\r
+ orr r0, r0, #0x080000*\sect\r
+.endif\r
+ ldrh r0, [r1, r0]!\r
+ ldrh r1, [r1, #2] @ 1ci\r
+ orr r0, r1, r0, lsl #16\r
+ bx lr\r
+.endm\r
+\r
+\r
+m_read32_rom0: @ 0x000000 - 0x07ffff\r
+ m_read32_rom 0\r
+\r
+m_read32_rom1: @ 0x080000 - 0x0fffff\r
+ m_read32_rom 1\r
+\r
+m_read32_rom2: @ 0x100000 - 0x17ffff\r
+ m_read32_rom 2\r
+\r
+m_read32_rom3: @ 0x180000 - 0x1fffff\r
+ m_read32_rom 3\r
+\r
+m_read32_rom4: @ 0x200000 - 0x27ffff, SRAM area (does any game do long reads?)\r
+ ldr r2, =(SRam)\r
+ ldr r3, =(Pico+0x22200)\r
+ ldr r1, [r2, #8] @ SRam.end\r
+ bic r0, r0, #0xf80000\r
+ bic r0, r0, #1\r
+ orr r0, r0, #0x200000\r
+ cmp r0, r1\r
+ bgt m_read32_nosram\r
+ ldr r1, [r2, #4] @ SRam.start\r
+ cmp r0, r1\r
+ blt m_read32_nosram\r
+ ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
+ tst r1, #5\r
+ beq m_read32_nosram\r
+ stmfd sp!,{r0,lr}\r
+ bl SRAMRead16\r
+ ldmfd sp!,{r1,lr}\r
+ stmfd sp!,{r0,lr}\r
+ add r0, r1, #2\r
+ bl SRAMRead16\r
+ ldmfd sp!,{r1,lr}\r
+ orr r0, r0, r1, lsl #16\r
+ bx lr\r
+m_read32_nosram:\r
+ ldr r1, [r3, #4] @ romsize\r
+ cmp r0, r1\r
+ movgt r0, #0\r
+ bxgt lr @ bad location\r
+ ldr r1, [r3] @ (1ci)\r
+ ldrh r0, [r1, r0]!\r
+ ldrh r1, [r1, #2] @ (2ci)\r
+ orr r0, r1, r0, lsl #16\r
+ bx lr\r
+\r
+m_read32_rom5: @ 0x280000 - 0x2fffff\r
+ m_read32_rom 5\r
+\r
+m_read32_rom6: @ 0x300000 - 0x37ffff\r
+ m_read32_rom 6\r
+\r
+m_read32_rom7: @ 0x380000 - 0x3fffff\r
+ m_read32_rom 7\r
+\r
+m_read32_rom8: @ 0x400000 - 0x47ffff\r
+ m_read32_rom 8\r
+\r
+m_read32_rom9: @ 0x480000 - 0x4fffff\r
+ m_read32_rom 9\r
+\r
+m_read32_romA: @ 0x500000 - 0x57ffff\r
+ m_read32_rom 0xA\r
+\r
+m_read32_romB: @ 0x580000 - 0x5fffff\r
+ m_read32_rom 0xB\r
+\r
+m_read32_romC: @ 0x600000 - 0x67ffff\r
+ m_read32_rom 0xC\r
+\r
+m_read32_romD: @ 0x680000 - 0x6fffff\r
+ m_read32_rom 0xD\r
+\r
+m_read32_romE: @ 0x700000 - 0x77ffff\r
+ m_read32_rom 0xE\r
+\r
+m_read32_romF: @ 0x780000 - 0x7fffff\r
+ m_read32_rom 0xF\r
+\r
+m_read32_rom10: @ 0x800000 - 0x87ffff\r
+ m_read32_rom 0x10\r
+\r
+m_read32_rom11: @ 0x880000 - 0x8fffff\r
+ m_read32_rom 0x11\r
+\r
+m_read32_rom12: @ 0x900000 - 0x97ffff\r
+ m_read32_rom 0x12\r
+\r
+m_read32_rom13: @ 0x980000 - 0x9fffff\r
+ m_read32_rom 0x13\r
+\r
+m_read32_misc:\r
+ bic r0, r0, #1\r
+ stmfd sp!,{r0,lr}\r
+ mov r1, #32\r
+ bl OtherRead16\r
+ mov r1, r0\r
+ ldmfd sp!,{r0}\r
+ stmfd sp!,{r1}\r
+ add r0, r0, #2\r
+ mov r1, #32\r
+ bl OtherRead16\r
+ ldmfd sp!,{r1,lr}\r
+ orr r0, r0, r1, lsl #16\r
+ bx lr\r
+\r
+m_read32_vdp:\r
+ tst r0, #0x70000\r
+ tsteq r0, #0x000e0\r
+ bxne lr @ invalid read\r
+ bic r0, r0, #1\r
+ add r1, r0, #2\r
+ stmfd sp!,{r1,lr}\r
+ bl PicoVideoRead\r
+ swp r0, r0, [sp]\r
+ bl PicoVideoRead\r
+ ldmfd sp!,{r1,lr}\r
+ orr r0, r0, r1, lsl #16\r
+ bx lr\r
+\r
+m_read32_ram:\r
+ ldr r1, =Pico\r
+ bic r0, r0, #0xff0000\r
+ bic r0, r0, #1\r
+ ldrh r0, [r1, r0]!\r
+ ldrh r1, [r1, #2] @ 2ci\r
+ orr r0, r1, r0, lsl #16\r
+ bx lr\r
+\r
+m_read32_above_rom:\r
+ ldr r2, =PicoRead16Hook\r
+ bic r0, r0, #1\r
+ ldr r2, [r2]\r
+ mov r1, #32\r
+ stmfd sp!,{r0,r2,lr}\r
+ mov lr, pc\r
+ bx r2\r
+ mov r1, r0\r
+ ldmfd sp!,{r0,r2}\r
+ stmfd sp!,{r1}\r
+ add r0, r0, #2\r
+ mov r1, #32\r
+ mov lr, pc\r
+ bx r2\r
+ ldmfd sp!,{r1,lr}\r
+ orr r0, r0, r1, lsl #16\r
+ bx lr\r
+\r
+.pool\r
+\r
+@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+\r
+PicoWriteRomHW_SSF2: @ u32 a, u32 d\r
+ and r0, r0, #0xe\r
+ movs r0, r0, lsr #1\r
+ bne pwr_banking\r
+\r
+ @ sram register\r
+ ldr r2, =(Pico+0x22211) @ Pico.m.sram_reg\r
+ ldrb r0, [r2]\r
+ and r1, r1, #3\r
+ bic r0, r0, #3\r
+ orr r0, r0, r1\r
+ strb r0, [r2]\r
+ bx lr\r
+\r
+pwr_banking:\r
+ and r1, r1, #0x1f\r
+\r
+ ldr r3, =m_read8_def_table\r
+ ldr r2, =m_read8_table\r
+ ldr r12, [r3, r1, lsl #2]\r
+ str r12, [r2, r0, lsl #2]\r
+\r
+ ldr r3, =m_read16_def_table\r
+ ldr r2, =m_read16_table\r
+ ldr r12, [r3, r1, lsl #2]\r
+ str r12, [r2, r0, lsl #2]\r
+\r
+ ldr r3, =m_read32_def_table\r
+ ldr r2, =m_read32_table\r
+ ldr r12, [r3, r1, lsl #2]\r
+ str r12, [r2, r0, lsl #2]\r
+ \r
+ bx lr\r
+\r
+@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+\r
+@ Here we only handle most often used locations,\r
+@ everything else is passed to generic handlers\r
+\r
+PicoWrite8: @ u32 a, u8 d\r
+ bic r0, r0, #0xff000000\r
+ and r2, r0, #0x00e00000\r
+ cmp r2, #0x00e00000 @ RAM?\r
+ ldr r3, =Pico\r
+ biceq r0, r0, #0x00ff0000\r
+ eoreq r0, r0, #1\r
+ streqb r1, [r3, r0]\r
+ bxeq lr\r
+\r
+m_m68k_write8_misc:\r
+ bic r2, r0, #0x1f @ most commonly we get i/o port write,\r
+ cmp r2, #0xa10000 @ so check for it first\r
+ bne m_write8_misc2\r
+m_write8_io:\r
+ ldr r2, =PicoOpt\r
+ and r0, r0, #0x1e\r
+ ldr r2, [r2]\r
+ ldr r3, =(Pico+0x22000) @ Pico.ioports\r
+ tst r2, #0x20 @ 6 button pad?\r
+ streqb r1, [r3, r0, lsr #1]\r
+ bxeq lr\r
+ cmp r0, #2\r
+ cmpne r0, #4\r
+ bne m_write8_io_done @ not likely to happen\r
+ add r2, r3, #0x200 @ Pico+0x22200\r
+ mov r12,#0\r
+ cmp r0, #2\r
+ streqb r12,[r2,#0x18]\r
+ strneb r12,[r2,#0x19] @ Pico.m.padDelay[i] = 0\r
+ tst r1, #0x40 @ TH\r
+ beq m_write8_io_done\r
+ ldrb r12,[r3, r0, lsr #1]\r
+ tst r12,#0x40\r
+ bne m_write8_io_done\r
+ cmp r0, #2\r
+ ldreqb r12,[r2,#0x0a]\r
+ ldrneb r12,[r2,#0x0b] @ Pico.m.padTHPhase\r
+ add r12,r12,#1\r
+ streqb r12,[r2,#0x0a]\r
+ strneb r12,[r2,#0x0b] @ Pico.m.padTHPhase\r
+m_write8_io_done:\r
+ strb r1, [r3, r0, lsr #1]\r
+ bx lr\r
+\r
+\r
+m_write8_misc2:\r
+ and r2, r0, #0xff0000\r
+ cmp r2, #0xa00000 @ z80 area?\r
+ bne m_write8_not_z80\r
+ tst r0, #0x4000\r
+ bne m_write8_z80_not_ram\r
+ ldr r3, =(Pico+0x20000) @ Pico.zram\r
+ add r2, r3, #0x02200 @ Pico+0x22200\r
+ ldrb r2, [r2, #9] @ Pico.m.z80Run\r
+ bic r0, r0, #0xff0000\r
+ bic r0, r0, #0x00e000\r
+ tst r2, #1\r
+ ldr r2, =SekCycleCnt\r
+ streqb r1, [r3, r0] @ zram\r
+ ldr r0, [r2]\r
+ add r0, r0, #2 @ hack?\r
+ str r0, [r2]\r
+ bx lr\r
+\r
+m_write8_z80_not_ram:\r
+ and r2, r0, #0x6000\r
+ cmp r2, #0x4000\r
+ bne m_write8_z80_not_ym2612\r
+ ldr r3, =PicoOpt\r
+ and r0, r0, #3\r
+ ldr r3, [r3]\r
+ mov r2, #0 @ is_from_z80 = 0\r
+ tst r3, #1\r
+ bxeq lr\r
+ stmfd sp!,{lr}\r
+ and r1, r1, #0xff\r
+ bl ym2612_write_local\r
+ ldr r2, =emustatus\r
+ ldmfd sp!,{lr}\r
+ ldr r1, [r2]\r
+ and r0, r0, #1\r
+ orr r1, r0, r1\r
+ str r1, [r2] @ emustatus|=ym2612_write_local(a&3, d);\r
+ bx lr\r
+\r
+m_write8_z80_not_ym2612: @ not too likely\r
+ mov r2, r0, lsl #17\r
+ bic r2, r2, #6<<17\r
+ mov r3, #0x7f00\r
+ orr r3, r3, #0x0011\r
+ cmp r3, r2, lsr #17 @ psg @ z80 area?\r
+ beq m_write8_psg\r
+ and r2, r0, #0x7f00\r
+ cmp r2, #0x6000 @ bank register?\r
+ bxne lr @ invalid write\r
+\r
+m_write8_z80_bank_reg:\r
+ ldr r3, =(Pico+0x22208) @ Pico.m\r
+ ldrh r2, [r3, #0x0a]\r
+ mov r1, r1, lsl #8\r
+ orr r2, r1, r2, lsr #1\r
+ bic r2, r2, #0xfe00\r
+ strh r2, [r3, #0x0a]\r
+ bx lr\r
+\r
+\r
+m_write8_not_z80:\r
+ and r2, r0, #0xe70000\r
+ cmp r2, #0xc00000 @ VDP area?\r
+ bne OtherWrite8 @ passthrough\r
+ and r2, r0, #0xf9\r
+ cmp r2, #0x11\r
+ bne OtherWrite8\r
+m_write8_psg:\r
+ ldr r2, =PicoOpt\r
+ and r0, r1, #0xff\r
+ ldr r2, [r2]\r
+ tst r2, #2\r
+ bxeq lr\r
+ b SN76496Write\r
+\r
notaz.gp2x.de / picodrive.git / blobdiff