32x: sh2 wip, main SH2 BIOS passes

[picodrive.git] / pico / pico_cmn.c

diff --git a/pico/pico_cmn.c b/pico/pico_cmn.c
index 368b4c8..212ed8d 100644 (file)
--- a/pico/pico_cmn.c
+++ b/pico/pico_cmn.c
@@ -1,5 +1,5 @@
 // common code for Pico.c and cd/Pico.c
-// (c) Copyright 2007,2008 Grazvydas "notaz" Ignotas
+// (c) Copyright 2007-2009 Grazvydas "notaz" Ignotas
 
 #define CYCLES_M68K_LINE     488 // suitable for both PAL/NTSC
 #define CYCLES_M68K_VINT_LAG  68
@@ -15,9 +15,16 @@
   }
 
 // CPUS_RUN
+#ifndef RUN_SH2S
+#define RUN_SH2S
+#endif
+
 #ifndef PICO_CD
 #define CPUS_RUN(m68k_cycles,s68k_cycles) \
-    SekRunM68k(m68k_cycles);
+{ \
+    SekRunM68k(m68k_cycles); \
+    RUN_SH2S \
+}
 #else
 #define CPUS_RUN(m68k_cycles,s68k_cycles) \
 { \
@@ -31,7 +38,6 @@
 }
 #endif
 
-// Accurate but slower frame which does hints
 static int PicoFrameHints(void)
 {
   struct PicoVideo *pv=&Pico.video;
@@ -176,6 +182,10 @@ static int PicoFrameHints(void)
   pv->status|=0x08; // go into vblank
   pv->pending_ints|=0x20;
 
+#ifdef PICO_32X
+  p32x_start_blank();
+#endif
+
   // the following SekRun is there for several reasons:
   // there must be a delay after vblank bit is set and irq is asserted (Mazin Saga)
   // also delay between F bit (bit 7) is set in SR and IRQ happens (Ex-Mutants)